1 /* $NetBSD: dma.h,v 1.2 2001/07/24 16:26:53 tsutsui Exp $ */ 2 /* $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $ */ 3 4 #ifndef __JAZZ_R4030_DMA 5 #define __JAZZ_R4030_DMA 6 7 #ifndef GXEMUL 8 #define GXEMUL 9 #endif 10 11 /* 12 * Copyright (c) 1996 Per Fogelstrom 13 * All rights reserved. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by Per Fogelstrom. 26 * 4. The name of the author may not be used to endorse or promote products 27 * derived from this software without specific prior written permission 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 31 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 32 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 33 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 34 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 38 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Hardware dma registers. 43 */ 44 typedef volatile struct { 45 int32_t dma_mode; 46 int32_t pad1; 47 int32_t dma_enab; 48 int32_t pad2; 49 int32_t dma_count; 50 int32_t pad3; 51 int32_t dma_addr; 52 int32_t pad4; 53 } DmaReg, *pDmaReg; 54 55 #define R4030_DMA_MODE_40NS 0x00 /* Device dma timing */ 56 #define R4030_DMA_MODE_80NS 0x01 /* Device dma timing */ 57 #define R4030_DMA_MODE_120NS 0x02 /* Device dma timing */ 58 #define R4030_DMA_MODE_160NS 0x03 /* Device dma timing */ 59 #define R4030_DMA_MODE_200NS 0x04 /* Device dma timing */ 60 #define R4030_DMA_MODE_240NS 0x05 /* Device dma timing */ 61 #define R4030_DMA_MODE_280NS 0x06 /* Device dma timing */ 62 #define R4030_DMA_MODE_320NS 0x07 /* Device dma timing */ 63 #define R4030_DMA_MODE_8 0x08 /* Device 8 bit */ 64 #define R4030_DMA_MODE_16 0x10 /* Device 16 bit */ 65 #define R4030_DMA_MODE_32 0x18 /* Device 32 bit */ 66 #define R4030_DMA_MODE_INT 0x20 /* Interrupt when done */ 67 #define R4030_DMA_MODE_BURST 0x40 /* Burst mode (Rev 2 only) */ 68 #define R4030_DMA_MODE_FAST 0x80 /* Fast dma cycle (Rev 2 only) */ 69 #define R4030_DMA_MODE 0xff /* Mode register bits */ 70 #define DMA_DIR_WRITE 0x100 /* Software direction status */ 71 #define DMA_DIR_READ 0x000 /* Software direction status */ 72 73 #define R4030_DMA_ENAB_RUN 0x01 /* Enable dma */ 74 #define R4030_DMA_ENAB_READ 0x00 /* Read from device */ 75 #define R4030_DMA_ENAB_WRITE 0x02 /* Write to device */ 76 #define R4030_DMA_ENAB_TC_IE 0x100 /* Terminal count int enable */ 77 #define R4030_DMA_ENAB_ME_IE 0x200 /* Memory error int enable */ 78 #define R4030_DMA_ENAB_TL_IE 0x400 /* Translation limit int enable */ 79 80 #define R4030_DMA_COUNT_MASK 0x000fffff /* Byte count mask */ 81 82 /* 83 * Structure used to control dma. 84 */ 85 86 #ifndef GXEMUL 87 typedef struct dma_softc { 88 struct device sc_dev; /* use as a device */ 89 struct esp_softc *sc_esp; 90 bus_addr_t dma_va; /* Viritual address for transfer */ 91 int mode; /* Mode register value and direction */ 92 jazz_dma_pte_t *pte_base; /* Pointer to dma tlb array */ 93 int pte_size; /* Size of pte allocated pte array */ 94 pDmaReg dma_reg; /* Pointer to dma registers */ 95 int sc_active; /* Active flag */ 96 void (*reset)(struct dma_softc *); /* Reset routine pointer */ 97 void (*enintr)(struct dma_softc *); /* Int enab routine pointer */ 98 void (*map)(struct dma_softc *, char *, size_t, int); 99 /* Map a dma viritual area */ 100 void (*start)(struct dma_softc *, caddr_t, size_t, int); 101 /* Start routine pointer */ 102 int (*isintr)(struct dma_softc *); /* Int check routine pointer */ 103 int (*intr)(struct dma_softc *); /* Interrupt routine pointer */ 104 void (*end)(struct dma_softc *); /* Interrupt routine pointer */ 105 } dma_softc_t; 106 #endif /* not in gxemul */ 107 108 #define DMA_TO_DEV 0 109 #define DMA_FROM_DEV 1 110 111 #define DMA_RESET(r) ((r->reset)(r)) 112 #define DMA_START(a, b, c, d) ((a->start)(a, b, c, d)) 113 #define DMA_MAP(a, b, c, d) ((a->map)(a, b, c, d)) 114 #define DMA_INTR(r) ((r->intr)(r)) 115 #define DMA_DRAIN(r) 116 #define DMA_END(r) ((r->end)(r)) 117 118 #ifndef GXEMUL 119 void picaDmaInit __P((void)); 120 void picaDmaTLBAlloc __P((dma_softc_t *)); 121 void picaDmaTLBFree __P((dma_softc_t *)); 122 void picaDmaMap __P((struct dma_softc *, char *, size_t, int)); 123 void picaDmaStart __P((struct dma_softc *, char *, size_t, int)); 124 void picaDmaFlush __P((struct dma_softc *, char *, size_t, int)); 125 void asc_dma_init __P((struct dma_softc *)); 126 void fdc_dma_init __P((struct dma_softc *)); 127 #endif /* not in gxemul */ 128 129 #endif /* __JAZZ_R4030_DMA */ 130