1 // license:BSD-3-Clause
2 // copyright-holders:Patrick Mackinlay
3
4 /*
5 * TODO
6 * - enforce "should be zero" fields
7 * - enforce "Ra must be R31"
8 * - assembly and register naming preferences
9 * - implementation-dependent instructions for EV5 and EV6
10 */
11
12 #include "emu.h"
13 #include "alphad.h"
14 #include "common.h"
15
16 // instruction formats
17 #define OPERATE_RRR(opcode, ra, rb, rc) util::stream_format(stream, "%-10s %s, %s, %s", opcode, R[ra], R[rb], R[rc])
18 #define OPERATE_FFF(opcode, ra, rb, rc) util::stream_format(stream, "%-10s %s, %s, %s", opcode, F[ra], F[rb], F[rc])
19 #define OPERATE_RIR(opcode, ra, im, rc) util::stream_format(stream, "%-10s %s, #%d, %s", opcode, R[ra], im, R[rc])
20 #define OPERATE_RR(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s", opcode, R[rb], R[rc])
21 #define OPERATE_FF(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s", opcode, F[rb], F[rc])
22 #define OPERATE_RF(opcode, ra, rc) util::stream_format(stream, "%-10s %s, %s", opcode, R[ra], F[rc])
23 #define OPERATE_FR(opcode, ra, rc) util::stream_format(stream, "%-10s %s, %s", opcode, F[ra], R[rc])
24 #define OPERATE_IR(opcode, im, rc) util::stream_format(stream, "%-10s #%d, %s", opcode, im, R[rc])
25 #define OPERATE_R(opcode, rc) util::stream_format(stream, "%-10s %s", opcode, R[rc])
26 #define OPERATE_F(opcode, rc) util::stream_format(stream, "%-10s %s", opcode, F[rc])
27
28 // TODO: verify syntax for multiple register formats
29 #define OPERATE_RI(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s", opcode, R[rb], IBX[rc])
30 #define OPERATE_RA(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s", opcode, R[rb], ABX[rc])
31 #define OPERATE_RAI(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s:%s", opcode, R[rb], ABX[rc], IBX[rc])
32 #define OPERATE_RP(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s", opcode, R[rb], PT[rc])
33 #define OPERATE_RPI(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s:%s", opcode, R[rb], PT[rc], IBX[rc])
34 #define OPERATE_RPA(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s:%s", opcode, R[rb], PT[rc], ABX[rc])
35 #define OPERATE_RPAI(opcode, rb, rc) util::stream_format(stream, "%-10s %s, %s:%s:%s", opcode, R[rb], PT[rc], ABX[rc], IBX[rc])
36
37 #define MEMORY_R(opcode, ra, disp, rb) util::stream_format(stream, "%-10s %s, %d(%s)", opcode, R[ra], disp, R[rb])
38 #define MEMORY_F(opcode, ra, disp, rb) util::stream_format(stream, "%-10s %s, %d(%s)", opcode, F[ra], disp, R[rb])
39 #define BRANCH_R(opcode, ra, offset) util::stream_format(stream, "%-10s %s, 0x%x", opcode, R[ra], pc + 4 + offset)
40 #define BRANCH_F(opcode, ra, offset) util::stream_format(stream, "%-10s %s, 0x%x", opcode, F[ra], pc + 4 + offset)
41 #define BRANCH(opcode, offset) util::stream_format(stream, "%-10s 0x%x", opcode, pc + 4 + offset)
42
43 #define JUMP(opcode, ra, rb) util::stream_format(stream, "%-10s %s, (%s)", opcode, R[ra], R[rb])
44
45 #define MISC(opcode) util::stream_format(stream, "%-10s", opcode)
46 #define MISC_R(opcode, ra) util::stream_format(stream, "%-10s %s", opcode, R[ra])
47 #define MISC_M(opcode, rb) util::stream_format(stream, "%-10s (%s)", opcode, R[rb])
48
49 #define CALL_PAL(fnc) util::stream_format(stream, "%-10s %s", "call_pal", fnc)
50
51 #define RESERVED(opcode) util::stream_format(stream, "%-10s", opcode)
52 #define UNKNOWN(type) util::stream_format(stream, "unknown %s", type)
53
54 // register names
55 const char *const alpha_disassembler::R[] =
56 {
57 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
58 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
59 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
60 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
61 };
62
63 const char *const alpha_disassembler::F[] =
64 {
65 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
66 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
67 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
68 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
69 };
70
71 const char *const alpha_disassembler::PT[] =
72 {
73 "pt0", "pt1", "pt2", "pt3", "pt4", "pt5", "pt6", "pt7",
74 "pt8", "pt9", "pt10", "pt11", "pt12", "pt13", "pt14", "pt15",
75 "pt16", "pt17", "pt18", "pt19", "pt20", "pt21", "pt22", "pt23",
76 "pt24", "pt25", "pt26", "pt27", "pt28", "pt29", "pt30", "pt31"
77 };
78
79 // NOTE: ABXn and IBXn are placeholders for undefined/unused registers
80 const char *const alpha_disassembler::ABX[] =
81 {
82 "TB_CTL", "ABX1", "DTB_PTE", "DTB_PTE_TEMP", "MM_CSR", "VA", "DTBZAP", "DTBASM",
83 "DTBIS", "BIU_ADDR", "BIU_STAT", "ABX12", "DC_STAT", "FILL_ADDR", "ABOX_CTL", "ALT_MODE",
84 "CC", "CC_CTL", "BIU_CTL", "FILL_SYNDROME", "BC_TAG", "FLUSH_IC", "ABX22", "FLUSH_IC_ASM",
85 "ABX24", "ABX25", "ABX26", "ABX27", "ABX28", "ABX29", "ABX30", "ABX31"
86 };
87
88 const char *const alpha_disassembler::IBX[] =
89 {
90 "TB_TAG", "ITB_PTE", "ICCSR", "ITB_PTE_TEMP", "EXC_ADDR", "SL_RCV", "ITBZAP", "ITBASM",
91 "ITBIS", "PS", "EXC_SUM", "PAL_BASE", "HIRR", "SIRR", "ASTRR", "IBX15",
92 "HIERR", "SIER", "ASTER", "SL_CLR", "IBX20", "IBX21", "SL_XMIT", "IBX23",
93 "IBX24", "IBX25", "IBX26", "IBX27", "IBX28", "IBX29", "IBX30", "IBX31"
94 };
95
disassemble(std::ostream & stream,offs_t pc,const data_buffer & opcodes,const data_buffer & params)96 offs_t alpha_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms)
97 {
98 offs_t const bytes = 4;
99 u32 flags = SUPPORTED;
100
101 u32 const instruction = opcodes.r32(pc);
102
103 switch (instruction >> 26)
104 {
105 // pal format
106 case 0x00:
107 switch (m_dasm_type)
108 {
109 case TYPE_UNKNOWN:
110 switch (instruction & 0x03ffffff)
111 {
112 case 0x0000: CALL_PAL("halt"); break;
113 case 0x0002: CALL_PAL("draina"); break;
114 case 0x0086: CALL_PAL("imb"); break;
115
116 default: UNKNOWN("call_pal"); break;
117 }
118 break;
119
120 case TYPE_NT:
121 switch (instruction & 0x03ffffff)
122 {
123 // Windows NT unprivileged PALcode
124 case 0x0080: CALL_PAL("bpt"); break; // breakpoint trap
125 case 0x0083: CALL_PAL("callsys"); break; // call system service
126 case 0x0086: CALL_PAL("imb"); break; // instruction memory barrier
127 case 0x00aa: CALL_PAL("gentrap"); break; // generate trap
128 case 0x00ab: CALL_PAL("rdteb"); break; // read TEB internal processor register
129 case 0x00ac: CALL_PAL("kbpt"); break; // kernel breakpoint trap
130 case 0x00ad: CALL_PAL("callkd"); break; // call kernel debugger
131
132 // Windows NT privileged PALcode
133 case 0x0000: CALL_PAL("halt"); break; // trap to illegal instruction
134 case 0x0001: CALL_PAL("restart"); break; // restart the processor
135 case 0x0002: CALL_PAL("draina"); break; // drain aborts
136 case 0x0003: CALL_PAL("reboot"); break; // transfer to console firmware
137 case 0x0004: CALL_PAL("initpal"); break; // initialize the PALcode
138 case 0x0005: CALL_PAL("wrentry"); break; // write system entry
139 case 0x0006: CALL_PAL("swpirql"); break; // swap IRQL
140 case 0x0007: CALL_PAL("rdirql"); break; // read current IRQL
141 case 0x0008: CALL_PAL("di"); break; // disable interrupts
142 case 0x0009: CALL_PAL("ei"); break; // enable interrupts
143 case 0x000a: CALL_PAL("swppal"); break; // swap PALcode
144 case 0x000c: CALL_PAL("ssir"); break; // set software interrupt request
145 case 0x000d: CALL_PAL("csir"); break; // clear software interrupt request
146 case 0x000e: CALL_PAL("rfe"); break; // return from exception
147 case 0x000f: CALL_PAL("retsys"); break; // return from system service call
148 case 0x0010: CALL_PAL("swpctx"); break; // swap privileged thread context
149 case 0x0011: CALL_PAL("swpprocess"); break; // swap privileged process context
150 case 0x0012: CALL_PAL("rdmces"); break; // read machine check error summary
151 case 0x0013: CALL_PAL("wrmces"); break; // write machine check error summary
152 case 0x0014: CALL_PAL("tbia"); break; // translation buffer invalidate all
153 case 0x0015: CALL_PAL("tbis"); break; // translation buffer invalidate single
154 case 0x0016: CALL_PAL("dtbis"); break; // data translation buffer invalidate single
155 case 0x0017: CALL_PAL("tbisasn"); break; // translation buffer invalidate single ASN
156 case 0x0018: CALL_PAL("rdksp"); break; // read initial kernel stack
157 case 0x0019: CALL_PAL("swpksp"); break; // swap initial kernel stack
158 case 0x001a: CALL_PAL("rdpsr"); break; // read processor status register
159 case 0x001c: CALL_PAL("rdpcr"); break; // read PCR (processor control registers)
160 case 0x001e: CALL_PAL("rdthread"); break; // read the current thread value
161 case 0x0020: CALL_PAL("wrperfmon"); break; // write performance monitoring values
162 case 0x0030: CALL_PAL("rdcounters"); break; // read PALcode event counters
163 case 0x0031: CALL_PAL("rdstate"); break; // read internal processor state
164
165 default: UNKNOWN("call_pal"); break;
166 }
167 break;
168
169 case TYPE_UNIX:
170 switch (instruction & 0x03ffffff)
171 {
172 // Digital UNIX unprivileged PALcode
173 case 0x0080: CALL_PAL("bpt"); break; // breakpoint trap
174 case 0x0081: CALL_PAL("bugchk"); break; // bugcheck
175 case 0x0083: CALL_PAL("callsys"); break; // system call
176 case 0x0086: CALL_PAL("imb"); break; // i-stream memory barrier
177 case 0x0092: CALL_PAL("urti"); break; // return from user mode trap
178 case 0x009e: CALL_PAL("rdunique"); break; // read unique value
179 case 0x009f: CALL_PAL("wrunique"); break; // write unique value
180 case 0x00aa: CALL_PAL("gentrap"); break; // generate software trap
181 case 0x00ae: CALL_PAL("clrfen"); break; // clear floating-point enable
182
183 // Digital UNIX privileged PALcode
184 case 0x0000: CALL_PAL("halt"); break; // halt the processor
185 case 0x0001: CALL_PAL("cflush"); break; // cache flush
186 case 0x0002: CALL_PAL("draina"); break; // drain aborts
187 case 0x0009: CALL_PAL("cserve"); break; // console service
188 case 0x000a: CALL_PAL("swppal"); break; // swap PALcode image
189 case 0x000d: CALL_PAL("wripir"); break; // write interprocessor interrupt request
190 case 0x0010: CALL_PAL("rdmces"); break; // read machine check error summary register
191 case 0x0011: CALL_PAL("wrmces"); break; // write machine check error summary register
192 case 0x002b: CALL_PAL("wrfen"); break; // write floating-point enable
193 case 0x002d: CALL_PAL("wrvptptr"); break; // write virtual page table pointer
194 case 0x0030: CALL_PAL("swpctx"); break; // swap privileged context
195 case 0x0031: CALL_PAL("wrval"); break; // write system value
196 case 0x0032: CALL_PAL("rdval"); break; // read system value
197 case 0x0033: CALL_PAL("tbi"); break; // translation buffer invalidate
198 case 0x0034: CALL_PAL("wrent"); break; // write system entry address
199 case 0x0035: CALL_PAL("swpipl"); break; // swap interrupt priority level
200 case 0x0036: CALL_PAL("rdps"); break; // read processor status
201 case 0x0037: CALL_PAL("wrkgp"); break; // write kernel global pointer
202 case 0x0038: CALL_PAL("wrusp"); break; // write user stack pointer
203 case 0x0039: CALL_PAL("wrperfmon"); break; // performance monitoring function
204 case 0x003a: CALL_PAL("rdusp"); break; // read user stack pointer
205 case 0x003c: CALL_PAL("whami"); break; // who am I
206 case 0x003d: CALL_PAL("retsys"); break; // return from system call
207 case 0x003e: CALL_PAL("wtint"); break; // wait for interrupt
208 case 0x003f: CALL_PAL("rti"); break; // return from trap or interrupt
209
210 default: UNKNOWN("call_pal"); break;
211 }
212 break;
213
214 case TYPE_VMS:
215 switch (instruction & 0x03ffffff)
216 {
217 // OpenVMS unprivileged PALcode
218 case 0x0080: CALL_PAL("bpt"); break; // breakpoint
219 case 0x0081: CALL_PAL("bugchk"); break; // bugcheck
220 case 0x0082: CALL_PAL("chme"); break; // change mode to executive
221 case 0x0083: CALL_PAL("chmk"); break; // change mode to kernel
222 case 0x0084: CALL_PAL("chms"); break; // change mode to supervisor
223 case 0x0085: CALL_PAL("chmu"); break; // change mode to user
224 case 0x0086: CALL_PAL("imb"); break; // i-stream memory barrier
225 case 0x0087: CALL_PAL("insqhil"); break; // insert into longword queue at head interlocked
226 case 0x0088: CALL_PAL("insqtil"); break; // insert into longword queue at tail interlocked
227 case 0x0089: CALL_PAL("insqhiq"); break; // insert into quadword queue at head interlocked
228 case 0x008a: CALL_PAL("insqtiq"); break; // insert into quadword queue at tail interlocked
229 case 0x008b: CALL_PAL("insquel"); break; // insert entry into longword queue
230 case 0x008c: CALL_PAL("insqueq"); break; // insert entry into quadword queue
231 case 0x008d: CALL_PAL("insquel/d"); break; // insert entry into longword queue deferred
232 case 0x008e: CALL_PAL("insqueq/d"); break; // insert entry into quadword queue deferred
233 case 0x008f: CALL_PAL("prober"); break; // probe for read access
234 case 0x0090: CALL_PAL("probew"); break; // probe for write access
235 case 0x0091: CALL_PAL("rd_ps"); break; // move processor status
236 case 0x0092: CALL_PAL("rei"); break; // return from exception or interrupt
237 case 0x0093: CALL_PAL("remqhil"); break; // remove from longword queue at head interlocked
238 case 0x0094: CALL_PAL("remqtil"); break; // remove from longword queue at tail interlocked
239 case 0x0095: CALL_PAL("remqhiq"); break; // remove from quadword queue at head interlocked
240 case 0x0096: CALL_PAL("remqtiq"); break; // remove from quadword queue at tail interlocked
241 case 0x0097: CALL_PAL("remquel"); break; // remove entry from longword queue
242 case 0x0098: CALL_PAL("remqueq"); break; // remove entry from quadword queue
243 case 0x0099: CALL_PAL("remquel/d"); break; // remove entry from longword queue deferred
244 case 0x009a: CALL_PAL("remqueq/d"); break; // remove entry from quadword queue deferred
245 case 0x009b: CALL_PAL("swasten"); break; // swap AST enable for current mode
246 case 0x009c: CALL_PAL("wr_ps_sw"); break; // write processor status software field
247 case 0x009d: CALL_PAL("rscc"); break; // read system cycle counter
248 case 0x009e: CALL_PAL("read_unq"); break; // read unique context
249 case 0x009f: CALL_PAL("write_unq"); break; // write unique context
250 case 0x00a0: CALL_PAL("amovrr"); break; // atomic move from register to register
251 case 0x00a1: CALL_PAL("amovrm"); break; // atomic move from register to memory
252 case 0x00a2: CALL_PAL("insqhilr"); break; // insert into longword queue at head interlocked resident
253 case 0x00a3: CALL_PAL("insqtilr"); break; // insert into longword queue at tail interlocked resident
254 case 0x00a4: CALL_PAL("insqhiqr"); break; // insert into quadword queue at head interlocked resident
255 case 0x00a5: CALL_PAL("insqtiqr"); break; // insert into quadword queue at tail interlocked resident
256 case 0x00a6: CALL_PAL("remqhilr"); break; // remove from longword queue at head interlocked resident
257 case 0x00a7: CALL_PAL("remqtilr"); break; // remove from longword queue at tail interlocked resident
258 case 0x00a8: CALL_PAL("remqhiqr"); break; // remove from quadword queue at head interlocked resident
259 case 0x00a9: CALL_PAL("remqtiqr"); break; // remove from quadword queue at tail interlocked resident
260 case 0x00aa: CALL_PAL("gentrap"); break; // generate software trap
261 case 0x00ae: CALL_PAL("clrfen"); break; // clear floating-point enable
262
263 // OpenVMS privileged PALcode
264 case 0x0000: CALL_PAL("halt"); break; // halt processor
265 case 0x0001: CALL_PAL("cflush"); break; // cache flush
266 case 0x0002: CALL_PAL("draina"); break; // drain aborts
267 case 0x0003: CALL_PAL("ldqp"); break; // load quadword physical
268 case 0x0004: CALL_PAL("stqp"); break; // store quadword physical
269 case 0x0005: CALL_PAL("swpctx"); break; // swap privileged context
270 case 0x0006: CALL_PAL("mfpr_asn"); break; // move from processor register ASN
271 case 0x0009: CALL_PAL("cserve"); break; // console service
272 case 0x000a: CALL_PAL("swppal"); break; // swap PALcode image
273 case 0x000b: CALL_PAL("mfpr_fen"); break; // move from processor register FEN
274 case 0x000c: CALL_PAL("mtpr_fen"); break; // move to processor register FEN
275 case 0x000d: CALL_PAL("mtpr_ipir"); break; // move to processor register IPRI
276 case 0x000e: CALL_PAL("mfpr_ipl"); break; // move from processor register IPL
277 case 0x000f: CALL_PAL("mtpr_ipl"); break; // move to processor register IPL
278 case 0x0010: CALL_PAL("mfpr_mces"); break; // move from processor register MCES
279 case 0x0011: CALL_PAL("mtpr_mces"); break; // move to processor register MCES
280 case 0x0012: CALL_PAL("mfpr_pcbb"); break; // move from processor register PCBB
281 case 0x0013: CALL_PAL("mfpr_prbr"); break; // move from processor register PRBR
282 case 0x0014: CALL_PAL("mtpr_prbr"); break; // move to processor register PRBR
283 case 0x0015: CALL_PAL("mfpr_ptbr"); break; // move from processor register PTBR
284 case 0x0016: CALL_PAL("mfpr_scbb"); break; // move from processor register SCBB
285 case 0x0017: CALL_PAL("mtpr_scbb"); break; // move to processor register SCBB
286 case 0x0018: CALL_PAL("mtpr_sirr"); break; // move to processor register SIRR
287 case 0x0019: CALL_PAL("mfpr_sisr"); break; // move from processor register SISR
288 case 0x001a: CALL_PAL("mfpr_tbchk"); break; // move from processor register TBCHK
289 case 0x001b: CALL_PAL("mtpr_tbia"); break; // move to processor register TBIA
290 case 0x001c: CALL_PAL("mtpr_tbiap"); break; // move to processor register TBIAP
291 case 0x001d: CALL_PAL("mtpr_tbis"); break; // move to processor register TBIS
292 case 0x001e: CALL_PAL("mfpr_esp"); break; // move from processor register ESP
293 case 0x001f: CALL_PAL("mtpr_esp"); break; // move to processor register ESP
294 case 0x0020: CALL_PAL("mfpr_ssp"); break; // move from processor register SSP
295 case 0x0021: CALL_PAL("mtpr_ssp"); break; // move to processor register SSP
296 case 0x0022: CALL_PAL("mfpr_usp"); break; // move from processor register USP
297 case 0x0023: CALL_PAL("mtpr_usp"); break; // move to processor register USP
298 case 0x0024: CALL_PAL("mtpr_tbisd"); break; // move to processor register TBISD
299 case 0x0025: CALL_PAL("mtpr_tbisi"); break; // move to processor register TBISI
300 case 0x0026: CALL_PAL("mtpr_asten"); break; // move to processor register ASTEN
301 case 0x0027: CALL_PAL("mtpr_astsr"); break; // move to processor register ASTSR
302 case 0x0029: CALL_PAL("mfpr_vptb"); break; // move from processor register VPTB
303 case 0x002a: CALL_PAL("mtpr_vptb"); break; // move to processor register VPTB
304 case 0x002b: CALL_PAL("mtpr_perfmon"); break; // move to processor register PERFMON
305 case 0x002e: CALL_PAL("mtpr_datfx"); break; // move to processor register DATFX
306 case 0x003e: CALL_PAL("wtint"); break; // wait for interrupt
307 case 0x003f: CALL_PAL("mfpr_whami"); break; // move from processor register WHAMI
308
309 default: UNKNOWN("call_pal"); break;
310 }
311 break;
312 }
313 break;
314
315 // reserved opcodes
316 case 0x01: RESERVED("opc01"); break; // OPC01
317 case 0x02: RESERVED("opc02"); break; // OPC02
318 case 0x03: RESERVED("opc03"); break; // OPC03
319 case 0x04: RESERVED("opc04"); break; // OPC04
320 case 0x05: RESERVED("opc05"); break; // OPC05
321 case 0x06: RESERVED("opc06"); break; // OPC06
322 case 0x07: RESERVED("opc07"); break; // OPC07
323
324 // memory format
325 case 0x08:
326 if (Rb(instruction) == 31)
327 OPERATE_IR("mov", Disp_M(instruction), Ra(instruction));
328 else
329 MEMORY_R("lda", Ra(instruction), Disp_M(instruction), Rb(instruction)); // LDA
330 break;
331 case 0x09: MEMORY_R("ldah", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDAH
332 case 0x0a: MEMORY_R("ldbu", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDBU (BWX)
333 case 0x0b:
334 if (Ra(instruction) == 31 && Disp_M(instruction) == 0)
335 MISC("unop");
336 else
337 MEMORY_R("ldq_u", Ra(instruction), Disp_M(instruction), Rb(instruction)); // LDQ_U
338 break;
339 case 0x0c: MEMORY_R("ldwu", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDWU (BWX)
340 case 0x0d: MEMORY_R("stw", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STW (BWX)
341 case 0x0e: MEMORY_R("stb", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STB (BWX)
342 case 0x0f: MEMORY_R("stq_u", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STQ_U
343
344 // operate format
345 case 0x10: // INTA* (integer arithmetic)
346 switch ((instruction >> 5) & 0xff)
347 {
348 // register variants
349 case 0x00:
350 if (Ra(instruction) == 31)
351 OPERATE_RR("sextl", Rb(instruction), Rc(instruction));
352 else
353 OPERATE_RRR("addl", Ra(instruction), Rb(instruction), Rc(instruction)); // ADDL
354 break;
355 case 0x02: OPERATE_RRR("s4addl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S4ADDL
356 case 0x09:
357 if (Ra(instruction) == 31)
358 OPERATE_RR("negl", Rb(instruction), Rc(instruction));
359 else
360 OPERATE_RRR("subl", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBL
361 break;
362 case 0x0b: OPERATE_RRR("s4subl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S4SUBL
363 case 0x0f: OPERATE_RRR("cmpbge", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPBGE
364 case 0x12: OPERATE_RRR("s8addl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S8ADDL
365 case 0x1b: OPERATE_RRR("s8subl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S8SUBL
366 case 0x1d: OPERATE_RRR("cmpult", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPULT
367 case 0x20: OPERATE_RRR("addq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDQ
368 case 0x22: OPERATE_RRR("s4addq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S4ADDQ
369 case 0x29:
370 if (Ra(instruction) == 31)
371 OPERATE_RR("negq", Rb(instruction), Rc(instruction));
372 else
373 OPERATE_RRR("subq", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBQ
374 break;
375 case 0x2b: OPERATE_RRR("s4subq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S4SUBQ
376 case 0x2d: OPERATE_RRR("cmpeq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPEQ
377 case 0x32: OPERATE_RRR("s8addq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S8ADDQ
378 case 0x3b: OPERATE_RRR("s8subq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // S8SUBQ
379 case 0x3d: OPERATE_RRR("cmpule", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPULE
380 case 0x40: OPERATE_RRR("addl/v", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDL/V
381 case 0x49:
382 if (Ra(instruction) == 31)
383 OPERATE_RR("negl/v", Rb(instruction), Rc(instruction));
384 else
385 OPERATE_RRR("subl/v", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBL/V
386 break;
387 case 0x4d: OPERATE_RRR("cmplt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPLT
388 case 0x60: OPERATE_RRR("addq/v", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDQ/V
389 case 0x69:
390 if (Ra(instruction) == 31)
391 OPERATE_RR("negq/v", Rb(instruction), Rc(instruction));
392 else
393 OPERATE_RRR("subq/v", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBQ/V
394 break;
395 case 0x6d: OPERATE_RRR("cmple", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPLE
396
397 // immediate variants
398 case 0x80:
399 if (Ra(instruction) == 31)
400 OPERATE_IR("sextl", Im(instruction), Rc(instruction));
401 else
402 OPERATE_RIR("addl", Ra(instruction), Im(instruction), Rc(instruction)); // ADDL
403 break;
404 case 0x82: OPERATE_RIR("s4addl", Ra(instruction), Im(instruction), Rc(instruction)); break; // S4ADDL
405 case 0x89:
406 if (Ra(instruction) == 31)
407 OPERATE_IR("negl", Im(instruction), Rc(instruction));
408 else
409 OPERATE_RIR("subl", Ra(instruction), Im(instruction), Rc(instruction)); // SUBL
410 break;
411 case 0x8b: OPERATE_RIR("s4subl", Ra(instruction), Im(instruction), Rc(instruction)); break; // S4SUBL
412 case 0x8f: OPERATE_RIR("cmpbge", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMPBGE
413 case 0x92: OPERATE_RIR("s8addl", Ra(instruction), Im(instruction), Rc(instruction)); break; // S8ADDL
414 case 0x9b: OPERATE_RIR("s8subl", Ra(instruction), Im(instruction), Rc(instruction)); break; // S8SUBL
415 case 0x9d: OPERATE_RIR("cmpult", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMPULT
416 case 0xa0: OPERATE_RIR("addq", Ra(instruction), Im(instruction), Rc(instruction)); break; // ADDQ
417 case 0xa2: OPERATE_RIR("s4addq", Ra(instruction), Im(instruction), Rc(instruction)); break; // S4ADDQ
418 case 0xa9:
419 if (Ra(instruction) == 31)
420 OPERATE_IR("negq", Im(instruction), Rc(instruction));
421 else
422 OPERATE_RIR("subq", Ra(instruction), Im(instruction), Rc(instruction)); // SUBQ
423 break;
424 case 0xab: OPERATE_RIR("s4subq", Ra(instruction), Im(instruction), Rc(instruction)); break; // S4SUBQ
425 case 0xad: OPERATE_RIR("cmpeq", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMPEQ
426 case 0xb2: OPERATE_RIR("s8addq", Ra(instruction), Im(instruction), Rc(instruction)); break; // S8ADDQ
427 case 0xbb: OPERATE_RIR("s8subq", Ra(instruction), Im(instruction), Rc(instruction)); break; // S8SUBQ
428 case 0xbd: OPERATE_RIR("cmpule", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMPULE
429 case 0xc0: OPERATE_RIR("addl/v", Ra(instruction), Im(instruction), Rc(instruction)); break; // ADDL/V
430 case 0xc9:
431 if (Ra(instruction) == 31)
432 OPERATE_IR("negl/v", Im(instruction), Rc(instruction));
433 else
434 OPERATE_RIR("subl/v", Ra(instruction), Im(instruction), Rc(instruction)); // SUBL/V
435 break;
436 case 0xcd: OPERATE_RIR("cmplt", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMPLT
437 case 0xe0: OPERATE_RIR("addq/v", Ra(instruction), Im(instruction), Rc(instruction)); break; // ADDQ/V
438 case 0xe9:
439 if (Ra(instruction) == 31)
440 OPERATE_IR("negq/v", Im(instruction), Rc(instruction));
441 else
442 OPERATE_RIR("subq/v", Ra(instruction), Im(instruction), Rc(instruction)); // SUBQ/V
443 break;
444 case 0xed: OPERATE_RIR("cmple", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMPLE
445
446 default: UNKNOWN("inta*"); break;
447 }
448 break;
449 case 0x11: // INTL* (integer logical)
450 switch ((instruction >> 5) & 0xff)
451 {
452 // register variants
453 case 0x00: OPERATE_RRR("and", Ra(instruction), Rb(instruction), Rc(instruction)); break; // AND
454 case 0x08: OPERATE_RRR("bic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // BIC
455 case 0x14: OPERATE_RRR("cmovlbs", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVLBS
456 case 0x16: OPERATE_RRR("cmovlbc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVLBC
457 case 0x20:
458 if (Ra(instruction) == 31 && Rb(instruction) == 31 && Rc(instruction) == 31)
459 MISC("nop");
460 else if (Ra(instruction) == 31 && Rb(instruction) == 31)
461 OPERATE_R("clr", Rc(instruction));
462 else if (Ra(instruction) == Rb(instruction))
463 OPERATE_RR("mov", Rb(instruction), Rc(instruction));
464 else
465 OPERATE_RRR("bis", Ra(instruction), Rb(instruction), Rc(instruction)); // BIS
466 break;
467 case 0x24: OPERATE_RRR("cmoveq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVEQ
468 case 0x26: OPERATE_RRR("cmovne", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVNE
469 case 0x28:
470 if (Ra(instruction) == 31)
471 OPERATE_RR("not", Rb(instruction), Rc(instruction));
472 else
473 OPERATE_RRR("ornot", Ra(instruction), Rb(instruction), Rc(instruction)); // ORNOT
474 break;
475 case 0x40: OPERATE_RRR("xor", Ra(instruction), Rb(instruction), Rc(instruction)); break; // XOR
476 case 0x44: OPERATE_RRR("cmovlt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVLT
477 case 0x46: OPERATE_RRR("cmovge", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVGE
478 case 0x48: OPERATE_RRR("eqv", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EQV
479 case 0x61: OPERATE_RR("amask", Rb(instruction), Rc(instruction)); break; // AMASK
480 case 0x64: OPERATE_RRR("cmovle", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVLE
481 case 0x66: OPERATE_RRR("cmovgt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMOVGT
482
483 // immediate variants
484 case 0x80: OPERATE_RIR("and", Ra(instruction), Im(instruction), Rc(instruction)); break; // AND
485 case 0x88: OPERATE_RIR("bic", Ra(instruction), Im(instruction), Rc(instruction)); break; // BIC
486 case 0x94: OPERATE_RIR("cmovlbs", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVLBS
487 case 0x96: OPERATE_RIR("cmovlbc", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVLBC
488 case 0xa0:
489 if (Ra(instruction) == 31)
490 OPERATE_IR("mov", Im(instruction), Rc(instruction));
491 else
492 OPERATE_RIR("bis", Ra(instruction), Im(instruction), Rc(instruction)); // BIS
493 break;
494 case 0xa4: OPERATE_RIR("cmoveq", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVEQ
495 case 0xa6: OPERATE_RIR("cmovne", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVNE
496 case 0xa8:
497 if (Ra(instruction) == 31)
498 OPERATE_IR("not", Im(instruction), Rc(instruction));
499 else
500 OPERATE_RIR("ornot", Ra(instruction), Im(instruction), Rc(instruction)); // ORNOT
501 break;
502 case 0xc0: OPERATE_RIR("xor", Ra(instruction), Im(instruction), Rc(instruction)); break; // XOR
503 case 0xc4: OPERATE_RIR("cmovlt", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVLT
504 case 0xc6: OPERATE_RIR("cmovge", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVGE
505 case 0xc8: OPERATE_RIR("eqv", Ra(instruction), Im(instruction), Rc(instruction)); break; // EQV
506 case 0xe1: OPERATE_IR("amask", Im(instruction), Rc(instruction)); break; // AMASK
507 case 0xe4: OPERATE_RIR("cmovle", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVLE
508 case 0xe6: OPERATE_RIR("cmovgt", Ra(instruction), Im(instruction), Rc(instruction)); break; // CMOVGT
509
510 // TODO: Rb must be literal #1?
511 case 0xec: OPERATE_R("implver", Rc(instruction)); break; // IMPLVER
512
513 default: UNKNOWN("intl*"); break;
514 }
515 break;
516 case 0x12: // INTS* (integer shift)
517 switch ((instruction >> 5) & 0xff)
518 {
519 // register variants
520 case 0x02: OPERATE_RRR("mskbl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKBL
521 case 0x06: OPERATE_RRR("extbl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTBL
522 case 0x0b: OPERATE_RRR("insbl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSBL
523 case 0x12: OPERATE_RRR("mskwl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKWL
524 case 0x16: OPERATE_RRR("extwl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTWL
525 case 0x1b: OPERATE_RRR("inswl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSWL
526 case 0x22: OPERATE_RRR("mskll", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKLL
527 case 0x26: OPERATE_RRR("extll", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTLL
528 case 0x2b: OPERATE_RRR("insll", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSLL
529 case 0x30: OPERATE_RRR("zap", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ZAP
530 case 0x31: OPERATE_RRR("zapnot", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ZAPNOT
531 case 0x32: OPERATE_RRR("mskql", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKQL
532 case 0x34: OPERATE_RRR("srl", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SRL
533 case 0x36: OPERATE_RRR("extql", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTQL
534 case 0x39: OPERATE_RRR("sll", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SLL
535 case 0x3b: OPERATE_RRR("insql", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSQL
536 case 0x3c: OPERATE_RRR("sra", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SRA
537 case 0x52: OPERATE_RRR("mskwh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKWH
538 case 0x57: OPERATE_RRR("inswh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSWH
539 case 0x5a: OPERATE_RRR("extwh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTWH
540 case 0x62: OPERATE_RRR("msklh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKLH
541 case 0x67: OPERATE_RRR("inslh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSLH
542 case 0x6a: OPERATE_RRR("extlh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTLH
543 case 0x72: OPERATE_RRR("mskqh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MSKQH
544 case 0x77: OPERATE_RRR("insqh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // INSQH
545 case 0x7a: OPERATE_RRR("extqh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // EXTQH
546
547 // immediate variants
548 case 0x82: OPERATE_RIR("mskbl", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKBL
549 case 0x86: OPERATE_RIR("extbl", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTBL
550 case 0x8b: OPERATE_RIR("insbl", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSBL
551 case 0x92: OPERATE_RIR("mskwl", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKWL
552 case 0x96: OPERATE_RIR("extwl", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTWL
553 case 0x9b: OPERATE_RIR("inswl", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSWL
554 case 0xa2: OPERATE_RIR("mskll", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKLL
555 case 0xa6: OPERATE_RIR("extll", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTLL
556 case 0xab: OPERATE_RIR("insll", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSLL
557 case 0xb0: OPERATE_RIR("zap", Ra(instruction), Im(instruction), Rc(instruction)); break; // ZAP
558 case 0xb1: OPERATE_RIR("zapnot", Ra(instruction), Im(instruction), Rc(instruction)); break; // ZAPNOT
559 case 0xb2: OPERATE_RIR("mskql", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKQL
560 case 0xb4: OPERATE_RIR("srl", Ra(instruction), Im(instruction), Rc(instruction)); break; // SRL
561 case 0xb6: OPERATE_RIR("extql", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTQL
562 case 0xb9: OPERATE_RIR("sll", Ra(instruction), Im(instruction), Rc(instruction)); break; // SLL
563 case 0xbb: OPERATE_RIR("insql", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSQL
564 case 0xbc: OPERATE_RIR("sra", Ra(instruction), Im(instruction), Rc(instruction)); break; // SRA
565 case 0xd2: OPERATE_RIR("mskwh", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKWH
566 case 0xd7: OPERATE_RIR("inswh", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSWH
567 case 0xda: OPERATE_RIR("extwh", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTWH
568 case 0xe2: OPERATE_RIR("msklh", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKLH
569 case 0xe7: OPERATE_RIR("inslh", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSLH
570 case 0xea: OPERATE_RIR("extlh", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTLH
571 case 0xf2: OPERATE_RIR("mskqh", Ra(instruction), Im(instruction), Rc(instruction)); break; // MSKQH
572 case 0xf7: OPERATE_RIR("insqh", Ra(instruction), Im(instruction), Rc(instruction)); break; // INSQH
573 case 0xfa: OPERATE_RIR("extqh", Ra(instruction), Im(instruction), Rc(instruction)); break; // EXTQH
574
575 default: UNKNOWN("ints*"); break;
576 }
577 break;
578 case 0x13: // INTM* (integer multiply)
579 switch ((instruction >> 5) & 0xff)
580 {
581 // register variants
582 case 0x00: OPERATE_RRR("mull", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULL
583 case 0x20: OPERATE_RRR("mulq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULQ
584 case 0x30: OPERATE_RRR("umulh", Ra(instruction), Rb(instruction), Rc(instruction)); break; // UMULH
585 case 0x40: OPERATE_RRR("mull/v", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULL/V
586 case 0x60: OPERATE_RRR("mulq/v", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULQ/V
587
588 // immediate variants
589 case 0x80: OPERATE_RIR("mull", Ra(instruction), Im(instruction), Rc(instruction)); break; // MULL
590 case 0xa0: OPERATE_RIR("mulq", Ra(instruction), Im(instruction), Rc(instruction)); break; // MULQ
591 case 0xb0: OPERATE_RIR("umulh", Ra(instruction), Im(instruction), Rc(instruction)); break; // UMULH
592 case 0xc0: OPERATE_RIR("mull/v", Ra(instruction), Im(instruction), Rc(instruction)); break; // MULL/V
593 case 0xe0: OPERATE_RIR("mulq/v", Ra(instruction), Im(instruction), Rc(instruction)); break; // MULQ/V
594
595 default: UNKNOWN("intm*"); break;
596 }
597 case 0x14: // ITFP* (integer to floating)
598 switch ((instruction >> 5) & 0x7ff)
599 {
600 case 0x004: OPERATE_RF("itofs", Ra(instruction), Rc(instruction)); break; // ITOFS
601 case 0x00a: OPERATE_FF("sqrtf/c", Rb(instruction), Rc(instruction)); break; // SQRTF/C
602 case 0x00b: OPERATE_FF("sqrts/c", Rb(instruction), Rc(instruction)); break; // SQRTS/C
603 case 0x014: OPERATE_RF("itoff", Ra(instruction), Rc(instruction)); break; // ITOFF
604 case 0x024: OPERATE_RF("itoft", Ra(instruction), Rc(instruction)); break; // ITOFT
605 case 0x02a: OPERATE_FF("sqrtg/c", Rb(instruction), Rc(instruction)); break; // SQRTG/C
606 case 0x02b: OPERATE_FF("sqrtt/c", Rb(instruction), Rc(instruction)); break; // SQRTT/C
607 case 0x04b: OPERATE_FF("sqrts/m", Rb(instruction), Rc(instruction)); break; // SQRTS/M
608 case 0x06b: OPERATE_FF("sqrtt/m", Rb(instruction), Rc(instruction)); break; // SQRTT/M
609 case 0x08a: OPERATE_FF("sqrtf", Rb(instruction), Rc(instruction)); break; // SQRTF
610 case 0x08b: OPERATE_FF("sqrts", Rb(instruction), Rc(instruction)); break; // SQRTS
611 case 0x0aa: OPERATE_FF("sqrtg", Rb(instruction), Rc(instruction)); break; // SQRTG
612 case 0x0ab: OPERATE_FF("sqrtt", Rb(instruction), Rc(instruction)); break; // SQRTT
613 case 0x0cb: OPERATE_FF("sqrts/d", Rb(instruction), Rc(instruction)); break; // SQRTS/D
614 case 0x0eb: OPERATE_FF("sqrtt/d", Rb(instruction), Rc(instruction)); break; // SQRTT/D
615 case 0x10a: OPERATE_FF("sqrtf/uc", Rb(instruction), Rc(instruction)); break; // SQRTF/UC
616 case 0x10b: OPERATE_FF("sqrts/uc", Rb(instruction), Rc(instruction)); break; // SQRTS/UC
617 case 0x12a: OPERATE_FF("sqrtg/uc", Rb(instruction), Rc(instruction)); break; // SQRTG/UC
618 case 0x12b: OPERATE_FF("sqrtt/uc", Rb(instruction), Rc(instruction)); break; // SQRTT/UC
619 case 0x14b: OPERATE_FF("sqrts/um", Rb(instruction), Rc(instruction)); break; // SQRTS/UM
620 case 0x16b: OPERATE_FF("sqrtt/um", Rb(instruction), Rc(instruction)); break; // SQRTT/UM
621 case 0x18a: OPERATE_FF("sqrtf/u", Rb(instruction), Rc(instruction)); break; // SQRTF/U
622 case 0x1aa: OPERATE_FF("sqrtg/u", Rb(instruction), Rc(instruction)); break; // SQRTG/U
623 case 0x1ab: OPERATE_FF("sqrtt/u", Rb(instruction), Rc(instruction)); break; // SQRTT/U
624 case 0x1cb: OPERATE_FF("sqrts/ud", Rb(instruction), Rc(instruction)); break; // SQRTS/UD
625 case 0x1eb: OPERATE_FF("sqrtt/ud", Rb(instruction), Rc(instruction)); break; // SQRTT/UD
626 case 0x40a: OPERATE_FF("sqrtf/sc", Rb(instruction), Rc(instruction)); break; // SQRTF/SC
627 case 0x42a: OPERATE_FF("sqrtg/sc", Rb(instruction), Rc(instruction)); break; // SQRTG/SC
628 case 0x48a: OPERATE_FF("sqrtf/s", Rb(instruction), Rc(instruction)); break; // SQRTF/S
629 case 0x4aa: OPERATE_FF("sqrtg/s", Rb(instruction), Rc(instruction)); break; // SQRTG/S
630 case 0x50a: OPERATE_FF("sqrtf/suc", Rb(instruction), Rc(instruction)); break; // SQRTF/SUC
631 case 0x50b: OPERATE_FF("sqrts/suc", Rb(instruction), Rc(instruction)); break; // SQRTS/SUC
632 case 0x52a: OPERATE_FF("sqrtg/suc", Rb(instruction), Rc(instruction)); break; // SQRTG/SUC
633 case 0x52b: OPERATE_FF("sqrtt/suc", Rb(instruction), Rc(instruction)); break; // SQRTT/SUC
634 case 0x54b: OPERATE_FF("sqrts/sum", Rb(instruction), Rc(instruction)); break; // SQRTS/SUM
635 case 0x56b: OPERATE_FF("sqrtt/sum", Rb(instruction), Rc(instruction)); break; // SQRTT/SUM
636 case 0x58a: OPERATE_FF("sqrtf/su", Rb(instruction), Rc(instruction)); break; // SQRTF/SU
637 case 0x58b: OPERATE_FF("sqrts/su", Rb(instruction), Rc(instruction)); break; // SQRTS/SU
638 case 0x5aa: OPERATE_FF("sqrtg/su", Rb(instruction), Rc(instruction)); break; // SQRTG/SU
639 case 0x5ab: OPERATE_FF("sqrtt/su", Rb(instruction), Rc(instruction)); break; // SQRTT/SU
640 case 0x5cb: OPERATE_FF("sqrts/sud", Rb(instruction), Rc(instruction)); break; // SQRTS/SUD
641 case 0x5eb: OPERATE_FF("sqrtt/sud", Rb(instruction), Rc(instruction)); break; // SQRTT/SUD
642 case 0x70b: OPERATE_FF("sqrts/suic", Rb(instruction), Rc(instruction)); break; // SQRTS/SUIC
643 case 0x72b: OPERATE_FF("sqrtt/suic", Rb(instruction), Rc(instruction)); break; // SQRTT/SUIC
644 case 0x74b: OPERATE_FF("sqrts/suim", Rb(instruction), Rc(instruction)); break; // SQRTS/SUIM
645 case 0x76b: OPERATE_FF("sqrtt/suim", Rb(instruction), Rc(instruction)); break; // SQRTT/SUIM
646 case 0x78b: OPERATE_FF("sqrts/sui", Rb(instruction), Rc(instruction)); break; // SQRTS/SUI
647 case 0x7ab: OPERATE_FF("sqrtt/sui", Rb(instruction), Rc(instruction)); break; // SQRTT/SUI
648 case 0x7cb: OPERATE_FF("sqrts/suid", Rb(instruction), Rc(instruction)); break; // SQRTS/SUID
649 case 0x7eb: OPERATE_FF("sqrtt/suid", Rb(instruction), Rc(instruction)); break; // SQRTT/SUID
650
651 default: UNKNOWN("itfp*"); break;
652 }
653 break;
654 case 0x15: // FLTV* (vax floating)
655 switch ((instruction >> 5) & 0x7ff)
656 {
657 case 0x000: OPERATE_FFF("addf/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/C
658 case 0x001: OPERATE_FFF("subf/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBF/C
659 case 0x002: OPERATE_FFF("mulf/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/C
660 case 0x003: OPERATE_FFF("divf/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/C
661 case 0x01e: OPERATE_FF("cvtdg/c", Rb(instruction), Rc(instruction)); break; // CVTDG/C
662 case 0x020: OPERATE_FFF("addg/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/C
663 case 0x021: OPERATE_FFF("subg/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBG/C
664 case 0x022: OPERATE_FFF("mulg/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/C
665 case 0x023: OPERATE_FFF("divg/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/C
666 case 0x02c: OPERATE_FF("cvtgf/c", Rb(instruction), Rc(instruction)); break; // CVTGF/C
667 case 0x02d: OPERATE_FF("cvtgd/c", Rb(instruction), Rc(instruction)); break; // CVTGD/C
668 case 0x02f: OPERATE_FF("cvtgq/c", Rb(instruction), Rc(instruction)); break; // CVTGQ/C
669 case 0x03c: OPERATE_FF("cvtqf/c", Rb(instruction), Rc(instruction)); break; // CVTQF/C
670 case 0x03e: OPERATE_FF("cvtqg/c", Rb(instruction), Rc(instruction)); break; // CVTQG/C
671 case 0x080: OPERATE_FFF("addf", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF
672 case 0x081:
673 if (Ra(instruction) == 31)
674 OPERATE_FF("negf", Rb(instruction), Rc(instruction));
675 else
676 OPERATE_FFF("subf", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBF
677 break;
678 case 0x082: OPERATE_FFF("mulf", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF
679 case 0x083: OPERATE_FFF("divf", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF
680 case 0x09e: OPERATE_FF("cvtdg", Rb(instruction), Rc(instruction)); break; // CVTDG
681 case 0x0a0: OPERATE_FFF("addg", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG
682 case 0x0a1:
683 if (Ra(instruction) == 31)
684 OPERATE_FF("negg", Rb(instruction), Rc(instruction));
685 else
686 OPERATE_FFF("subg", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBG
687 break;
688 case 0x0a2: OPERATE_FFF("mulg", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG
689 case 0x0a3: OPERATE_FFF("divg", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG
690 case 0x0a5: OPERATE_FFF("cmpgeq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPGEQ
691 case 0x0a6: OPERATE_FFF("cmpglt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPGLT
692 case 0x0a7: OPERATE_FFF("cmpgle", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPGLE
693 case 0x0ac: OPERATE_FF("cvtgf", Rb(instruction), Rc(instruction)); break; // CVTGF
694 case 0x0ad: OPERATE_FF("cvtgd", Rb(instruction), Rc(instruction)); break; // CVTGD
695 case 0x0af: OPERATE_FF("cvtgq", Rb(instruction), Rc(instruction)); break; // CVTGQ
696 case 0x0bc: OPERATE_FF("cvtqf", Rb(instruction), Rc(instruction)); break; // CVTQF
697 case 0x0be: OPERATE_FF("cvtqg", Rb(instruction), Rc(instruction)); break; // CVTQG
698 case 0x100: OPERATE_FFF("addf/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/UC
699 case 0x101: OPERATE_FFF("subf/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBF/UC
700 case 0x102: OPERATE_FFF("mulf/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/UC
701 case 0x103: OPERATE_FFF("divf/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/UC
702 case 0x11e: OPERATE_FF("cvtdg/uc", Rb(instruction), Rc(instruction)); break; // CVTDG/UC
703 case 0x120: OPERATE_FFF("addg/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/UC
704 case 0x121: OPERATE_FFF("subg/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBG/UC
705 case 0x122: OPERATE_FFF("mulg/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/UC
706 case 0x123: OPERATE_FFF("divg/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/UC
707 case 0x12c: OPERATE_FF("cvtgf/uc", Rb(instruction), Rc(instruction)); break; // CVTGF/UC
708 case 0x12d: OPERATE_FF("cvtgd/uc", Rb(instruction), Rc(instruction)); break; // CVTGD/UC
709 case 0x12f: OPERATE_FF("cvtgq/vc", Rb(instruction), Rc(instruction)); break; // CVTGQ/VC
710 case 0x180: OPERATE_FFF("addf/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/U
711 case 0x181: OPERATE_FFF("subf/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBF/U
712 case 0x182: OPERATE_FFF("mulf/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/U
713 case 0x183: OPERATE_FFF("divf/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/U
714 case 0x19e: OPERATE_FF("cvtdg/u", Rb(instruction), Rc(instruction)); break; // CVTDG/U
715 case 0x1a0: OPERATE_FFF("addg/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/U
716 case 0x1a1: OPERATE_FFF("subg/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBG/U
717 case 0x1a2: OPERATE_FFF("mulg/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/U
718 case 0x1a3: OPERATE_FFF("divg/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/U
719 case 0x1ac: OPERATE_FF("cvtgf/u", Rb(instruction), Rc(instruction)); break; // CVTGF/U
720 case 0x1ad: OPERATE_FF("cvtgd/u", Rb(instruction), Rc(instruction)); break; // CVTGD/U
721 case 0x1af: OPERATE_FF("cvtgq/v", Rb(instruction), Rc(instruction)); break; // CVTGQ/V
722 case 0x400: OPERATE_FFF("addf/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/SC
723 case 0x401: OPERATE_FFF("subf/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBF/SC
724 case 0x402: OPERATE_FFF("mulf/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/SC
725 case 0x403: OPERATE_FFF("divf/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/SC
726 case 0x41e: OPERATE_FF("cvtdg/sc", Rb(instruction), Rc(instruction)); break; // CVTDG/SC
727 case 0x420: OPERATE_FFF("addg/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/SC
728 case 0x421: OPERATE_FFF("subg/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBG/SC
729 case 0x422: OPERATE_FFF("mulg/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/SC
730 case 0x423: OPERATE_FFF("divg/sc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/SC
731 case 0x42c: OPERATE_FF("cvtgf/sc", Rb(instruction), Rc(instruction)); break; // CVTGF/SC
732 case 0x42d: OPERATE_FF("cvtgd/sc", Rb(instruction), Rc(instruction)); break; // CVTGD/SC
733 case 0x42f: OPERATE_FF("cvtgq/sc", Rb(instruction), Rc(instruction)); break; // CVTGQ/SC
734 case 0x480: OPERATE_FFF("addf/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/S
735 case 0x481:
736 if (Ra(instruction) == 31)
737 OPERATE_FF("negf/s", Rb(instruction), Rc(instruction));
738 else
739 OPERATE_FFF("subf/s", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBF/S
740 break;
741 case 0x482: OPERATE_FFF("mulf/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/S
742 case 0x483: OPERATE_FFF("divf/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/S
743 case 0x49e: OPERATE_FF("cvtdg/s", Rb(instruction), Rc(instruction)); break; // CVTDG/S
744 case 0x4a0: OPERATE_FFF("addg/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/S
745 case 0x4a1:
746 if (Ra(instruction) == 31)
747 OPERATE_FF("negg/s", Rb(instruction), Rc(instruction));
748 else
749 OPERATE_FFF("subg/s", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBG/S
750 break;
751 case 0x4a2: OPERATE_FFF("mulg/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/S
752 case 0x4a3: OPERATE_FFF("divg/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/S
753 case 0x4a5: OPERATE_FFF("cmpgeq/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPGEQ/S
754 case 0x4a6: OPERATE_FFF("cmpglt/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPGLT/S
755 case 0x4a7: OPERATE_FFF("cmpgle/s", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPGLE/S
756 case 0x4ac: OPERATE_FF("cvtgf/s", Rb(instruction), Rc(instruction)); break; // CVTGF/S
757 case 0x4ad: OPERATE_FF("cvtgd/s", Rb(instruction), Rc(instruction)); break; // CVTGD/S
758 case 0x4af: OPERATE_FF("cvtgq/s", Rb(instruction), Rc(instruction)); break; // CVTGQ/S
759 case 0x500: OPERATE_FFF("addf/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/SUC
760 case 0x501: OPERATE_FFF("subf/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBF/SUC
761 case 0x502: OPERATE_FFF("mulf/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/SUC
762 case 0x503: OPERATE_FFF("divf/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/SUC
763 case 0x51e: OPERATE_FF("cvtdg/suc", Rb(instruction), Rc(instruction)); break; // CVTDG/SUC
764 case 0x520: OPERATE_FFF("addg/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/SUC
765 case 0x521: OPERATE_FFF("subg/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBG/SUC
766 case 0x522: OPERATE_FFF("mulg/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/SUC
767 case 0x523: OPERATE_FFF("divg/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/SUC
768 case 0x52c: OPERATE_FF("cvtgf/suc", Rb(instruction), Rc(instruction)); break; // CVTGF/SUC
769 case 0x52d: OPERATE_FF("cvtgd/suc", Rb(instruction), Rc(instruction)); break; // CVTGD/SUC
770 case 0x52f: OPERATE_FF("cvtgq/svc", Rb(instruction), Rc(instruction)); break; // CVTGQ/SVC
771 case 0x580: OPERATE_FFF("addf/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDF/SU
772 case 0x581: OPERATE_FFF("subf/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBF/SU
773 case 0x582: OPERATE_FFF("mulf/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULF/SU
774 case 0x583: OPERATE_FFF("divf/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVF/SU
775 case 0x59e: OPERATE_FF("cvtdg/su", Rb(instruction), Rc(instruction)); break; // CVTDG/SU
776 case 0x5a0: OPERATE_FFF("addg/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDG/SU
777 case 0x5a1: OPERATE_FFF("subg/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBG/SU
778 case 0x5a2: OPERATE_FFF("mulg/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULG/SU
779 case 0x5a3: OPERATE_FFF("divg/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVG/SU
780 case 0x5ac: OPERATE_FF("cvtgf/su", Rb(instruction), Rc(instruction)); break; // CVTGF/SU
781 case 0x5ad: OPERATE_FF("cvtgd/su", Rb(instruction), Rc(instruction)); break; // CVTGD/SU
782 case 0x5af: OPERATE_FF("cvtgq/sv", Rb(instruction), Rc(instruction)); break; // CVTGQ/SV
783
784 default: UNKNOWN("fltv*"); break;
785 }
786 break;
787 case 0x16: // FLTI* (ieee floating)
788 switch ((instruction >> 5) & 0x7ff)
789 {
790 case 0x000: OPERATE_FFF("adds/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/C
791 case 0x001: OPERATE_FFF("subs/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/C
792 case 0x002: OPERATE_FFF("muls/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/C
793 case 0x003: OPERATE_FFF("divs/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/C
794 case 0x020: OPERATE_FFF("addt/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/C
795 case 0x021: OPERATE_FFF("subt/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/C
796 case 0x022: OPERATE_FFF("mult/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/C
797 case 0x023: OPERATE_FFF("divt/c", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/C
798 case 0x02c: OPERATE_FF("cvttts/c", Rb(instruction), Rc(instruction)); break; // CVTTS/C
799 case 0x02f: OPERATE_FF("cvttq/c", Rb(instruction), Rc(instruction)); break; // CVTTQ/C
800 case 0x03c: OPERATE_FF("cvtqs/c", Rb(instruction), Rc(instruction)); break; // CVTQS/C
801 case 0x03e: OPERATE_FF("cvtqt/c", Rb(instruction), Rc(instruction)); break; // CVTQT/C
802 case 0x040: OPERATE_FFF("adds/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/M
803 case 0x041: OPERATE_FFF("subs/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/M
804 case 0x042: OPERATE_FFF("muls/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/M
805 case 0x043: OPERATE_FFF("divs/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/M
806 case 0x060: OPERATE_FFF("addt/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/M
807 case 0x061: OPERATE_FFF("subt/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/M
808 case 0x062: OPERATE_FFF("mult/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/M
809 case 0x063: OPERATE_FFF("divt/m", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/M
810 case 0x06c: OPERATE_FF("cvttts/m", Rb(instruction), Rc(instruction)); break; // CVTTS/M
811 case 0x06f: OPERATE_FF("cvttq/m", Rb(instruction), Rc(instruction)); break; // CVTTQ/M
812 case 0x07c: OPERATE_FF("cvtqs/m", Rb(instruction), Rc(instruction)); break; // CVTQS/M
813 case 0x07e: OPERATE_FF("cvtqt/m", Rb(instruction), Rc(instruction)); break; // CVTQT/M
814 case 0x080: OPERATE_FFF("adds", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS
815 case 0x081:
816 if (Ra(instruction) == 31)
817 OPERATE_FF("negs", Rb(instruction), Rc(instruction));
818 else
819 OPERATE_FFF("subs", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBS
820 break;
821 case 0x082: OPERATE_FFF("muls", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS
822 case 0x083: OPERATE_FFF("divs", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS
823 case 0x0a0: OPERATE_FFF("addt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT
824 case 0x0a1:
825 if (Ra(instruction) == 31)
826 OPERATE_FF("negt", Rb(instruction), Rc(instruction));
827 else
828 OPERATE_FFF("subt", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBT
829 break;
830 case 0x0a2: OPERATE_FFF("mult", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT
831 case 0x0a3: OPERATE_FFF("divt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT
832 case 0x0a4: OPERATE_FFF("cmptun", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTUN
833 case 0x0a5: OPERATE_FFF("cmpteq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTEQ
834 case 0x0a6: OPERATE_FFF("cmptlt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTLT
835 case 0x0a7: OPERATE_FFF("cmptle", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTLE
836 case 0x0ac: OPERATE_FF("cvttts", Rb(instruction), Rc(instruction)); break; // CVTTS
837 case 0x0af: OPERATE_FF("cvttq", Rb(instruction), Rc(instruction)); break; // CVTTQ
838 case 0x0bc: OPERATE_FF("cvtqs", Rb(instruction), Rc(instruction)); break; // CVTQS
839 case 0x0be: OPERATE_FF("cvtqt", Rb(instruction), Rc(instruction)); break; // CVTQT
840 case 0x0c0: OPERATE_FFF("adds/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/D
841 case 0x0c1: OPERATE_FFF("subs/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/D
842 case 0x0c2: OPERATE_FFF("muls/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/D
843 case 0x0c3: OPERATE_FFF("divs/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/D
844 case 0x0e0: OPERATE_FFF("addt/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/D
845 case 0x0e1: OPERATE_FFF("subt/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/D
846 case 0x0e2: OPERATE_FFF("mult/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/D
847 case 0x0e3: OPERATE_FFF("divt/d", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/D
848 case 0x0ec: OPERATE_FF("cvttts/d", Rb(instruction), Rc(instruction)); break; // CVTTS/D
849 case 0x0ef: OPERATE_FF("cvttq/d", Rb(instruction), Rc(instruction)); break; // CVTTQ/D
850 case 0x0fc: OPERATE_FF("cvtqs/d", Rb(instruction), Rc(instruction)); break; // CVTQS/D
851 case 0x0fe: OPERATE_FF("cvtqt/d", Rb(instruction), Rc(instruction)); break; // CVTQT/D
852 case 0x100: OPERATE_FFF("adds/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/UC
853 case 0x101: OPERATE_FFF("subs/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/UC
854 case 0x102: OPERATE_FFF("muls/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/UC
855 case 0x103: OPERATE_FFF("divs/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/UC
856 case 0x120: OPERATE_FFF("addt/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/UC
857 case 0x121: OPERATE_FFF("subt/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/UC
858 case 0x122: OPERATE_FFF("mult/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/UC
859 case 0x123: OPERATE_FFF("divt/uc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/UC
860 case 0x12c: OPERATE_FF("cvttts/uc", Rb(instruction), Rc(instruction)); break; // CVTTS/UC
861 case 0x12f: OPERATE_FF("cvttq/vc", Rb(instruction), Rc(instruction)); break; // CVTTQ/VC
862 case 0x140: OPERATE_FFF("adds/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/UM
863 case 0x141: OPERATE_FFF("subs/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/UM
864 case 0x142: OPERATE_FFF("muls/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/UM
865 case 0x143: OPERATE_FFF("divs/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/UM
866 case 0x160: OPERATE_FFF("addt/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/UM
867 case 0x161: OPERATE_FFF("subt/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/UM
868 case 0x162: OPERATE_FFF("mult/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/UM
869 case 0x163: OPERATE_FFF("divt/um", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/UM
870 case 0x16c: OPERATE_FF("cvttts/um", Rb(instruction), Rc(instruction)); break; // CVTTS/UM
871 case 0x16f: OPERATE_FF("cvttq/vm", Rb(instruction), Rc(instruction)); break; // CVTTQ/VM
872 case 0x180: OPERATE_FFF("adds/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/U
873 case 0x181: OPERATE_FFF("subs/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/U
874 case 0x182: OPERATE_FFF("muls/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/U
875 case 0x183: OPERATE_FFF("divs/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/U
876 case 0x1a0: OPERATE_FFF("addt/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/U
877 case 0x1a1: OPERATE_FFF("subt/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/U
878 case 0x1a2: OPERATE_FFF("mult/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/U
879 case 0x1a3: OPERATE_FFF("divt/u", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/U
880 case 0x1ac: OPERATE_FF("cvttts/u", Rb(instruction), Rc(instruction)); break; // CVTTS/U
881 case 0x1af: OPERATE_FF("cvttq/v", Rb(instruction), Rc(instruction)); break; // CVTTQ/V
882 case 0x1c0: OPERATE_FFF("adds/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/UD
883 case 0x1c1: OPERATE_FFF("subs/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/UD
884 case 0x1c2: OPERATE_FFF("muls/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/UD
885 case 0x1c3: OPERATE_FFF("divs/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/UD
886 case 0x1e0: OPERATE_FFF("addt/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/UD
887 case 0x1e1: OPERATE_FFF("subs/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/UD
888 case 0x1e2: OPERATE_FFF("mult/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/UD
889 case 0x1e3: OPERATE_FFF("divt/ud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/UD
890 case 0x1ec: OPERATE_FF("cvttts/ud", Rb(instruction), Rc(instruction)); break; // CVTTS/UD
891 case 0x1ef: OPERATE_FF("cvttq/vd", Rb(instruction), Rc(instruction)); break; // CVTTQ/VD
892 case 0x2ac: OPERATE_FF("cvtst", Rb(instruction), Rc(instruction)); break; // CVTST
893 case 0x500: OPERATE_FFF("adds/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUC
894 case 0x501: OPERATE_FFF("subs/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/SUC
895 case 0x502: OPERATE_FFF("muls/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUC
896 case 0x503: OPERATE_FFF("divs/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUC
897 case 0x520: OPERATE_FFF("addt/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUC
898 case 0x521: OPERATE_FFF("subt/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/SUC
899 case 0x522: OPERATE_FFF("mult/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUC
900 case 0x523: OPERATE_FFF("divt/suc", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUC
901 case 0x52c: OPERATE_FF("cvttts/suc", Rb(instruction), Rc(instruction)); break; // CVTTS/SUC
902 case 0x52f: OPERATE_FF("cvttq/svc", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVC
903 case 0x540: OPERATE_FFF("adds/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUM
904 case 0x541: OPERATE_FFF("subs/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/SUM
905 case 0x542: OPERATE_FFF("muls/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUM
906 case 0x543: OPERATE_FFF("divs/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUM
907 case 0x560: OPERATE_FFF("addt/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUM
908 case 0x561: OPERATE_FFF("subt/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/SUM
909 case 0x562: OPERATE_FFF("mult/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUM
910 case 0x563: OPERATE_FFF("divt/sum", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUM
911 case 0x56c: OPERATE_FF("cvttts/sum", Rb(instruction), Rc(instruction)); break; // CVTTS/SUM
912 case 0x56f: OPERATE_FF("cvttq/svm", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVM
913 case 0x580: OPERATE_FFF("adds/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SU
914 case 0x581:
915 if (Ra(instruction) == 31)
916 OPERATE_FF("negs/su", Rb(instruction), Rc(instruction));
917 else
918 OPERATE_FFF("subs/su", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBS/SU
919 break;
920 case 0x582: OPERATE_FFF("muls/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SU
921 case 0x583: OPERATE_FFF("divs/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SU
922 case 0x5a0: OPERATE_FFF("addt/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SU
923 case 0x5a1:
924 if (Ra(instruction) == 31)
925 OPERATE_FF("negt/su", Rb(instruction), Rc(instruction));
926 else
927 OPERATE_FFF("subt/su", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBT/SU
928 break;
929 case 0x5a2: OPERATE_FFF("mult/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SU
930 case 0x5a3: OPERATE_FFF("divt/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SU
931 case 0x5a4: OPERATE_FFF("cmptun/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTUN/SU
932 case 0x5a5: OPERATE_FFF("cmpteq/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTEQ/SU
933 case 0x5a6: OPERATE_FFF("cmptlt/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTLT/SU
934 case 0x5a7: OPERATE_FFF("cmptle/su", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CMPTLE/SU
935 case 0x5ac: OPERATE_FF("cvttts/su", Rb(instruction), Rc(instruction)); break; // CVTTS/SU
936 case 0x5af: OPERATE_FF("cvttq/sv", Rb(instruction), Rc(instruction)); break; // CVTTQ/SV
937 case 0x5c0: OPERATE_FFF("adds/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUD
938 case 0x5c1: OPERATE_FFF("subs/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/SUD
939 case 0x5c2: OPERATE_FFF("muls/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUD
940 case 0x5c3: OPERATE_FFF("divs/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUD
941 case 0x5e0: OPERATE_FFF("addt/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUD
942 case 0x5e1: OPERATE_FFF("subt/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/SUD
943 case 0x5e2: OPERATE_FFF("mult/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUD
944 case 0x5e3: OPERATE_FFF("divt/sud", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUD
945 case 0x5ec: OPERATE_FF("cvttts/sud", Rb(instruction), Rc(instruction)); break; // CVTTS/SUD
946 case 0x5ef: OPERATE_FF("cvttq/svd", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVD
947 case 0x6ac: OPERATE_FF("cvtst/s", Rb(instruction), Rc(instruction)); break; // CVTST/S
948 case 0x700: OPERATE_FFF("adds/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUIC
949 case 0x701: OPERATE_FFF("subs/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/SUIC
950 case 0x702: OPERATE_FFF("muls/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUIC
951 case 0x703: OPERATE_FFF("divs/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUIC
952 case 0x720: OPERATE_FFF("addt/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUIC
953 case 0x721: OPERATE_FFF("subt/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/SUIC
954 case 0x722: OPERATE_FFF("mult/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUIC
955 case 0x723: OPERATE_FFF("divt/suic", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUIC
956 case 0x72c: OPERATE_FF("cvttts/suic", Rb(instruction), Rc(instruction)); break; // CVTTS/SUIC
957 case 0x72f: OPERATE_FF("cvttq/svic", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVIC
958 case 0x73c: OPERATE_FF("cvtqs/suic", Rb(instruction), Rc(instruction)); break; // CVTQS/SUIC
959 case 0x73e: OPERATE_FF("cvtqt/suic", Rb(instruction), Rc(instruction)); break; // CVTQT/SUIC
960 case 0x740: OPERATE_FFF("adds/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUIM
961 case 0x741: OPERATE_FFF("subs/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/SUIM
962 case 0x742: OPERATE_FFF("muls/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUIM
963 case 0x743: OPERATE_FFF("divs/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUIM
964 case 0x760: OPERATE_FFF("addt/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUIM
965 case 0x761: OPERATE_FFF("subt/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/SUIM
966 case 0x762: OPERATE_FFF("mult/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUIM
967 case 0x763: OPERATE_FFF("divt/suim", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUIM
968 case 0x76c: OPERATE_FF("cvttts/suim", Rb(instruction), Rc(instruction)); break; // CVTTS/SUIM
969 case 0x76f: OPERATE_FF("cvttq/svim", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVIM
970 case 0x77c: OPERATE_FF("cvtqs/suim", Rb(instruction), Rc(instruction)); break; // CVTQS/SUIM
971 case 0x77e: OPERATE_FF("cvtqt/suim", Rb(instruction), Rc(instruction)); break; // CVTQT/SUIM
972 case 0x780: OPERATE_FFF("adds/sui", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUI
973 case 0x781:
974 if (Ra(instruction) == 31)
975 OPERATE_FF("negs/sui", Rb(instruction), Rc(instruction));
976 else
977 OPERATE_FFF("subs/sui", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBS/SUI
978 break;
979 case 0x782: OPERATE_FFF("muls/sui", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUI
980 case 0x783: OPERATE_FFF("divs/sui", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUI
981 case 0x7a0: OPERATE_FFF("addt/sui", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUI
982 case 0x7a1:
983 if (Ra(instruction) == 31)
984 OPERATE_FF("negt/sui", Rb(instruction), Rc(instruction));
985 else
986 OPERATE_FFF("subt/sui", Ra(instruction), Rb(instruction), Rc(instruction)); // SUBT/SUI
987 break;
988 case 0x7a2: OPERATE_FFF("mult/sui", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUI
989 case 0x7a3: OPERATE_FFF("divt/sui", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUI
990 case 0x7ac: OPERATE_FF("cvttts/sui", Rb(instruction), Rc(instruction)); break; // CVTTS/SUI
991 case 0x7af: OPERATE_FF("cvttq/svi", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVI
992 case 0x7bc: OPERATE_FF("cvtqs/sui", Rb(instruction), Rc(instruction)); break; // CVTQS/SUI
993 case 0x7be: OPERATE_FF("cvtqt/sui", Rb(instruction), Rc(instruction)); break; // CVTQT/SUI
994 case 0x7c0: OPERATE_FFF("adds/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDS/SUID
995 case 0x7c1: OPERATE_FFF("subs/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBS/SUID
996 case 0x7c2: OPERATE_FFF("muls/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULS/SUID
997 case 0x7c3: OPERATE_FFF("divs/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVS/SUID
998 case 0x7e0: OPERATE_FFF("addt/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // ADDT/SUID
999 case 0x7e1: OPERATE_FFF("subt/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // SUBT/SUID
1000 case 0x7e2: OPERATE_FFF("mult/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MULT/SUID
1001 case 0x7e3: OPERATE_FFF("divt/suid", Ra(instruction), Rb(instruction), Rc(instruction)); break; // DIVT/SUID
1002 case 0x7ec: OPERATE_FF("cvttts/suid", Rb(instruction), Rc(instruction)); break; // CVTTS/SUID
1003 case 0x7ef: OPERATE_FF("cvttq/svid", Rb(instruction), Rc(instruction)); break; // CVTTQ/SVID
1004 case 0x7fc: OPERATE_FF("cvtqs/suid", Rb(instruction), Rc(instruction)); break; // CVTQS/SUID
1005 case 0x7fe: OPERATE_FF("cvtqt/suid", Rb(instruction), Rc(instruction)); break; // CVTQT/SUID
1006
1007 default: UNKNOWN("flti*"); break;
1008 }
1009 break;
1010 case 0x17: // FLTL* (floating)
1011 switch ((instruction >> 5) & 0x7ff)
1012 {
1013 case 0x010: OPERATE_FF("cvtlq", Rb(instruction), Rc(instruction)); break; // CVTLQ
1014 case 0x020:
1015 if (Ra(instruction) == 31 && Rb(instruction) == 31 && Rc(instruction) == 31)
1016 MISC("fnop");
1017 else if (Ra(instruction) == 31 && Rb(instruction) == 31)
1018 OPERATE_F("fclr", Rc(instruction));
1019 else if (Ra(instruction) == 31)
1020 OPERATE_FF("fabs", Rb(instruction), Rc(instruction));
1021 else if (Ra(instruction) == Rb(instruction))
1022 OPERATE_FF("fmov", Rb(instruction), Rc(instruction));
1023 else
1024 OPERATE_FFF("cpys", Ra(instruction), Rb(instruction), Rc(instruction)); // CPYS
1025 break;
1026 case 0x021:
1027 if (Ra(instruction) == Rb(instruction))
1028 OPERATE_FF("fneg", Rb(instruction), Rc(instruction));
1029 else
1030 OPERATE_FFF("cpysn", Ra(instruction), Rb(instruction), Rc(instruction)); // CPYSN
1031 break;
1032 case 0x022: OPERATE_FFF("cpyse", Ra(instruction), Rb(instruction), Rc(instruction)); break; // CPYSE
1033 case 0x024:
1034 if (Ra(instruction) == Rb(instruction) && Rb(instruction) == Rc(instruction))
1035 OPERATE_F("mt_fpcr", Rc(instruction));
1036 else
1037 OPERATE_FFF("mt_fpcr", Ra(instruction), Rb(instruction), Rc(instruction)); // MT_FPCR
1038 break;
1039 case 0x025:
1040 if (Ra(instruction) == Rb(instruction) && Rb(instruction) == Rc(instruction))
1041 OPERATE_F("mf_fpcr", Rc(instruction));
1042 else
1043 OPERATE_FFF("mf_fpcr", Ra(instruction), Rb(instruction), Rc(instruction)); // MF_FPCR
1044 break;
1045 case 0x02a: OPERATE_FFF("fcmoveq", Ra(instruction), Rb(instruction), Rc(instruction)); break; // FCMOVEQ
1046 case 0x02b: OPERATE_FFF("fcmovne", Ra(instruction), Rb(instruction), Rc(instruction)); break; // FCMOVNE
1047 case 0x02c: OPERATE_FFF("fcmovlt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // FCMOVLT
1048 case 0x02d: OPERATE_FFF("fcmovge", Ra(instruction), Rb(instruction), Rc(instruction)); break; // FCMOVGE
1049 case 0x02e: OPERATE_FFF("fcmovle", Ra(instruction), Rb(instruction), Rc(instruction)); break; // FCMOVLE
1050 case 0x02f: OPERATE_FFF("fcmovgt", Ra(instruction), Rb(instruction), Rc(instruction)); break; // FCMOVGT
1051 case 0x030: OPERATE_FF("cvtql", Rb(instruction), Rc(instruction)); break; // CVTQL
1052 case 0x130: OPERATE_FF("cvtql/v", Rb(instruction), Rc(instruction)); break; // CVTQL/V
1053 case 0x530: OPERATE_FF("cvtql/sv", Rb(instruction), Rc(instruction)); break; // CVTQL/SV
1054
1055 default: UNKNOWN("fltl*"); break;
1056 }
1057 break;
1058 case 0x18: // MISC* (miscellaneous)
1059 switch (u16(instruction))
1060 {
1061 case 0x0000: MISC("trapb"); break; // TRAPB
1062 case 0x0400: MISC("excb"); break; // EXCB
1063 case 0x4000: MISC("mb"); break; // MB
1064 case 0x4400: MISC("wmb"); break; // WMB
1065 case 0x8000: MISC_M("fetch", Rb(instruction)); break; // FETCH
1066 case 0xa000: MISC_M("fetch_m", Rb(instruction)); break; // FETCH_M
1067 case 0xc000: MISC_R("rpcc", Ra(instruction)); break; // RPCC
1068 case 0xe000: MISC_R("rc", Ra(instruction)); break; // RC
1069 case 0xe800: MISC_M("ecb", Rb(instruction)); break; // ECB
1070 case 0xf000: MISC_R("rs", Ra(instruction)); break; // RS
1071 case 0xf800: MISC_M("wh64", Rb(instruction)); break; // WH64
1072
1073 default: UNKNOWN("misc*"); break;
1074 }
1075 break;
1076 case 0x19: // PAL19
1077 switch ((instruction >> 5) & 0x7)
1078 {
1079 case 0x0: MISC("nop"); break;
1080 case 0x1: OPERATE_RI("hw_mfpr/i", Rb(instruction), Rc(instruction)); break;
1081 case 0x2: OPERATE_RA("hw_mfpr/a", Rb(instruction), Rc(instruction)); break;
1082 case 0x3: OPERATE_RAI("hw_mfpr/ai", Rb(instruction), Rc(instruction)); break;
1083 case 0x4: OPERATE_RP("hw_mfpr/p", Rb(instruction), Rc(instruction)); break;
1084 case 0x5: OPERATE_RPI("hw_mfpr/pi", Rb(instruction), Rc(instruction)); break;
1085 case 0x6: OPERATE_RPA("hw_mfpr/pa", Rb(instruction), Rc(instruction)); break;
1086 case 0x7: OPERATE_RPAI("hw_mfpr/pai", Rb(instruction), Rc(instruction)); break;
1087 }
1088 break;
1089
1090 case 0x1a: // JSR* (jump)
1091 switch ((instruction >> 14) & 3)
1092 {
1093 case 0: JUMP("jmp", Ra(instruction), Rb(instruction)); break; // JMP
1094 case 1: JUMP("jsr", Ra(instruction), Rb(instruction)); flags |= STEP_OVER; break; // JSR
1095 case 2: JUMP("ret", Ra(instruction), Rb(instruction)); flags |= STEP_OUT; break; // RET
1096 case 3: JUMP("jsr_c", Ra(instruction), Rb(instruction)); break; // JSR_COROUTINE
1097 }
1098 break;
1099 case 0x1b: // PAL1B
1100 switch ((instruction >> 12) & 0xf)
1101 {
1102 case 0x0: MEMORY_R("hw_ldl", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1103 case 0x1: MEMORY_R("hw_ldq", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1104 case 0x2: MEMORY_R("hw_ldl/r", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1105 case 0x3: MEMORY_R("hw_ldq/r", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1106 case 0x4: MEMORY_R("hw_ldl/a", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1107 case 0x5: MEMORY_R("hw_ldq/a", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1108 case 0x6: MEMORY_R("hw_ldl/ar", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1109 case 0x7: MEMORY_R("hw_ldq/ar", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1110 case 0x8: MEMORY_R("hw_ldl/p", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1111 case 0x9: MEMORY_R("hw_ldq/p", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1112 case 0xa: MEMORY_R("hw_ldl/pr", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1113 case 0xb: MEMORY_R("hw_ldq/pr", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1114 case 0xc: MEMORY_R("hw_ldl/pa", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1115 case 0xd: MEMORY_R("hw_ldq/pa", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1116 case 0xe: MEMORY_R("hw_ldl/par", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1117 case 0xf: MEMORY_R("hw_ldq/par", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1118 }
1119 break;
1120 case 0x1c: // FPTI* (floating to integer)
1121 switch ((instruction >> 5) & 0xff)
1122 {
1123 // register variants
1124 case 0x00: OPERATE_RR("sextb", Rb(instruction), Rc(instruction)); break; // SEXTB (BWX)
1125 case 0x01: OPERATE_RR("sextw", Rb(instruction), Rc(instruction)); break; // SEXTW (BWX)
1126 case 0x30: OPERATE_RR("ctpop", Rb(instruction), Rc(instruction)); break; // CTPOP (CIX)
1127 case 0x31: OPERATE_RRR("perr", Ra(instruction), Rb(instruction), Rc(instruction)); break; // PERR (MVI)
1128 case 0x32: OPERATE_RR("ctlz", Rb(instruction), Rc(instruction)); break; // CTLZ (CIX)
1129 case 0x33: OPERATE_RR("cttz", Rb(instruction), Rc(instruction)); break; // CTTZ (CIX)
1130 case 0x34: OPERATE_RR("unpkbw", Rb(instruction), Rc(instruction)); break; // UNPKBW (MVI)
1131 case 0x35: OPERATE_RR("unpkbl", Rb(instruction), Rc(instruction)); break; // UNPKBL (MVI)
1132 case 0x36: OPERATE_RR("pkwb", Rb(instruction), Rc(instruction)); break; // PKWB (MVI)
1133 case 0x37: OPERATE_RR("pklb", Rb(instruction), Rc(instruction)); break; // PKLB (MVI)
1134 case 0x38: OPERATE_RRR("minsb8", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MINSB8 (MVI)
1135 case 0x39: OPERATE_RRR("minsw4", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MINSW4 (MVI)
1136 case 0x3a: OPERATE_RRR("minub8", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MINUB8 (MVI)
1137 case 0x3b: OPERATE_RRR("minuw4", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MINUW4 (MVI)
1138 case 0x3c: OPERATE_RRR("maxub8", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MAXUB8 (MVI)
1139 case 0x3d: OPERATE_RRR("maxuw4", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MAXUW4 (MVI)
1140 case 0x3e: OPERATE_RRR("maxsb8", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MAXSB8 (MVI)
1141 case 0x3f: OPERATE_RRR("maxsw4", Ra(instruction), Rb(instruction), Rc(instruction)); break; // MAXSW4 (MVI)
1142 case 0x70: OPERATE_FR("ftoit", Ra(instruction), Rc(instruction)); break; // FTOIT (FIX)
1143 case 0x78: OPERATE_FR("ftois", Ra(instruction), Rc(instruction)); break; // FTOIS (FIX)
1144
1145 // immediate variants
1146 case 0x80: OPERATE_IR("sextb", Im(instruction), Rc(instruction)); break; // SEXTB (BWX)
1147 case 0x81: OPERATE_IR("sextw", Im(instruction), Rc(instruction)); break; // SEXTW (BWX)
1148 case 0xb8: OPERATE_RIR("minsb8", Ra(instruction), Im(instruction), Rc(instruction)); break; // MINSB8 (MVI)
1149 case 0xb9: OPERATE_RIR("minsw4", Ra(instruction), Im(instruction), Rc(instruction)); break; // MINSW4 (MVI)
1150 case 0xba: OPERATE_RIR("minub8", Ra(instruction), Im(instruction), Rc(instruction)); break; // MINUB8 (MVI)
1151 case 0xbb: OPERATE_RIR("minuw4", Ra(instruction), Im(instruction), Rc(instruction)); break; // MINUW4 (MVI)
1152 case 0xbc: OPERATE_RIR("maxub8", Ra(instruction), Im(instruction), Rc(instruction)); break; // MAXUB8 (MVI)
1153 case 0xbd: OPERATE_RIR("maxuw4", Ra(instruction), Im(instruction), Rc(instruction)); break; // MAXUW4 (MVI)
1154 case 0xbe: OPERATE_RIR("maxsb8", Ra(instruction), Im(instruction), Rc(instruction)); break; // MAXSB8 (MVI)
1155 case 0xbf: OPERATE_RIR("maxsw4", Ra(instruction), Im(instruction), Rc(instruction)); break; // MAXSW4 (MVI)
1156
1157 default: UNKNOWN("fpti*"); break;
1158 }
1159 break;
1160 case 0x1d: // PAL1D
1161 switch ((instruction >> 5) & 0x7)
1162 {
1163 case 0x0: MISC("nop"); break;
1164 case 0x1: OPERATE_RI("hw_mtpr/i", Rb(instruction), Rc(instruction)); break;
1165 case 0x2: OPERATE_RA("hw_mtpr/a", Rb(instruction), Rc(instruction)); break;
1166 case 0x3: OPERATE_RAI("hw_mtpr/ai", Rb(instruction), Rc(instruction)); break;
1167 case 0x4: OPERATE_RP("hw_mtpr/p", Rb(instruction), Rc(instruction)); break;
1168 case 0x5: OPERATE_RPI("hw_mtpr/pi", Rb(instruction), Rc(instruction)); break;
1169 case 0x6: OPERATE_RPA("hw_mtpr/pa", Rb(instruction), Rc(instruction)); break;
1170 case 0x7: OPERATE_RPAI("hw_mtpr/pai", Rb(instruction), Rc(instruction)); break;
1171 }
1172 break;
1173 case 0x1e: // PAL1E
1174 switch (instruction & 0x03ffffff)
1175 {
1176 case 0x03ff8000: MISC("hw_rei"); break;
1177
1178 default: UNKNOWN("pal1e"); break;
1179 }
1180 break;
1181 case 0x1f: // PAL1F
1182 switch ((instruction >> 12) & 0xf)
1183 {
1184 case 0x0: MEMORY_R("hw_stl", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1185 case 0x1: MEMORY_R("hw_stq", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1186 case 0x2: MEMORY_R("hw_stl/r", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1187 case 0x3: MEMORY_R("hw_stq/r", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1188 case 0x4: MEMORY_R("hw_stl/a", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1189 case 0x5: MEMORY_R("hw_stq/a", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1190 case 0x6: MEMORY_R("hw_stl/ar", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1191 case 0x7: MEMORY_R("hw_stq/ar", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1192 case 0x8: MEMORY_R("hw_stl/p", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1193 case 0x9: MEMORY_R("hw_stq/p", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1194 case 0xa: MEMORY_R("hw_stl/pr", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1195 case 0xb: MEMORY_R("hw_stq/pr", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1196 case 0xc: MEMORY_R("hw_stl/pa", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1197 case 0xd: MEMORY_R("hw_stq/pa", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1198 case 0xe: MEMORY_R("hw_stl/par", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1199 case 0xf: MEMORY_R("hw_stq/par", Ra(instruction), Disp_P(instruction), Rb(instruction)); break;
1200 }
1201 break;
1202 // memory format
1203 case 0x20: MEMORY_F("ldf", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDF
1204 case 0x21: MEMORY_F("ldg", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDG
1205 case 0x22: MEMORY_F("lds", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDS
1206 case 0x23: MEMORY_F("ldt", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDT
1207 case 0x24: MEMORY_F("stf", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STF
1208 case 0x25: MEMORY_F("stg", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STG
1209 case 0x26: MEMORY_F("sts", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STS
1210 case 0x27: MEMORY_F("stt", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STT
1211 case 0x28: MEMORY_R("ldl", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDL
1212 case 0x29: MEMORY_R("ldq", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDQ
1213 case 0x2a: MEMORY_R("ldl_l", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDL_L
1214 case 0x2b: MEMORY_R("ldq_l", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // LDQ_L
1215 case 0x2c: MEMORY_R("stl", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STL
1216 case 0x2d: MEMORY_R("stq", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STQ
1217 case 0x2e: MEMORY_R("stl_c", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STL_C
1218 case 0x2f: MEMORY_R("stq_c", Ra(instruction), Disp_M(instruction), Rb(instruction)); break; // STQ_C
1219
1220 // branch format
1221 case 0x30:
1222 if (Ra(instruction) == 31)
1223 BRANCH("br", Disp_B(instruction));
1224 else
1225 BRANCH_R("br", Ra(instruction), Disp_B(instruction)); // BR
1226 break;
1227 case 0x31: BRANCH_F("fbeq", Ra(instruction), Disp_B(instruction)); break; // FBEQ
1228 case 0x32: BRANCH_F("fblt", Ra(instruction), Disp_B(instruction)); break; // FBLT
1229 case 0x33: BRANCH_F("fble", Ra(instruction), Disp_B(instruction)); break; // FBLE
1230 case 0x34: BRANCH_R("bsr", Ra(instruction), Disp_B(instruction)); break; // BSR
1231 case 0x35: BRANCH_F("fbne", Ra(instruction), Disp_B(instruction)); break; // FBNE
1232 case 0x36: BRANCH_F("fbge", Ra(instruction), Disp_B(instruction)); break; // FBGE
1233 case 0x37: BRANCH_F("fbgt", Ra(instruction), Disp_B(instruction)); break; // FBGT
1234 case 0x38: BRANCH_R("blbc", Ra(instruction), Disp_B(instruction)); break; // BLBC
1235 case 0x39: BRANCH_R("beq", Ra(instruction), Disp_B(instruction)); break; // BEQ
1236 case 0x3a: BRANCH_R("blt", Ra(instruction), Disp_B(instruction)); break; // BLT
1237 case 0x3b: BRANCH_R("ble", Ra(instruction), Disp_B(instruction)); break; // BLE
1238 case 0x3c: BRANCH_R("blbs", Ra(instruction), Disp_B(instruction)); break; // BLBS
1239 case 0x3d: BRANCH_R("bne", Ra(instruction), Disp_B(instruction)); break; // BNE
1240 case 0x3e: BRANCH_R("bge", Ra(instruction), Disp_B(instruction)); break; // BGE
1241 case 0x3f: BRANCH_R("bgt", Ra(instruction), Disp_B(instruction)); break; // BGT
1242 }
1243
1244 return bytes | flags;
1245 }
1246