1 // license:BSD-3-Clause 2 // copyright-holders:Philip Bennett 3 /*************************************************************************** 4 5 cubeqcpu.h 6 Interface file for the Cube Quest CPUs 7 Written by Phil Bennett 8 9 ***************************************************************************/ 10 11 #ifndef MAME_CPU_CUBEQCPU_CUBEQCPU_H 12 #define MAME_CPU_CUBEQCPU_CUBEQCPU_H 13 14 15 /*************************************************************************** 16 PUBLIC FUNCTIONS 17 ***************************************************************************/ 18 19 class cquestsnd_cpu_device : public cpu_device 20 { 21 public: 22 // construction/destruction 23 cquestsnd_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); 24 25 // configuration helpers dac_w()26 auto dac_w() { return m_dac_w.bind(); } set_sound_region(const char * tag)27 void set_sound_region(const char *tag) { m_sound_region_tag = tag; } 28 29 void sndram_w(offs_t offset, u16 data, u16 mem_mask = ~0); 30 u16 sndram_r(offs_t offset); 31 32 protected: 33 enum 34 { 35 CQUESTSND_PC = 1, 36 CQUESTSND_Q, 37 CQUESTSND_RAM0, 38 CQUESTSND_RAM1, 39 CQUESTSND_RAM2, 40 CQUESTSND_RAM3, 41 CQUESTSND_RAM4, 42 CQUESTSND_RAM5, 43 CQUESTSND_RAM6, 44 CQUESTSND_RAM7, 45 CQUESTSND_RAM8, 46 CQUESTSND_RAM9, 47 CQUESTSND_RAMA, 48 CQUESTSND_RAMB, 49 CQUESTSND_RAMC, 50 CQUESTSND_RAMD, 51 CQUESTSND_RAME, 52 CQUESTSND_RAMF, 53 CQUESTSND_RTNLATCH, 54 CQUESTSND_ADRCNTR, 55 CQUESTSND_DINLATCH 56 }; 57 58 // device-level overrides 59 virtual void device_start() override; 60 virtual void device_reset() override; 61 62 // device_execute_interface overrides execute_min_cycles()63 virtual u32 execute_min_cycles() const noexcept override { return 1; } execute_max_cycles()64 virtual u32 execute_max_cycles() const noexcept override { return 1; } execute_input_lines()65 virtual u32 execute_input_lines() const noexcept override { return 0; } 66 virtual void execute_run() override; 67 68 // device_memory_interface overrides 69 virtual space_config_vector memory_space_config() const override; 70 71 // device_disasm_interface overrides 72 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; 73 74 private: 75 address_space_config m_program_config; 76 77 /* AM2901 internals */ 78 u16 m_ram[16]; 79 u16 m_q; 80 u16 m_f; 81 u16 m_y; 82 u32 m_cflag; 83 u32 m_vflag; 84 85 u8 m_pc; /* 2 x LS161 @ 6E, 6F */ 86 u16 m_platch; 87 u8 m_rtnlatch; /* LS374 @ 5F */ 88 u8 m_adrcntr; /* 2 x LS161 */ 89 u16 m_adrlatch; 90 u16 m_dinlatch; 91 u16 m_ramwlatch; 92 93 u16 m_sram[4096/2]; 94 95 bool m_prev_ipram; 96 bool m_prev_ipwrt; 97 98 devcb_write16 m_dac_w; 99 const char *m_sound_region_tag; 100 u16 *m_sound_data; 101 102 memory_access<9, 3, -3, ENDIANNESS_BIG>::cache m_cache; 103 memory_access<9, 3, -3, ENDIANNESS_BIG>::specific m_program; 104 105 int m_icount; 106 107 bool do_sndjmp(u8 jmp); 108 }; 109 110 111 class cquestrot_cpu_device : public cpu_device 112 { 113 public: 114 // construction/destruction 115 cquestrot_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); 116 117 // configuration helpers linedata_w()118 auto linedata_w() { return m_linedata_w.bind(); } 119 120 u16 linedata_r(); 121 void rotram_w(offs_t offset, u16 data, u16 mem_mask = ~0); 122 u16 rotram_r(offs_t offset); 123 124 protected: 125 enum 126 { 127 CQUESTROT_PC = 1, 128 CQUESTROT_Q, 129 CQUESTROT_RAM0, 130 CQUESTROT_RAM1, 131 CQUESTROT_RAM2, 132 CQUESTROT_RAM3, 133 CQUESTROT_RAM4, 134 CQUESTROT_RAM5, 135 CQUESTROT_RAM6, 136 CQUESTROT_RAM7, 137 CQUESTROT_RAM8, 138 CQUESTROT_RAM9, 139 CQUESTROT_RAMA, 140 CQUESTROT_RAMB, 141 CQUESTROT_RAMC, 142 CQUESTROT_RAMD, 143 CQUESTROT_RAME, 144 CQUESTROT_RAMF, 145 CQUESTROT_SEQCNT, 146 CQUESTROT_DYNADDR, 147 CQUESTROT_DYNDATA, 148 CQUESTROT_YRLATCH, 149 CQUESTROT_YDLATCH, 150 CQUESTROT_DINLATCH, 151 CQUESTROT_DSRCLATCH, 152 CQUESTROT_RSRCLATCH, 153 CQUESTROT_LDADDR, 154 CQUESTROT_LDDATA 155 }; 156 157 // device-level overrides 158 virtual void device_start() override; 159 virtual void device_reset() override; 160 161 // device_execute_interface overrides execute_min_cycles()162 virtual u32 execute_min_cycles() const noexcept override { return 1; } execute_max_cycles()163 virtual u32 execute_max_cycles() const noexcept override { return 1; } execute_input_lines()164 virtual u32 execute_input_lines() const noexcept override { return 0; } 165 virtual void execute_run() override; 166 167 // device_memory_interface overrides 168 virtual space_config_vector memory_space_config() const override; 169 170 // device_state_interface overrides 171 virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; 172 173 // device_disasm_interface overrides 174 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; 175 176 private: 177 address_space_config m_program_config; 178 devcb_write16 m_linedata_w; 179 180 /* AM2901 internals */ 181 u16 m_ram[16]; 182 u16 m_q; 183 u16 m_f; 184 u16 m_y; 185 u32 m_cflag; 186 u32 m_vflag; 187 188 u16 m_pc; /* 12-bit, but only 9 used */ 189 u8 m_seqcnt; /* 4-bit counter */ 190 191 u8 m_dsrclatch; 192 u8 m_rsrclatch; 193 u16 m_dynaddr; /* LS374 at 2D, 8D */ 194 u16 m_dyndata; /* LS374 at 10B, 9B */ 195 u16 m_yrlatch; /* LS374 at 9D, 10D */ 196 u16 m_ydlatch; /* LS374 at 9C, 10C */ 197 u16 m_dinlatch; 198 u8 m_divreg; /* LS74 at ? */ 199 200 u16 m_linedata; 201 u16 m_lineaddr; 202 203 u16 m_dram[16384]; /* Shared with 68000 */ 204 u16 m_sram[2048]; /* Private */ 205 206 u8 m_prev_dred; 207 u8 m_prev_dwrt; 208 u8 m_wc; 209 u8 m_rc; 210 u8 m_clkcnt; 211 212 memory_access<9, 3, -3, ENDIANNESS_BIG>::cache m_cache; 213 memory_access<9, 3, -3, ENDIANNESS_BIG>::specific m_program; 214 int m_icount; 215 216 // For the debugger 217 u8 m_flags; 218 219 int do_rotjmp(u8 jmp); 220 }; 221 222 223 class cquestlin_cpu_device : public cpu_device 224 { 225 public: 226 // construction/destruction 227 cquestlin_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock); 228 229 // configuration helpers linedata_r()230 auto linedata_r() { return m_linedata_r.bind(); } 231 232 void linedata_w(offs_t offset, u16 data); 233 void cubeqcpu_swap_line_banks(); 234 void cubeqcpu_clear_stack(); 235 u8 cubeqcpu_get_ptr_ram_val(int i); 236 u32* cubeqcpu_get_stack_ram(); 237 238 protected: 239 enum 240 { 241 CQUESTLIN_FGPC = 1, 242 CQUESTLIN_BGPC, 243 CQUESTLIN_Q, 244 CQUESTLIN_RAM0, 245 CQUESTLIN_RAM1, 246 CQUESTLIN_RAM2, 247 CQUESTLIN_RAM3, 248 CQUESTLIN_RAM4, 249 CQUESTLIN_RAM5, 250 CQUESTLIN_RAM6, 251 CQUESTLIN_RAM7, 252 CQUESTLIN_RAM8, 253 CQUESTLIN_RAM9, 254 CQUESTLIN_RAMA, 255 CQUESTLIN_RAMB, 256 CQUESTLIN_RAMC, 257 CQUESTLIN_RAMD, 258 CQUESTLIN_RAME, 259 CQUESTLIN_RAMF, 260 CQUESTLIN_FADLATCH, 261 CQUESTLIN_BADLATCH, 262 CQUESTLIN_SREG, 263 CQUESTLIN_XCNT, 264 CQUESTLIN_YCNT, 265 CQUESTLIN_CLATCH, 266 CQUESTLIN_ZLATCH 267 }; 268 269 // device-level overrides 270 virtual void device_start() override; 271 virtual void device_reset() override; 272 273 // device_execute_interface overrides execute_min_cycles()274 virtual u32 execute_min_cycles() const noexcept override { return 1; } execute_max_cycles()275 virtual u32 execute_max_cycles() const noexcept override { return 1; } execute_input_lines()276 virtual u32 execute_input_lines() const noexcept override { return 0; } 277 virtual void execute_run() override; 278 279 // device_memory_interface overrides 280 virtual space_config_vector memory_space_config() const override; 281 282 // device_state_interface overrides 283 virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; 284 285 // device_disasm_interface overrides 286 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; 287 288 private: 289 address_space_config m_program_config; 290 devcb_read16 m_linedata_r; 291 292 /* 12-bit AM2901 internals */ 293 u16 m_ram[16]; 294 u16 m_q; 295 u16 m_f; 296 u16 m_y; 297 u32 m_cflag; 298 u32 m_vflag; 299 300 u8 m_pc[2]; /* Two program counters; one for FG, other for BG */ 301 302 u16 m_seqcnt; /* 12-bit */ 303 u16 m_clatch; /* LS374 at 9E and 1-bit FF */ 304 u8 m_zlatch; /* LS374 at 4H */ 305 306 u16 m_xcnt; 307 u16 m_ycnt; 308 u8 m_sreg; 309 310 u16 m_fadlatch; 311 u16 m_badlatch; 312 313 u16 m_sramdlatch; 314 315 u8 m_fglatch; 316 u8 m_bglatch; 317 u8 m_gt0reg; 318 u8 m_fdxreg; 319 u32 m_field; 320 321 u32 m_clkcnt; 322 323 /* RAM */ 324 u16 m_sram[4096]; /* Shared with rotate CPU */ 325 u8 m_ptr_ram[1024]; /* Pointer RAM */ 326 u32 m_e_stack[32768]; /* Stack DRAM: 32kx20 */ 327 u32 m_o_stack[32768]; /* Stack DRAM: 32kx20 */ 328 329 memory_access<9, 3, -3, ENDIANNESS_BIG>::cache m_cache; 330 memory_access<9, 3, -3, ENDIANNESS_BIG>::specific m_program; 331 int m_icount; 332 333 // For the debugger 334 u8 m_flags; 335 u16 m_curpc; 336 337 int do_linjmp(u8 jmp); 338 }; 339 340 341 DECLARE_DEVICE_TYPE(CQUESTSND, cquestsnd_cpu_device) 342 DECLARE_DEVICE_TYPE(CQUESTROT, cquestrot_cpu_device) 343 DECLARE_DEVICE_TYPE(CQUESTLIN, cquestlin_cpu_device) 344 345 346 #endif // MAME_CPU_CUBEQCPU_CUBEQCPU_H 347