1 // license:BSD-3-Clause 2 // copyright-holders:Bryan McPhail, Alex W. Jackson 3 #define GetRB \ 4 ModRM = fetch(); \ 5 if (ModRM >= 0xc0) \ 6 tmp = Wreg(Mod_RM.RM.w[ModRM]) & 0x7; \ 7 else { \ 8 logerror("%06x: Invalid MODRM for register banking instruction\n",PC()); \ 9 tmp = 0; \ 10 } 11 12 #define RETRBI \ 13 tmp = (Wreg(PSW_SAVE) & 0x7000) >> 12; \ 14 m_ip = Wreg(PC_SAVE); \ 15 ExpandFlags(Wreg(PSW_SAVE)); \ 16 SetRB(tmp); \ 17 CHANGE_PC 18 19 #define TSKSW \ 20 Wreg(PSW_SAVE) = CompressFlags(); \ 21 Wreg(PC_SAVE) = m_ip; \ 22 SetRB(tmp); \ 23 m_ip = Wreg(PC_SAVE); \ 24 ExpandFlags(Wreg(PSW_SAVE)); \ 25 CHANGE_PC 26 27 #define MOVSPA \ 28 tmp = (Wreg(PSW_SAVE) & 0x7000) >> 8; \ 29 Sreg(SS) = m_internal_ram[tmp+SS]; \ 30 Wreg(SP) = m_internal_ram[tmp+SP] 31 32 #define MOVSPB \ 33 tmp <<= 4; \ 34 m_internal_ram[tmp+SS] = Sreg(SS); \ 35 m_internal_ram[tmp+SP] = Wreg(SP) 36 37 #define FINT \ 38 for(tmp = 1; tmp < 0x100; tmp <<= 1) { \ 39 if(m_ISPR & tmp) { \ 40 m_ISPR &= ~tmp; \ 41 break; \ 42 } \ 43 } 44 45 OP( 0x0f, i_pre_v25 ) { uint32_t ModRM, tmp, tmp2; 46 switch (fetch()) { 47 case 0x10 : BITOP_BYTE; CLKS(3,3,4); tmp2 = Breg(CL) & 0x7; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */ 48 case 0x11 : BITOP_WORD; CLKS(3,3,4); tmp2 = Breg(CL) & 0xf; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */ 49 case 0x12 : BITOP_BYTE; CLKS(5,5,4); tmp2 = Breg(CL) & 0x7; tmp &= ~(1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Clr */ 50 case 0x13 : BITOP_WORD; CLKS(5,5,4); tmp2 = Breg(CL) & 0xf; tmp &= ~(1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Clr */ 51 case 0x14 : BITOP_BYTE; CLKS(4,4,4); tmp2 = Breg(CL) & 0x7; tmp |= (1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Set */ 52 case 0x15 : BITOP_WORD; CLKS(4,4,4); tmp2 = Breg(CL) & 0xf; tmp |= (1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Set */ 53 case 0x16 : BITOP_BYTE; CLKS(4,4,4); tmp2 = Breg(CL) & 0x7; BIT_NOT; PutbackRMByte(ModRM,tmp); break; /* Not */ 54 case 0x17 : BITOP_WORD; CLKS(4,4,4); tmp2 = Breg(CL) & 0xf; BIT_NOT; PutbackRMWord(ModRM,tmp); break; /* Not */ 55 56 case 0x18 : BITOP_BYTE; CLKS(4,4,4); tmp2 = (fetch()) & 0x7; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */ 57 case 0x19 : BITOP_WORD; CLKS(4,4,4); tmp2 = (fetch()) & 0xf; m_ZeroVal = (tmp & (1<<tmp2)) ? 1 : 0; m_CarryVal=m_OverVal=0; break; /* Test */ 58 case 0x1a : BITOP_BYTE; CLKS(6,6,4); tmp2 = (fetch()) & 0x7; tmp &= ~(1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Clr */ 59 case 0x1b : BITOP_WORD; CLKS(6,6,4); tmp2 = (fetch()) & 0xf; tmp &= ~(1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Clr */ 60 case 0x1c : BITOP_BYTE; CLKS(5,5,4); tmp2 = (fetch()) & 0x7; tmp |= (1<<tmp2); PutbackRMByte(ModRM,tmp); break; /* Set */ 61 case 0x1d : BITOP_WORD; CLKS(5,5,4); tmp2 = (fetch()) & 0xf; tmp |= (1<<tmp2); PutbackRMWord(ModRM,tmp); break; /* Set */ 62 case 0x1e : BITOP_BYTE; CLKS(5,5,4); tmp2 = (fetch()) & 0x7; BIT_NOT; PutbackRMByte(ModRM,tmp); break; /* Not */ 63 case 0x1f : BITOP_WORD; CLKS(5,5,4); tmp2 = (fetch()) & 0xf; BIT_NOT; PutbackRMWord(ModRM,tmp); break; /* Not */ 64 65 case 0x20 : ADD4S; CLKS(7,7,2); break; 66 case 0x22 : SUB4S; CLKS(7,7,2); break; 67 case 0x25 : MOVSPA; CLK(16); break; 68 case 0x26 : CMP4S; CLKS(7,7,2); break; 69 case 0x28 : ModRM = fetch(); tmp = GetRMByte(ModRM); tmp <<= 4; tmp |= Breg(AL) & 0xf; Breg(AL) = (Breg(AL) & 0xf0) | ((tmp>>8)&0xf); tmp &= 0xff; PutbackRMByte(ModRM,tmp); CLKM(13,13,9,28,28,15); break; 70 case 0x2a : ModRM = fetch(); tmp = GetRMByte(ModRM); tmp2 = (Breg(AL) & 0xf)<<4; Breg(AL) = (Breg(AL) & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(17,17,13,32,32,19); break; 71 case 0x2d : GetRB; nec_bankswitch(tmp); CLK(15); break; 72 case 0x31 : ModRM = fetch(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC()); break; 73 case 0x33 : ModRM = fetch(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC()); break; 74 case 0x91 : RETRBI; CLK(12); break; 75 case 0x92 : FINT; CLK(2); m_no_interrupt = 1; break; 76 case 0x94 : GetRB; TSKSW; CLK(20); break; 77 case 0x95 : GetRB; MOVSPB; CLK(11); break; 78 case 0x9e : logerror("%06x: STOP\n",PC()); m_icount=0; break; 79 default: logerror("%06x: Unknown V25 instruction\n",PC()); break; 80 } 81 } 82 83 OP( 0x63, i_brkn ) { nec_interrupt(fetch(), BRKN); CLKS(50,50,24); } 84 OP( 0xF1, i_brks ) { nec_interrupt(fetch(), BRKS); CLKS(50,50,24); } 85