1 // license:BSD-3-Clause
2 // copyright-holders:Ryan Holtz
3 /**********************************************************************
4
5 STmicro ST6-series microcontroller emulation skeleton
6
7 To Do:
8 - Cycle counts
9 - STOP, WAIT opcodes
10 - Peripherals
11
12 **********************************************************************/
13
14 #include "emu.h"
15 #include "st62xx.h"
16 #include "st62xx_dasm.h"
17
18 DEFINE_DEVICE_TYPE(ST6228, st6228_device, "st6228", "STmicro ST6228")
19
st6228_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)20 st6228_device::st6228_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
21 : cpu_device(mconfig, ST6228, tag, owner, clock)
22 , m_pc(0)
23 , m_mode(MODE_NMI)
24 , m_prev_mode(MODE_NORMAL)
25 , m_program_config("program", ENDIANNESS_LITTLE, 8, 12, 0, address_map_constructor(FUNC(st6228_device::st6228_program_map), this))
26 , m_data_config("data", ENDIANNESS_LITTLE, 8, 8, 0, address_map_constructor(FUNC(st6228_device::st6228_data_map), this))
27 , m_porta_out(*this)
28 , m_portb_out(*this)
29 , m_portc_out(*this)
30 , m_portd_out(*this)
31 , m_program(nullptr)
32 , m_data(nullptr)
33 , m_rambank(*this, "rambank")
34 , m_program_rombank(*this, "program_rombank")
35 , m_data_rombank(*this, "data_rombank")
36 , m_rom(*this, this->tag())
37 {
38 }
39
st6228_program_map(address_map & map)40 void st6228_device::st6228_program_map(address_map &map)
41 {
42 map(0x000, 0x7ff).bankr(m_program_rombank);
43 map(0x800, 0xfff).rom().region(tag(), 0x800);
44 }
45
st6228_data_map(address_map & map)46 void st6228_device::st6228_data_map(address_map &map)
47 {
48 map(0x00, 0x3f).bankrw(m_rambank);
49 map(0x40, 0x7f).bankr(m_data_rombank);
50 map(0x80, 0xff).rw(FUNC(st6228_device::regs_r), FUNC(st6228_device::regs_w));
51 }
52
device_start()53 void st6228_device::device_start()
54 {
55 m_pc = 0;
56
57 m_program = &space(AS_PROGRAM);
58 m_data = &space(AS_DATA);
59
60 // register our state for the debugger
61 state_add(STATE_GENPC, "GENPC", m_pc).noshow();
62 state_add(STATE_GENPCBASE, "CURPC", m_pc).noshow();
63 state_add(STATE_GENFLAGS, "GENFLAGS", m_flags[0]).callimport().callexport().formatstr("%6s").noshow();
64 state_add(STATE_FLAGS, "FLAGS", m_flags[0]).mask(0x3f);
65 state_add(STATE_PC, "PC", m_pc).mask(0xfff);
66 state_add(STATE_SP, "SP", m_stack_index).mask(0x7);
67 state_add(STATE_STACK0, "STACK0", m_stack[0]).formatstr("%03X");
68 state_add(STATE_STACK1, "STACK1", m_stack[1]).formatstr("%03X");
69 state_add(STATE_STACK2, "STACK2", m_stack[2]).formatstr("%03X");
70 state_add(STATE_STACK3, "STACK3", m_stack[3]).formatstr("%03X");
71 state_add(STATE_STACK4, "STACK4", m_stack[4]).formatstr("%03X");
72 state_add(STATE_STACK5, "STACK5", m_stack[5]).formatstr("%03X");
73 state_add(STATE_A, "A", m_regs[REG_A]);
74 state_add(STATE_X, "X", m_regs[REG_X]);
75 state_add(STATE_Y, "Y", m_regs[REG_Y]);
76 state_add(STATE_V, "V", m_regs[REG_V]);
77 state_add(STATE_W, "W", m_regs[REG_W]);
78
79 save_item(NAME(m_regs));
80 save_item(NAME(m_ram));
81 save_item(NAME(m_pc));
82 save_item(NAME(m_mode));
83 save_item(NAME(m_prev_mode));
84 save_item(NAME(m_flags));
85 save_item(NAME(m_stack));
86 save_item(NAME(m_stack_index));
87 save_item(NAME(m_icount));
88 save_item(NAME(m_port_dir));
89 save_item(NAME(m_port_option));
90 save_item(NAME(m_port_data));
91 save_item(NAME(m_port_pullup));
92 save_item(NAME(m_port_analog));
93 save_item(NAME(m_port_input));
94 save_item(NAME(m_port_irq_enable));
95
96 // set our instruction counter
97 set_icountptr(m_icount);
98
99 m_rambank->configure_entries(0, 2, m_ram, 0x40);
100 m_program_rombank->configure_entries(0, 4, m_rom->base(), 0x800);
101 m_data_rombank->configure_entries(0, 128, m_rom->base(), 0x40);
102
103 m_porta_out.resolve_all_safe();
104 m_portb_out.resolve_all_safe();
105 m_portc_out.resolve_all_safe();
106 m_portd_out.resolve_all_safe();
107 }
108
device_reset()109 void st6228_device::device_reset()
110 {
111 std::fill(std::begin(m_regs), std::end(m_regs), 0);
112 std::fill(std::begin(m_ram), std::end(m_ram), 0);
113 std::fill(std::begin(m_stack), std::end(m_stack), 0);
114 std::fill(std::begin(m_flags), std::end(m_flags), 0);
115
116 std::fill(std::begin(m_port_dir), std::end(m_port_dir), 0);
117 std::fill(std::begin(m_port_option), std::end(m_port_option), 0);
118 std::fill(std::begin(m_port_data), std::end(m_port_data), 0);
119 std::fill(std::begin(m_port_pullup), std::end(m_port_pullup), 0);
120 std::fill(std::begin(m_port_analog), std::end(m_port_analog), 0);
121 std::fill(std::begin(m_port_input), std::end(m_port_input), 0);
122 std::fill(std::begin(m_port_irq_enable), std::end(m_port_irq_enable), 0);
123
124 m_pc = m_program->read_word(VEC_RESET);
125 m_stack_index = 0;
126 m_mode = MODE_NMI;
127 m_prev_mode = MODE_NORMAL;
128
129 m_rambank->set_entry(0);
130 m_program_rombank->set_entry(0);
131 m_data_rombank->set_entry(0);
132
133 m_regs[REG_TIMER_COUNT] = 0xff;
134 m_regs[REG_TIMER_PRESCALE] = 0x7f;
135 m_regs[REG_WATCHDOG] = 0xfe;
136 m_regs[REG_AD_CONTROL] = 0x40;
137 }
138
memory_space_config() const139 device_memory_interface::space_config_vector st6228_device::memory_space_config() const
140 {
141 return space_config_vector {
142 std::make_pair(AS_PROGRAM, &m_program_config),
143 std::make_pair(AS_DATA, &m_data_config)
144 };
145 }
146
state_string_export(const device_state_entry & entry,std::string & str) const147 void st6228_device::state_string_export(const device_state_entry &entry, std::string &str) const
148 {
149 switch (entry.index())
150 {
151 case STATE_GENFLAGS:
152 str = string_format("%c%c%c%c%c%c",
153 (m_flags[2] & FLAG_C) ? 'C' : '.',
154 (m_flags[2] & FLAG_Z) ? 'Z' : '.',
155 (m_flags[1] & FLAG_C) ? 'C' : '.',
156 (m_flags[1] & FLAG_Z) ? 'Z' : '.',
157 (m_flags[0] & FLAG_C) ? 'C' : '.',
158 (m_flags[0] & FLAG_Z) ? 'Z' : '.');
159 break;
160 }
161 }
162
create_disassembler()163 std::unique_ptr<util::disasm_interface> st6228_device::create_disassembler()
164 {
165 return std::make_unique<st62xx_disassembler>();
166 }
167
168 // TODO: interrupts
WRITE_LINE_MEMBER(st6228_device::porta0_w)169 WRITE_LINE_MEMBER(st6228_device::porta0_w) { m_port_input[PORT_A] &= ~(1 << 0); m_port_input[PORT_A] |= (state << 0); }
WRITE_LINE_MEMBER(st6228_device::porta1_w)170 WRITE_LINE_MEMBER(st6228_device::porta1_w) { m_port_input[PORT_A] &= ~(1 << 1); m_port_input[PORT_A] |= (state << 1); }
WRITE_LINE_MEMBER(st6228_device::porta2_w)171 WRITE_LINE_MEMBER(st6228_device::porta2_w) { m_port_input[PORT_A] &= ~(1 << 2); m_port_input[PORT_A] |= (state << 2); }
WRITE_LINE_MEMBER(st6228_device::porta3_w)172 WRITE_LINE_MEMBER(st6228_device::porta3_w) { m_port_input[PORT_A] &= ~(1 << 3); m_port_input[PORT_A] |= (state << 3); }
WRITE_LINE_MEMBER(st6228_device::porta4_w)173 WRITE_LINE_MEMBER(st6228_device::porta4_w) { m_port_input[PORT_A] &= ~(1 << 4); m_port_input[PORT_A] |= (state << 4); }
WRITE_LINE_MEMBER(st6228_device::porta5_w)174 WRITE_LINE_MEMBER(st6228_device::porta5_w) { m_port_input[PORT_A] &= ~(1 << 5); m_port_input[PORT_A] |= (state << 5); }
175
WRITE_LINE_MEMBER(st6228_device::portb4_w)176 WRITE_LINE_MEMBER(st6228_device::portb4_w) { m_port_input[PORT_B] &= ~(1 << 4); m_port_input[PORT_B] |= (state << 4); }
WRITE_LINE_MEMBER(st6228_device::portb5_w)177 WRITE_LINE_MEMBER(st6228_device::portb5_w) { m_port_input[PORT_B] &= ~(1 << 5); m_port_input[PORT_B] |= (state << 5); }
WRITE_LINE_MEMBER(st6228_device::portb6_w)178 WRITE_LINE_MEMBER(st6228_device::portb6_w) { m_port_input[PORT_B] &= ~(1 << 6); m_port_input[PORT_B] |= (state << 6); }
179
WRITE_LINE_MEMBER(st6228_device::portc4_w)180 WRITE_LINE_MEMBER(st6228_device::portc4_w) { m_port_input[PORT_C] &= ~(1 << 4); m_port_input[PORT_C] |= (state << 4); }
WRITE_LINE_MEMBER(st6228_device::portc5_w)181 WRITE_LINE_MEMBER(st6228_device::portc5_w) { m_port_input[PORT_C] &= ~(1 << 5); m_port_input[PORT_C] |= (state << 5); }
WRITE_LINE_MEMBER(st6228_device::portc6_w)182 WRITE_LINE_MEMBER(st6228_device::portc6_w) { m_port_input[PORT_C] &= ~(1 << 6); m_port_input[PORT_C] |= (state << 6); }
WRITE_LINE_MEMBER(st6228_device::portc7_w)183 WRITE_LINE_MEMBER(st6228_device::portc7_w) { m_port_input[PORT_C] &= ~(1 << 7); m_port_input[PORT_C] |= (state << 7); }
184
WRITE_LINE_MEMBER(st6228_device::portd1_w)185 WRITE_LINE_MEMBER(st6228_device::portd1_w) { m_port_input[PORT_D] &= ~(1 << 1); m_port_input[PORT_D] |= (state << 1); }
WRITE_LINE_MEMBER(st6228_device::portd2_w)186 WRITE_LINE_MEMBER(st6228_device::portd2_w) { m_port_input[PORT_D] &= ~(1 << 2); m_port_input[PORT_D] |= (state << 2); }
WRITE_LINE_MEMBER(st6228_device::portd3_w)187 WRITE_LINE_MEMBER(st6228_device::portd3_w) { m_port_input[PORT_D] &= ~(1 << 3); m_port_input[PORT_D] |= (state << 3); }
WRITE_LINE_MEMBER(st6228_device::portd4_w)188 WRITE_LINE_MEMBER(st6228_device::portd4_w) { m_port_input[PORT_D] &= ~(1 << 4); m_port_input[PORT_D] |= (state << 4); }
WRITE_LINE_MEMBER(st6228_device::portd5_w)189 WRITE_LINE_MEMBER(st6228_device::portd5_w) { m_port_input[PORT_D] &= ~(1 << 5); m_port_input[PORT_D] |= (state << 5); }
WRITE_LINE_MEMBER(st6228_device::portd6_w)190 WRITE_LINE_MEMBER(st6228_device::portd6_w) { m_port_input[PORT_D] &= ~(1 << 6); m_port_input[PORT_D] |= (state << 6); }
WRITE_LINE_MEMBER(st6228_device::portd7_w)191 WRITE_LINE_MEMBER(st6228_device::portd7_w) { m_port_input[PORT_D] &= ~(1 << 7); m_port_input[PORT_D] |= (state << 7); }
192
set_port_output_bit(uint8_t index,uint8_t bit,uint8_t state)193 void st6228_device::set_port_output_bit(uint8_t index, uint8_t bit, uint8_t state)
194 {
195 switch (index)
196 {
197 case PORT_A:
198 if (bit < 6)
199 m_porta_out[bit](state);
200 break;
201 case PORT_B:
202 if (bit >= 4 && bit <= 6)
203 m_portb_out[bit - 4](state);
204 break;
205 case PORT_C:
206 if (bit >= 4)
207 m_portc_out[bit - 4](state);
208 break;
209 case PORT_D:
210 if (bit >= 1)
211 m_portd_out[bit - 1](state);
212 break;
213 }
214 }
215
update_port_mode(uint8_t index,uint8_t changed)216 void st6228_device::update_port_mode(uint8_t index, uint8_t changed)
217 {
218 const uint8_t dir = m_port_dir[index];
219 const uint8_t option = m_port_option[index];
220 for (uint8_t bit = 0; bit < 8; bit++)
221 {
222 const uint8_t mask = (1 << bit);
223 if (BIT(changed, bit) && !BIT(dir, bit))
224 {
225 if (BIT(m_port_data[index], bit))
226 {
227 m_port_irq_enable[index] &= ~mask;
228 m_port_pullup[index] &= ~mask;
229
230 if (BIT(option, bit))
231 m_port_analog[index] |= mask;
232 else
233 m_port_analog[index] &= ~mask;
234 }
235 else
236 {
237 m_port_pullup[index] |= mask;
238 m_port_analog[index] &= ~mask;
239
240 if (BIT(option, bit))
241 m_port_irq_enable[index] |= mask;
242 else
243 m_port_irq_enable[index] &= ~mask;
244 }
245 }
246 else if (BIT(dir, bit))
247 {
248 m_port_pullup[index] &= ~mask;
249 m_port_analog[index] &= ~mask;
250 m_port_irq_enable[index] &= ~mask;
251 }
252 }
253 }
254
regs_w(offs_t offset,uint8_t data)255 void st6228_device::regs_w(offs_t offset, uint8_t data)
256 {
257 offset += 0x80;
258
259 if (offset > REG_W && offset < REG_PORTA_DATA)
260 {
261 // Data RAM
262 m_regs[offset] = data;
263 return;
264 }
265
266 static char PORT_NAMES[4] = { 'A', 'B', 'C', 'D' };
267
268 switch (offset)
269 {
270 case REG_X:
271 case REG_Y:
272 case REG_V:
273 case REG_W:
274 case REG_A:
275 m_regs[offset] = data;
276 break;
277
278 case REG_DATA_ROM_WINDOW:
279 m_regs[offset] = data;
280 m_data_rombank->set_entry(data & 0x7f);
281 break;
282
283 case REG_ROM_BANK_SELECT:
284 m_regs[offset] = data;
285 m_program_rombank->set_entry(data & 3);
286 break;
287
288 case REG_RAM_BANK_SELECT:
289 m_regs[offset] = data;
290 m_rambank->set_entry(data & 1);
291 break;
292
293 case REG_PORTA_DATA:
294 case REG_PORTB_DATA:
295 case REG_PORTC_DATA:
296 case REG_PORTD_DATA:
297 {
298 const uint8_t index = offset - REG_PORTA_DATA;
299 logerror("%s: Port %c data = %02x\n", machine().describe_context(), PORT_NAMES[index], data);
300 const uint8_t old_data = m_port_data[index];
301 const uint8_t changed = old_data ^ data;
302
303 m_port_data[index] = data;
304 update_port_mode(index, changed);
305
306 if (changed & m_port_dir[index])
307 {
308 for (uint8_t bit = 0; bit < 8; bit++)
309 {
310 if (BIT(changed, bit))
311 set_port_output_bit(index, bit, BIT(data, bit));
312 }
313 }
314 break;
315 }
316
317 case REG_PORTA_DIR:
318 case REG_PORTB_DIR:
319 case REG_PORTC_DIR:
320 case REG_PORTD_DIR:
321 {
322 const uint8_t index = offset - REG_PORTA_DIR;
323 logerror("%s: Port %c dir = %02x\n", machine().describe_context(), PORT_NAMES[index], data);
324 const uint8_t old_dir = m_port_dir[index];
325 const uint8_t changed = old_dir ^ data;
326
327 m_port_dir[index] = data;
328 update_port_mode(index, changed);
329
330 if (changed)
331 {
332 for (uint8_t bit = 0; bit < 8; bit++)
333 {
334 if (BIT(changed, bit))
335 {
336 set_port_output_bit(index, bit, BIT(m_port_data[index], bit));
337 }
338 }
339 }
340 break;
341 }
342
343 case REG_PORTA_OPTION:
344 case REG_PORTB_OPTION:
345 case REG_PORTC_OPTION:
346 case REG_PORTD_OPTION:
347 {
348 const uint8_t index = offset - REG_PORTA_OPTION;
349 logerror("%s: Port %c option = %02x\n", machine().describe_context(), PORT_NAMES[index], data);
350
351 const uint8_t changed = m_port_option[index] ^ data;
352 m_port_option[index] = data;
353
354 update_port_mode(index, changed);
355 break;
356 }
357
358 case REG_WATCHDOG:
359 // Do nothing for now
360 break;
361
362 default:
363 logerror("%s: Unknown register write: %02x = %02x\n", machine().describe_context(), offset, data);
364 break;
365 }
366 }
367
regs_r(offs_t offset)368 uint8_t st6228_device::regs_r(offs_t offset)
369 {
370 uint8_t ret = 0;
371 offset += 0x80;
372
373 if (offset > REG_W && offset < REG_PORTA_DATA)
374 {
375 // Data RAM
376 return m_regs[offset];
377 }
378
379 static char PORT_NAMES[4] = { 'A', 'B', 'C', 'D' };
380
381 switch (offset)
382 {
383 case REG_X:
384 case REG_Y:
385 case REG_V:
386 case REG_W:
387 case REG_A:
388 ret = m_regs[offset];
389 break;
390
391 case REG_PORTA_DATA:
392 case REG_PORTB_DATA:
393 case REG_PORTC_DATA:
394 case REG_PORTD_DATA:
395 {
396 const uint8_t index = offset - REG_PORTA_DATA;
397 ret = (m_port_data[index] & m_port_dir[index]) |
398 (m_port_input[index] & ~m_port_dir[index]) |
399 (m_port_pullup[index] & ~m_port_dir[index]);
400 logerror("%s: Port %c data read (%02x)\n", machine().describe_context(), PORT_NAMES[index], ret);
401 break;
402 }
403
404 case REG_PORTA_DIR:
405 case REG_PORTB_DIR:
406 case REG_PORTC_DIR:
407 case REG_PORTD_DIR:
408 {
409 const uint8_t index = offset - REG_PORTA_DIR;
410 ret = m_port_dir[index];
411 logerror("%s: Port %c direction read (%02x)\n", machine().describe_context(), PORT_NAMES[index], ret);
412 break;
413 }
414
415 case REG_PORTA_OPTION:
416 case REG_PORTB_OPTION:
417 case REG_PORTC_OPTION:
418 case REG_PORTD_OPTION:
419 {
420 const uint8_t index = offset - REG_PORTA_OPTION;
421 ret = m_port_option[index];
422 logerror("%s: Port %c option read (%02x)\n", machine().describe_context(), PORT_NAMES[index], ret);
423 break;
424 }
425
426 default:
427 logerror("%s: Unknown register read: %02x\n", machine().describe_context(), offset);
428 break;
429 }
430 return ret;
431 }
432
execute_min_cycles() const433 uint32_t st6228_device::execute_min_cycles() const noexcept
434 {
435 return 2;
436 }
437
execute_max_cycles() const438 uint32_t st6228_device::execute_max_cycles() const noexcept
439 {
440 return 5;
441 }
442
execute_input_lines() const443 uint32_t st6228_device::execute_input_lines() const noexcept
444 {
445 return 0;
446 }
447
execute_set_input(int inputnum,int state)448 void st6228_device::execute_set_input(int inputnum, int state)
449 {
450 logerror("%s: Unimplemented: execute_set_input line %d = %d\n", machine().describe_context(), inputnum, state);
451 }
452
tick_timers(int cycles)453 void st6228_device::tick_timers(int cycles)
454 {
455 }
456
unimplemented_opcode(uint8_t op)457 void st6228_device::unimplemented_opcode(uint8_t op)
458 {
459 fatalerror("ST62xx: unknown opcode (%02x) at %04x\n", op, m_pc);
460 }
461
execute_run()462 void st6228_device::execute_run()
463 {
464 while (m_icount > 0)
465 {
466 debugger_instruction_hook(m_pc);
467
468 uint8_t op = m_program->read_byte(m_pc);
469
470 int cycles = 4;
471
472 switch (op)
473 {
474 case 0x00: case 0x10: case 0x20: case 0x30: case 0x40: case 0x50: case 0x60: case 0x70:
475 case 0x80: case 0xa0: case 0xb0: case 0xc0: case 0xd0: case 0xe0: case 0xf0:
476 case 0x08: case 0x18: case 0x28: case 0x38: case 0x48: case 0x58: case 0x68: case 0x78:
477 case 0x88: case 0xa8: case 0xb8: case 0xc8: case 0xd8: case 0xe8: case 0xf8: // JRNZ e
478 {
479 const int8_t e = ((int8_t)op) >> 3;
480 if (!(m_flags[m_mode] & FLAG_Z))
481 m_pc += e;
482 break;
483 }
484 case 0x01: case 0x11: case 0x21: case 0x31: case 0x41: case 0x51: case 0x61: case 0x71:
485 case 0x81: case 0x91: case 0xa1: case 0xb1: case 0xc1: case 0xd1: case 0xe1: case 0xf1: // CALL abc
486 {
487 const uint8_t ab = m_program->read_byte(m_pc+1);
488 m_pc += 2;
489 const uint16_t abc = ((op & 0xf0) >> 4) | (ab << 4);
490 if (m_stack_index < 6) // FIXME: magic numbers
491 {
492 m_stack[m_stack_index] = m_pc;
493 m_stack_index++;
494 }
495 else
496 {
497 // Per documentation: "If more calls [than the maximum] are nested, the latest stacked PC
498 // values will be lost. In this case, returns will return to the PC
499 // values stacked first."
500 }
501 m_pc = abc-1;
502 break;
503 }
504 case 0x09: case 0x19: case 0x29: case 0x39: case 0x49: case 0x59: case 0x69: case 0x79:
505 case 0x89: case 0x99: case 0xa9: case 0xb9: case 0xc9: case 0xd9: case 0xe9: case 0xf9: // JP abc
506 {
507 const uint8_t ab = m_program->read_byte(m_pc+1);
508 const uint16_t abc = ((op & 0xf0) >> 4) | (ab << 4);
509 m_pc = abc-1;
510 break;
511 }
512 case 0x02: case 0x12: case 0x22: case 0x32: case 0x42: case 0x52: case 0x62: case 0x72:
513 case 0x82: case 0x92: case 0xa2: case 0xb2: case 0xc2: case 0xd2: case 0xe2: case 0xf2:
514 case 0x0a: case 0x1a: case 0x2a: case 0x3a: case 0x4a: case 0x5a: case 0x6a: case 0x7a:
515 case 0x8a: case 0x9a: case 0xaa: case 0xba: case 0xca: case 0xda: case 0xea: case 0xfa: // JRNC abc
516 {
517 const int8_t e = ((int8_t)op) >> 3;
518 if (!(m_flags[m_mode] & FLAG_C))
519 m_pc += e;
520 break;
521 }
522 case 0x03: case 0x23: case 0x43: case 0x63: case 0x83: case 0xa3: case 0xc3: case 0xe3: // JRR b,rr,ee
523 {
524 const uint8_t b = (op >> 5) & 7;
525 const uint8_t rr = m_program->read_byte(m_pc+1);
526 const int8_t ee = (int8_t)m_program->read_byte(m_pc+2);
527 const uint8_t value = m_data->read_byte(rr);
528 m_pc += 2;
529 if (!BIT(value, b))
530 m_pc += ee;
531 break;
532 }
533 case 0x13: case 0x33: case 0x53: case 0x73: case 0x93: case 0xb3: case 0xd3: case 0xf3: // JRS b,rr,ee
534 {
535 const uint8_t b = (op >> 5) & 7;
536 const uint8_t rr = m_program->read_byte(m_pc+1);
537 const int8_t ee = (int8_t)m_program->read_byte(m_pc+2);
538 const uint8_t value = m_data->read_byte(rr);
539 m_pc += 2;
540 if (BIT(value, b))
541 m_pc += ee;
542 break;
543 }
544 case 0x0b: case 0x2b: case 0x4b: case 0x6b: case 0x8b: case 0xab: case 0xcb: case 0xeb: // RES b,rr
545 {
546 const uint8_t b = (op >> 5) & 7;
547 const uint8_t rr = m_program->read_byte(m_pc+1);
548 const uint8_t nn = m_data->read_byte(rr);
549 m_data->write_byte(rr, nn & ~(1 << b));
550 m_pc++;
551 break;
552 }
553 case 0x1b: case 0x3b: case 0x5b: case 0x7b: case 0x9b: case 0xbb: case 0xdb: case 0xfb: // SET b,rr
554 {
555 const uint8_t b = (op >> 5) & 7;
556 const uint8_t rr = m_program->read_byte(m_pc+1);
557 const uint8_t nn = m_data->read_byte(rr);
558 m_data->write_byte(rr, nn | (1 << b));
559 m_pc++;
560 break;
561 }
562 case 0x04: case 0x14: case 0x24: case 0x34: case 0x44: case 0x54: case 0x64: case 0x74:
563 case 0x84: case 0x94: case 0xa4: case 0xb4: case 0xc4: case 0xd4: case 0xe4: case 0xf4:
564 case 0x0c: case 0x1c: case 0x2c: case 0x3c: case 0x4c: case 0x5c: case 0x6c: case 0x7c:
565 case 0x8c: case 0x9c: case 0xac: case 0xbc: case 0xcc: case 0xdc: case 0xec: case 0xfc: // JRZ e
566 {
567 const int8_t e = ((int8_t)op) >> 3;
568 if (m_flags[m_mode] & FLAG_Z)
569 m_pc += e;
570 break;
571 }
572 case 0x06: case 0x16: case 0x26: case 0x36: case 0x46: case 0x56: case 0x66: case 0x76:
573 case 0x86: case 0x96: case 0xa6: case 0xb6: case 0xc6: case 0xd6: case 0xe6: case 0xf6:
574 case 0x0e: case 0x1e: case 0x2e: case 0x3e: case 0x4e: case 0x5e: case 0x6e: case 0x7e:
575 case 0x8e: case 0x9e: case 0xae: case 0xbe: case 0xce: case 0xde: case 0xee: case 0xfe: // JRC e
576 {
577 const int8_t e = ((int8_t)op) >> 3;
578 if (m_flags[m_mode] & FLAG_C)
579 m_pc += e;
580 break;
581 }
582 case 0x15: // INC X
583 m_regs[REG_X]++;
584
585 if (m_regs[REG_X])
586 m_flags[m_mode] &= ~FLAG_Z;
587 else
588 m_flags[m_mode] |= FLAG_Z;
589 break;
590 case 0x35: // LD A,X
591 m_regs[REG_A] = m_regs[REG_X];
592
593 if (m_regs[REG_A])
594 m_flags[m_mode] &= ~FLAG_Z;
595 else
596 m_flags[m_mode] |= FLAG_Z;
597 break;
598 case 0x55: // INC Y
599 m_regs[REG_Y]++;
600
601 if (m_regs[REG_Y])
602 m_flags[m_mode] &= ~FLAG_Z;
603 else
604 m_flags[m_mode] |= FLAG_Z;
605 break;
606 case 0x75: // LD A,Y
607 m_regs[REG_A] = m_regs[REG_Y];
608
609 if (m_regs[REG_A])
610 m_flags[m_mode] &= ~FLAG_Z;
611 else
612 m_flags[m_mode] |= FLAG_Z;
613 break;
614 case 0x95: // INC V
615 m_regs[REG_V]++;
616
617 if (m_regs[REG_V])
618 m_flags[m_mode] &= ~FLAG_Z;
619 else
620 m_flags[m_mode] |= FLAG_Z;
621 break;
622 case 0xb5: // LD A,V
623 m_regs[REG_A] = m_regs[REG_V];
624
625 if (m_regs[REG_A])
626 m_flags[m_mode] &= ~FLAG_Z;
627 else
628 m_flags[m_mode] |= FLAG_Z;
629 break;
630 case 0xd5: // INC W
631 m_regs[REG_W]++;
632
633 if (m_regs[REG_W])
634 m_flags[m_mode] &= ~FLAG_Z;
635 else
636 m_flags[m_mode] |= FLAG_Z;
637 break;
638 case 0xf5: // LD A,W
639 m_regs[REG_A] = m_regs[REG_W];
640
641 if (m_regs[REG_A])
642 m_flags[m_mode] &= ~FLAG_Z;
643 else
644 m_flags[m_mode] |= FLAG_Z;
645 break;
646 case 0x0d: // LDI rr,nn
647 {
648 const uint8_t rr = m_program->read_byte(m_pc+1);
649 const uint8_t nn = m_program->read_byte(m_pc+2);
650 m_data->write_byte(rr, nn);
651
652 if (nn)
653 m_flags[m_mode] &= ~FLAG_Z;
654 else
655 m_flags[m_mode] |= FLAG_Z;
656 m_pc += 2;
657 break;
658 }
659 case 0x1d: // DEC X
660 m_regs[REG_X]--;
661
662 if (m_regs[REG_X])
663 m_flags[m_mode] &= ~FLAG_Z;
664 else
665 m_flags[m_mode] |= FLAG_Z;
666 break;
667 case 0x2d: // COM A
668 if (BIT(m_regs[REG_A], 7))
669 m_flags[m_mode] |= FLAG_C;
670 else
671 m_flags[m_mode] &= FLAG_C;
672
673 m_regs[REG_A] = ~m_regs[REG_A];
674
675 if (m_regs[REG_A])
676 m_flags[m_mode] &= ~FLAG_Z;
677 else
678 m_flags[m_mode] |= FLAG_Z;
679 break;
680 case 0x3d: // LD X,A
681 m_regs[REG_X] = m_regs[REG_A];
682
683 if (m_regs[REG_X])
684 m_flags[m_mode] &= ~FLAG_Z;
685 else
686 m_flags[m_mode] |= FLAG_Z;
687 break;
688 case 0x4d:
689 if (m_stack_index > 0)
690 {
691 m_stack_index--;
692 m_pc = m_stack[m_stack_index] - 1;
693 m_mode = m_prev_mode;
694 m_prev_mode = MODE_NORMAL;
695 }
696 else
697 {
698 fatalerror("Attempted to RETI with nothing on the stack");
699 }
700 break;
701 case 0x5d: // DEC Y
702 m_regs[REG_Y]--;
703
704 if (m_regs[REG_Y])
705 m_flags[m_mode] &= ~FLAG_Z;
706 else
707 m_flags[m_mode] |= FLAG_Z;
708 break;
709 case 0x6d:
710 //util::stream_format(stream, "STOP");
711 break;
712 case 0x7d: // LD Y,A
713 m_regs[REG_Y] = m_regs[REG_A];
714
715 if (m_regs[REG_Y])
716 m_flags[m_mode] &= ~FLAG_Z;
717 else
718 m_flags[m_mode] |= FLAG_Z;
719 break;
720 case 0x9d: // DEC V
721 m_regs[REG_V]--;
722
723 if (m_regs[REG_V])
724 m_flags[m_mode] &= ~FLAG_Z;
725 else
726 m_flags[m_mode] |= FLAG_Z;
727 break;
728 case 0xad: // RLC
729 {
730 const uint8_t old_c = (m_flags[m_mode] & FLAG_C) ? 1 : 0;
731 if (BIT(m_regs[REG_A], 7))
732 m_flags[m_mode] |= FLAG_C;
733 else
734 m_flags[m_mode] &= ~FLAG_C;
735 m_regs[REG_A] = (m_regs[REG_A] << 1) | old_c;
736
737 if (m_regs[REG_A])
738 m_flags[m_mode] &= ~FLAG_Z;
739 else
740 m_flags[m_mode] |= FLAG_Z;
741 break;
742 }
743 case 0xbd: // LD V,A
744 m_regs[REG_V] = m_regs[REG_A];
745
746 if (m_regs[REG_V])
747 m_flags[m_mode] &= ~FLAG_Z;
748 else
749 m_flags[m_mode] |= FLAG_Z;
750 break;
751 case 0xcd:
752 if (m_stack_index > 0)
753 {
754 m_stack_index--;
755 m_pc = m_stack[m_stack_index] - 1;
756 }
757 else
758 {
759 fatalerror("Attempted to RET with nothing on the stack");
760 }
761 break;
762 case 0xdd: // DEC W
763 m_regs[REG_W]--;
764
765 if (m_regs[REG_W])
766 m_flags[m_mode] &= ~FLAG_Z;
767 else
768 m_flags[m_mode] |= FLAG_Z;
769 break;
770 case 0xed:
771 //util::stream_format(stream, "WAIT");
772 break;
773 case 0xfd: // LD W,A
774 m_regs[REG_W] = m_regs[REG_A];
775
776 if (m_regs[REG_W])
777 m_flags[m_mode] &= ~FLAG_Z;
778 else
779 m_flags[m_mode] |= FLAG_Z;
780 break;
781 case 0x07: // LD A,(X)
782 m_regs[REG_A] = m_data->read_byte(m_regs[REG_X]);
783
784 if (m_regs[REG_A])
785 m_flags[m_mode] &= ~FLAG_Z;
786 else
787 m_flags[m_mode] |= FLAG_Z;
788 break;
789 case 0x17: // LDI A,rr
790 {
791 m_regs[REG_A] = m_program->read_byte(m_pc+1);
792
793 if (m_regs[REG_A])
794 m_flags[m_mode] &= ~FLAG_Z;
795 else
796 m_flags[m_mode] |= FLAG_Z;
797 m_pc++;
798 break;
799 }
800 case 0x27: // CP A,(X)
801 {
802 const uint8_t nn = m_data->read_byte(m_regs[REG_X]);
803
804 if (m_regs[REG_A] < nn)
805 {
806 m_flags[m_mode] |= FLAG_C;
807 m_flags[m_mode] &= ~FLAG_Z;
808 }
809 else
810 {
811 m_flags[m_mode] &= ~FLAG_C;
812 if (m_regs[REG_A] == nn)
813 m_flags[m_mode] |= FLAG_Z;
814 else
815 m_flags[m_mode] &= ~FLAG_Z;
816 }
817 break;
818 }
819 case 0x37: // CPI A,nn
820 {
821 const uint8_t nn = m_program->read_byte(m_pc+1);
822
823 if (m_regs[REG_A] < nn)
824 {
825 m_flags[m_mode] |= FLAG_C;
826 m_flags[m_mode] &= ~FLAG_Z;
827 }
828 else
829 {
830 m_flags[m_mode] &= ~FLAG_C;
831 if (m_regs[REG_A] == nn)
832 m_flags[m_mode] |= FLAG_Z;
833 else
834 m_flags[m_mode] &= ~FLAG_Z;
835 }
836 m_pc++;
837 break;
838 }
839 case 0x47: // ADD A,(X)
840 {
841 const uint8_t nn = m_data->read_byte(m_regs[REG_X]);
842 const uint16_t sum = m_regs[REG_A] + nn;
843
844 if (sum > 0xff)
845 {
846 m_flags[m_mode] |= FLAG_C;
847 m_flags[m_mode] &= ~FLAG_Z;
848 }
849 else
850 {
851 m_flags[m_mode] &= ~FLAG_C;
852 if (sum == 0)
853 m_flags[m_mode] |= FLAG_Z;
854 else
855 m_flags[m_mode] &= ~FLAG_Z;
856 }
857 m_regs[REG_A] = (uint8_t)sum;
858 break;
859 }
860 case 0x57: // ADDI A,nn
861 {
862 const uint8_t nn = m_program->read_byte(m_pc+1);
863 const uint16_t sum = m_regs[REG_A] + nn;
864
865 if (sum > 0xff)
866 {
867 m_flags[m_mode] |= FLAG_C;
868 m_flags[m_mode] &= ~FLAG_Z;
869 }
870 else
871 {
872 m_flags[m_mode] &= ~FLAG_C;
873 if (sum == 0)
874 m_flags[m_mode] |= FLAG_Z;
875 else
876 m_flags[m_mode] &= ~FLAG_Z;
877 }
878 m_regs[REG_A] = (uint8_t)sum;
879 m_pc++;
880 break;
881 }
882 case 0x67: // INC (X)
883 {
884 const uint8_t rr = m_data->read_byte(m_regs[REG_X]) + 1;
885 m_data->write_byte(m_regs[REG_X], rr);
886
887 if (rr)
888 m_flags[m_mode] &= ~FLAG_Z;
889 else
890 m_flags[m_mode] |= FLAG_Z;
891 break;
892 }
893 case 0x87: // LD (X),A
894 m_data->write_byte(m_regs[REG_X], m_regs[REG_A]);
895
896 if (m_regs[REG_A])
897 m_flags[m_mode] &= ~FLAG_Z;
898 else
899 m_flags[m_mode] |= FLAG_Z;
900 break;
901 case 0xa7: // AND A,(X)
902 m_regs[REG_A] &= m_data->read_byte(m_regs[REG_X]);
903
904 if (m_regs[REG_A])
905 m_flags[m_mode] &= ~FLAG_Z;
906 else
907 m_flags[m_mode] |= FLAG_Z;
908 break;
909 case 0xb7: // ANDI A,nn
910 {
911 m_regs[REG_A] &= m_program->read_byte(m_pc+1);
912
913 if (m_regs[REG_A])
914 m_flags[m_mode] &= ~FLAG_Z;
915 else
916 m_flags[m_mode] |= FLAG_Z;
917 m_pc++;
918 break;
919 }
920 case 0xc7: // SUB A,(X)
921 {
922 const uint8_t nn = m_data->read_byte(m_regs[REG_X]);
923
924 if (m_regs[REG_A] < nn)
925 {
926 m_flags[m_mode] |= FLAG_C;
927 m_flags[m_mode] &= ~FLAG_Z;
928 }
929 else
930 {
931 m_flags[m_mode] &= ~FLAG_C;
932 if (m_regs[REG_A] == nn)
933 m_flags[m_mode] |= FLAG_Z;
934 else
935 m_flags[m_mode] &= ~FLAG_Z;
936 }
937 m_regs[REG_A] -= nn;
938 break;
939 }
940 case 0xd7: // SUBI A,nn
941 {
942 const uint8_t nn = m_program->read_byte(m_pc+1);
943
944 if (m_regs[REG_A] < nn)
945 {
946 m_flags[m_mode] |= FLAG_C;
947 m_flags[m_mode] &= ~FLAG_Z;
948 }
949 else
950 {
951 m_flags[m_mode] &= ~FLAG_C;
952 if (m_regs[REG_A] == nn)
953 m_flags[m_mode] |= FLAG_Z;
954 else
955 m_flags[m_mode] &= ~FLAG_Z;
956 }
957 m_regs[REG_A] -= nn;
958 m_pc++;
959 break;
960 }
961 case 0xe7: // DEC (X)
962 {
963 const uint8_t rr = m_data->read_byte(m_regs[REG_X]) - 1;
964 m_data->write_byte(m_regs[REG_X], rr);
965
966 if (rr)
967 m_flags[m_mode] &= ~FLAG_Z;
968 else
969 m_flags[m_mode] |= FLAG_Z;
970 break;
971 }
972 case 0x0f: // LD A,(Y)
973 m_regs[REG_A] = m_data->read_byte(m_regs[REG_Y]);
974
975 if (m_regs[REG_A])
976 m_flags[m_mode] &= ~FLAG_Z;
977 else
978 m_flags[m_mode] |= FLAG_Z;
979 break;
980 case 0x1f: // LD A,rr
981 {
982 m_regs[REG_A] = m_data->read_byte(m_program->read_byte(m_pc+1));
983
984 if (m_regs[REG_V])
985 m_flags[m_mode] &= ~FLAG_Z;
986 else
987 m_flags[m_mode] |= FLAG_Z;
988 m_pc++;
989 break;
990 }
991 case 0x2f: // CP A,(Y)
992 {
993 const uint8_t nn = m_data->read_byte(m_regs[REG_Y]);
994
995 if (m_regs[REG_A] < nn)
996 {
997 m_flags[m_mode] |= FLAG_C;
998 m_flags[m_mode] &= ~FLAG_Z;
999 }
1000 else
1001 {
1002 m_flags[m_mode] &= ~FLAG_C;
1003 if (m_regs[REG_A] == nn)
1004 m_flags[m_mode] |= FLAG_Z;
1005 else
1006 m_flags[m_mode] &= ~FLAG_Z;
1007 }
1008 break;
1009 }
1010 case 0x3f: // CP A,rr
1011 {
1012 const uint8_t nn = m_data->read_byte(m_program->read_byte(m_pc+1));
1013
1014 if (m_regs[REG_A] < nn)
1015 {
1016 m_flags[m_mode] |= FLAG_C;
1017 m_flags[m_mode] &= ~FLAG_Z;
1018 }
1019 else
1020 {
1021 m_flags[m_mode] &= ~FLAG_C;
1022 if (m_regs[REG_A] == nn)
1023 m_flags[m_mode] |= FLAG_Z;
1024 else
1025 m_flags[m_mode] &= ~FLAG_Z;
1026 }
1027 m_pc++;
1028 break;
1029 }
1030 case 0x4f: // ADD A,(Y)
1031 {
1032 const uint8_t nn = m_data->read_byte(m_regs[REG_Y]);
1033 const uint16_t sum = m_regs[REG_A] + nn;
1034
1035 if (sum > 0xff)
1036 {
1037 m_flags[m_mode] |= FLAG_C;
1038 m_flags[m_mode] &= ~FLAG_Z;
1039 }
1040 else
1041 {
1042 m_flags[m_mode] &= ~FLAG_C;
1043 if (sum == 0)
1044 m_flags[m_mode] |= FLAG_Z;
1045 else
1046 m_flags[m_mode] &= ~FLAG_Z;
1047 }
1048 m_regs[REG_A] = (uint8_t)sum;
1049 break;
1050 }
1051 case 0x5f: // ADD A,rr
1052 {
1053 const uint8_t nn = m_data->read_byte(m_program->read_byte(m_pc+1));
1054 const uint16_t sum = m_regs[REG_A] + nn;
1055
1056 if (sum > 0xff)
1057 {
1058 m_flags[m_mode] |= FLAG_C;
1059 m_flags[m_mode] &= ~FLAG_Z;
1060 }
1061 else
1062 {
1063 m_flags[m_mode] &= ~FLAG_C;
1064 if (sum == 0)
1065 m_flags[m_mode] |= FLAG_Z;
1066 else
1067 m_flags[m_mode] &= ~FLAG_Z;
1068 }
1069 m_regs[REG_A] = (uint8_t)sum;
1070 m_pc++;
1071 break;
1072 }
1073 case 0x6f: // INC (Y)
1074 {
1075 const uint8_t rr = m_data->read_byte(m_regs[REG_Y]) + 1;
1076 m_data->write_byte(m_regs[REG_Y], rr);
1077
1078 if (rr)
1079 m_flags[m_mode] &= ~FLAG_Z;
1080 else
1081 m_flags[m_mode] |= FLAG_Z;
1082 break;
1083 }
1084 case 0x7f: // INC rr
1085 {
1086 const uint8_t rr = m_program->read_byte(m_pc+1);
1087 const uint8_t nn = m_data->read_byte(rr) + 1;
1088 m_data->write_byte(rr, nn);
1089
1090 if (nn)
1091 m_flags[m_mode] &= ~FLAG_Z;
1092 else
1093 m_flags[m_mode] |= FLAG_Z;
1094 m_pc++;
1095 break;
1096 }
1097 case 0x8f: // LD (Y),A
1098 m_data->write_byte(m_regs[REG_Y], m_regs[REG_A]);
1099
1100 if (m_regs[REG_A])
1101 m_flags[m_mode] &= ~FLAG_Z;
1102 else
1103 m_flags[m_mode] |= FLAG_Z;
1104 break;
1105 case 0x9f: // LD rr,A
1106 {
1107 m_regs[REG_A] = m_data->read_byte(m_program->read_byte(m_pc+1));
1108
1109 if (m_regs[REG_A])
1110 m_flags[m_mode] &= ~FLAG_Z;
1111 else
1112 m_flags[m_mode] |= FLAG_Z;
1113 m_pc++;
1114 break;
1115 }
1116 case 0xaf: // AND A,(Y)
1117 m_regs[REG_A] &= m_data->read_byte(m_regs[REG_Y]);
1118
1119 if (m_regs[REG_A])
1120 m_flags[m_mode] &= ~FLAG_Z;
1121 else
1122 m_flags[m_mode] |= FLAG_Z;
1123
1124 break;
1125 case 0xbf: // AND A,rr
1126 {
1127 m_regs[REG_A] &= m_data->read_byte(m_program->read_byte(m_pc+1));
1128
1129 if (m_regs[REG_A])
1130 m_flags[m_mode] &= ~FLAG_Z;
1131 else
1132 m_flags[m_mode] |= FLAG_Z;
1133 m_pc++;
1134 break;
1135 }
1136 case 0xcf: // SUB A,(Y)
1137 {
1138 const uint8_t nn = m_data->read_byte(m_regs[REG_Y]);
1139
1140 if (m_regs[REG_A] < nn)
1141 {
1142 m_flags[m_mode] |= FLAG_C;
1143 m_flags[m_mode] &= ~FLAG_Z;
1144 }
1145 else
1146 {
1147 m_flags[m_mode] &= ~FLAG_C;
1148 if (m_regs[REG_A] == nn)
1149 m_flags[m_mode] |= FLAG_Z;
1150 else
1151 m_flags[m_mode] &= ~FLAG_Z;
1152 }
1153 m_regs[REG_A] -= nn;
1154 break;
1155 }
1156 case 0xdf: // SUB A,rr
1157 {
1158 const uint8_t nn = m_data->read_byte(m_program->read_byte(m_pc+1));
1159
1160 if (m_regs[REG_A] < nn)
1161 {
1162 m_flags[m_mode] |= FLAG_C;
1163 m_flags[m_mode] &= ~FLAG_Z;
1164 }
1165 else
1166 {
1167 m_flags[m_mode] &= ~FLAG_C;
1168 if (m_regs[REG_A] == nn)
1169 m_flags[m_mode] |= FLAG_Z;
1170 else
1171 m_flags[m_mode] &= ~FLAG_Z;
1172 }
1173 m_regs[REG_A] -= nn;
1174 m_pc++;
1175 break;
1176 }
1177 case 0xef: // DEC (Y)
1178 {
1179 const uint8_t rr = m_data->read_byte(m_regs[REG_Y]) - 1;
1180 m_data->write_byte(m_regs[REG_Y], rr);
1181
1182 if (rr)
1183 m_flags[m_mode] &= ~FLAG_Z;
1184 else
1185 m_flags[m_mode] |= FLAG_Z;
1186 break;
1187 }
1188 case 0xff: // DEC rr
1189 {
1190 const uint8_t rr = m_program->read_byte(m_pc+1);
1191 const uint8_t value = m_data->read_byte(rr) - 1;
1192 m_data->write_byte(rr, value);
1193
1194 if (value)
1195 m_flags[m_mode] &= ~FLAG_Z;
1196 else
1197 m_flags[m_mode] |= FLAG_Z;
1198 m_pc++;
1199 break;
1200 }
1201 default:
1202 logerror("%s: Unsupported opcode: %02x\n", op);
1203 }
1204
1205 m_pc++;
1206
1207 tick_timers(cycles);
1208
1209 m_icount -= cycles;
1210 }
1211 }
1212