1 // license:BSD-3-Clause 2 // copyright-holders:Ryan Holtz 3 /************************************************************************** 4 * 5 * Intel XScale PXA255 peripheral emulation 6 * 7 * TODO: 8 * Most things 9 * 10 **************************************************************************/ 11 12 #ifndef MAME_MACHINE_PXA255 13 #define MAME_MACHINE_PXA255 14 15 #pragma once 16 17 #include "cpu/arm7/arm7.h" 18 #include "cpu/arm7/arm7core.h" 19 #include "sound/dmadac.h" 20 #include "emupal.h" 21 22 #include "pxa255defs.h" 23 24 25 class pxa255_periphs_device : public device_t 26 { 27 public: 28 template <typename T> pxa255_periphs_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock,T && cpu_tag)29 pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag) 30 : pxa255_periphs_device(mconfig, tag, owner, clock) 31 { 32 m_maincpu.set_tag(std::forward<T>(cpu_tag)); 33 } 34 35 pxa255_periphs_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 36 gpio0_write()37 auto gpio0_write() { return m_gpio0_w.bind(); } gpio0_read()38 auto gpio0_read() { return m_gpio0_r.bind(); } gpio1_write()39 auto gpio1_write() { return m_gpio1_w.bind(); } gpio1_read()40 auto gpio1_read() { return m_gpio1_r.bind(); } gpio2_write()41 auto gpio2_write() { return m_gpio2_w.bind(); } gpio2_read()42 auto gpio2_read() { return m_gpio2_r.bind(); } 43 44 uint32_t dma_r(offs_t offset, uint32_t mem_mask = ~0); 45 void dma_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 46 uint32_t i2s_r(offs_t offset, uint32_t mem_mask = ~0); 47 void i2s_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 48 uint32_t rtc_r(offs_t offset, uint32_t mem_mask = ~0); 49 void rtc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 50 uint32_t ostimer_r(offs_t offset, uint32_t mem_mask = ~0); 51 void ostimer_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 52 uint32_t intc_r(offs_t offset, uint32_t mem_mask = ~0); 53 void intc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 54 void gpio_bit_w(offs_t offset, uint8_t data, uint8_t mem_mask = ~0); 55 uint32_t gpio_r(offs_t offset, uint32_t mem_mask = ~0); 56 void gpio_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 57 uint32_t lcd_r(offs_t offset, uint32_t mem_mask = ~0); 58 void lcd_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 59 uint32_t power_r(offs_t offset, uint32_t mem_mask = ~0); 60 void power_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 61 uint32_t clocks_r(offs_t offset, uint32_t mem_mask = ~0); 62 void clocks_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 63 64 protected: 65 virtual void device_add_mconfig(machine_config &config) override; 66 virtual void device_start() override; 67 virtual void device_reset() override; 68 virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; 69 70 static const device_timer_id TIMER_DMA0 = 0; 71 static const device_timer_id TIMER_OSTIMER0 = 16; 72 static const device_timer_id TIMER_LCD_EOF0 = 20; 73 static const device_timer_id TIMER_RTC = 22; 74 75 void dma_irq_check(); 76 void dma_load_descriptor_and_start(int channel); 77 void ostimer_irq_check(); 78 void update_interrupts(); 79 void lcd_load_dma_descriptor(address_space & space, uint32_t address, int channel); 80 void lcd_irq_check(); 81 void lcd_dma_kickoff(int channel); 82 void lcd_check_load_next_branch(int channel); 83 84 uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 85 86 void dma_end_tick(int channel); 87 void ostimer_match_tick(int channel); 88 void lcd_dma_eof_tick(int channel); 89 void rtc_tick(); 90 91 void set_irq_line(uint32_t line, int state); 92 93 struct dma_regs 94 { 95 uint32_t dcsr[16]; 96 uint32_t pad0[44]; 97 98 uint32_t dint; 99 uint32_t pad1[3]; 100 101 uint32_t drcmr[40]; 102 uint32_t pad2[24]; 103 104 uint32_t ddadr[16]; 105 uint32_t dsadr[16]; 106 uint32_t dtadr[16]; 107 uint32_t dcmd[16]; 108 109 emu_timer* timer[16]; 110 }; 111 112 struct i2s_regs 113 { 114 uint32_t sacr0; 115 uint32_t sacr1; 116 uint32_t pad0; 117 118 uint32_t sasr0; 119 uint32_t pad1; 120 121 uint32_t saimr; 122 uint32_t saicr; 123 uint32_t pad2[17]; 124 125 uint32_t sadiv; 126 uint32_t pad3[6]; 127 128 uint32_t sadr; 129 }; 130 131 struct rtc_regs 132 { 133 uint32_t rcnr; 134 uint32_t rtar; 135 uint32_t rtsr; 136 uint32_t rttr; 137 emu_timer *timer; 138 }; 139 140 struct ostmr_regs 141 { 142 uint32_t osmr[4]; 143 uint32_t oscr; 144 uint32_t ossr; 145 uint32_t ower; 146 uint32_t oier; 147 148 emu_timer* timer[4]; 149 }; 150 151 struct intc_regs 152 { 153 uint32_t icip; 154 uint32_t icmr; 155 uint32_t iclr; 156 uint32_t icfp; 157 uint32_t icpr; 158 uint32_t iccr; 159 }; 160 161 struct gpio_regs 162 { 163 uint32_t gplr0; // GPIO Pin-Level 164 uint32_t gplr1; 165 uint32_t gplr2; 166 167 uint32_t gpdr0; 168 uint32_t gpdr1; 169 uint32_t gpdr2; 170 171 uint32_t gpsr0; 172 uint32_t gpsr1; 173 uint32_t gpsr2; 174 175 uint32_t gpcr0; 176 uint32_t gpcr1; 177 uint32_t gpcr2; 178 179 uint32_t grer0; 180 uint32_t grer1; 181 uint32_t grer2; 182 183 uint32_t gfer0; 184 uint32_t gfer1; 185 uint32_t gfer2; 186 187 uint32_t gedr0; 188 uint32_t gedr1; 189 uint32_t gedr2; 190 191 uint32_t gafr0l; 192 uint32_t gafr0u; 193 uint32_t gafr1l; 194 uint32_t gafr1u; 195 uint32_t gafr2l; 196 uint32_t gafr2u; 197 }; 198 199 struct lcd_dma_regs 200 { 201 uint32_t fdadr; 202 uint32_t fsadr; 203 uint32_t fidr; 204 uint32_t ldcmd; 205 emu_timer *eof; 206 }; 207 208 struct lcd_regs 209 { 210 uint32_t lccr0; 211 uint32_t lccr1; 212 uint32_t lccr2; 213 uint32_t lccr3; 214 215 uint32_t fbr[2]; 216 217 uint32_t lcsr; 218 uint32_t liidr; 219 uint32_t trgbr; 220 uint32_t tcr; 221 222 lcd_dma_regs dma[2]; 223 }; 224 225 struct power_regs 226 { 227 uint32_t pmcr; 228 uint32_t pssr; 229 uint32_t pspr; 230 uint32_t pwer; 231 uint32_t prer; 232 uint32_t pfer; 233 uint32_t pedr; 234 uint32_t pcfr; 235 uint32_t pgsr0; 236 uint32_t pgsr1; 237 uint32_t pgsr2; 238 uint32_t rcsr; 239 uint32_t pmfw; 240 }; 241 242 struct clocks_regs 243 { 244 uint32_t cccr; 245 uint32_t cken; 246 uint32_t oscc; 247 }; 248 249 dma_regs m_dma_regs; 250 i2s_regs m_i2s_regs; 251 rtc_regs m_rtc_regs; 252 ostmr_regs m_ostimer_regs; 253 intc_regs m_intc_regs; 254 gpio_regs m_gpio_regs; 255 lcd_regs m_lcd_regs; 256 power_regs m_power_regs; 257 clocks_regs m_clocks_regs; 258 259 devcb_write32 m_gpio0_w; 260 devcb_write32 m_gpio1_w; 261 devcb_write32 m_gpio2_w; 262 devcb_read32 m_gpio0_r; 263 devcb_read32 m_gpio1_r; 264 devcb_read32 m_gpio2_r; 265 266 required_device<cpu_device> m_maincpu; 267 required_device_array<dmadac_sound_device, 2> m_dmadac; 268 required_device<palette_device> m_palette; 269 270 std::unique_ptr<uint32_t[]> m_lcd_palette; // 0x100 271 std::unique_ptr<uint8_t[]> m_lcd_framebuffer; // 0x100000 272 std::unique_ptr<uint32_t[]> m_words; // 0x800 273 std::unique_ptr<int16_t[]> m_samples; // 0x1000 274 }; 275 276 DECLARE_DEVICE_TYPE(PXA255_PERIPHERALS, pxa255_periphs_device) 277 278 #endif // MAME_MACHINE_PXA255 279