1 // license:BSD-3-Clause
2 // copyright-holders:Manuel Abadia, Ernesto Corvi, Nicola Salmoria
3 /***************************************************************************
4
5 Galaga 3 / Gaplus (c) 1984 Namco
6
7 driver by Manuel Abadia, Ernesto Corvi, Nicola Salmoria
8
9
10 Custom ICs:
11 ----------
12 11XX gfx data shifter and mixer (16-bit in, 4-bit out) [1]
13 15XX sound control
14 16XX I/O control
15 CUS20 tilemap and sprite address generator
16 CUS21 sprite generator
17 CUS26 starfield generator
18 CUS29 sprite line buffer and sprite/tilemap mixer
19 CUS33 timing generator
20 CUS34 address decoder
21 56XX I/O
22 58XX I/O
23 CUS62 I/O and explosion generator
24 98XX lamp/coin output
25 99XX sound volume
26
27
28 memory map
29 ----------
30 Most of the address decoding for main and sound CPU is done by a custom IC (34XX),
31 so the memory map is largely deducted by program behaviour. The 34XX also handles
32 internally the main and sub irq, and a watchdog.
33 Most of the address decoding for sub CPU is done by a PAL which was read and
34 decoded, but there are some doubts about its validity.
35 There is also some additional decoding for tile/sprite RAM done by the 20XX
36 tilemap and sprite address generator.
37
38 Note: chip positions are based on the Midway version schematics. The Namco
39 version has a different layout (see later for the known correspondencies)
40
41 MAIN CPU:
42
43 Address Dir Data Name Description
44 ---------------- --- -------- --------- -----------------------
45 00000xxxxxxxxxxx R/W xxxxxxxx RAM 9J tilemap RAM (shared with sub CPU)
46 00001xxxxxxxxxxx R/W xxxxxxxx RAM 3M work RAM (shared with sub CPU)
47 000011111xxxxxxx R/W xxxxxxxx portion holding sprite registers (sprite number & color)
48 00010xxxxxxxxxxx R/W xxxxxxxx RAM 3K work RAM (shared with sub CPU)
49 000101111xxxxxxx R/W xxxxxxxx portion holding sprite registers (x, y)
50 00011xxxxxxxxxxx R/W xxxxxxxx RAM 3L work RAM (shared with sub CPU)
51 000111111xxxxxxx R/W xxxxxxxx portion holding sprite registers (x msb, flip, size)
52 01100-xxxxxxxxxx R/W xxxxxxxx SOUND RAM (shared with sound CPU)
53 01101-----xxxxxx R/W ----xxxx FBIT I/O chips
54 0111x----------- W -------- main CPU irq enable (data is in A11) (MIRQ generated by 34XX)
55 01111----------- R -------- watchdog reset (MRESET generated by 34XX)
56 1000x----------- W -------- SRESET reset sub and sound CPU, sound enable (data is in A11) (latch in 34XX)
57 1001x----------- W -------- FRESET reset I/O chips (data is in A11) (latch in 34XX)
58 10100---------xx W xxxxxxxx STWR to custom 26XX (starfield control)
59 10-xxxxxxxxxxxxx R xxxxxxxx ROM 9E program ROM (can optionally be a 27128)
60 110xxxxxxxxxxxxx R xxxxxxxx ROM 9D program ROM
61 111xxxxxxxxxxxxx R xxxxxxxx ROM 9C program ROM
62
63 [1] Program uses addresses with A10 = 1, e.g. 7400, 7c00, but A10 is not used.
64 On startup, it also writes to 7820-782f. This might be a bug, the intended range
65 being 6820-682f to address the 3rd I/O chip.
66
67
68 SOUND CPU:
69
70 Address Dir Data Name Description
71 ---------------- --- -------- --------- -----------------------
72 000---xxxxxxxxxx R/W xxxxxxxx SOUND2 RAM (shared with main CPU)
73 001------------- R/W -------- watchdog reset? (34XX) [1]
74 01x------------- W -------- sound CPU irq enable (data is in A13) (SIRQ generated by 34XX)
75 11-xxxxxxxxxxxxx R xxxxxxxx ROM 7B program ROM (can optionally be a 27128)
76
77 [1] Program writes to 3000 and on startup reads from 3000.
78 On startup it also writes to 2007, but there doesn't seem to be anything else there.
79
80
81 SUB CPU:
82
83 Address Dir Data Name Description
84 ---------------- --- -------- --------- -----------------------
85 00000xxxxxxxxxxx R/W xxxxxxxx RAM 9J tilemap RAM (shared with main CPU)
86 00001xxxxxxxxxxx R/W xxxxxxxx RAM 3M work RAM (shared with main CPU)
87 000011111xxxxxxx R/W xxxxxxxx portion holding sprite registers (sprite number & color)
88 00010xxxxxxxxxxx R/W xxxxxxxx RAM 3K work RAM (shared with main CPU)
89 000101111xxxxxxx R/W xxxxxxxx portion holding sprite registers (x, y)
90 00011xxxxxxxxxxx R/W xxxxxxxx RAM 3L work RAM (shared with main CPU)
91 000111111xxxxxxx R/W xxxxxxxx portion holding sprite registers (x msb, flip, size)
92 0110-----------x -------- VINTON sub CPU irq enable (data is in A0) [1]
93 10-xxxxxxxxxxxxx R xxxxxxxx ROM 6L program ROM (can optionally be a 27128)
94 110xxxxxxxxxxxxx R xxxxxxxx ROM 6M program ROM
95 111xxxxxxxxxxxxx R xxxxxxxx ROM 6N program ROM
96
97 [1] Program normally uses 6080/6081, but 6001 is written on startup.
98 500F is also written on startup, whose meaning is unknown.
99
100
101 ROM chip placements
102 -------------------
103 Midway Namco
104 ------ -----
105 9C 8B
106 9D 8C
107 9E 8D
108 6N 11B
109 6M 11C
110 6L 11D
111 7B 4B
112 9L 8S
113 5K 11R
114 5L 11N
115 5M 11P
116 5N 11M
117
118 ----------------------------------------------------------------------------
119
120
121 Notes:
122 ------
123 - Easter egg:
124 - enter service mode
125 - keep P1 start and P1 button pressed
126 - move joystick left until sound reaches 19
127 (c) 1984 NAMCO will appear on the screen
128
129 - most sets always say "I/O OK", even if the custom I/O checks fail. Only
130 gaplus and gaplusd stop working; these two also don't do the usual
131 Namco-trademark RAM test on startup, and use the first I/O chip in "coin" mode,
132 while the others use it in "switch/lamp" mode.
133
134 - gaplusd has the 58XX and 56XX inverted. Why would they do that?
135
136 - To use Round Advance: turn the dip switch on before the start of a level. Push
137 joystick up to pick a later level, then set the dip switch back to off.
138
139 - The only difference between galaga3b and galaga3m is the bonus life settings.
140
141 TODO:
142 - The starfield is wrong.
143
144 - schematics show 4 lines going from the 58XX I/O chip to the 26XX (starfield generator).
145 Function and operation unknown.
146
147 - Complete 62XX custom emulation (machine/namco62.cpp) (though it's quite different from 56XX and 58XX).
148
149 - Is the sprite generator the same as Phozon? This isn't clear yet. They are
150 very similar, especially in the way the size flags are layed out.
151
152 ***************************************************************************/
153
154 #include "emu.h"
155 #include "includes/gaplus.h"
156
157 #include "cpu/m6809/m6809.h"
158 #include "machine/namco62.h"
159 #include "machine/watchdog.h"
160 #include "sound/samples.h"
161 #include "speaker.h"
162
163
irq_1_ctrl_w(offs_t offset,uint8_t data)164 void gaplus_base_state::irq_1_ctrl_w(offs_t offset, uint8_t data)
165 {
166 int bit = !BIT(offset, 11);
167 m_main_irq_mask = bit & 1;
168 if (!bit)
169 m_maincpu->set_input_line(0, CLEAR_LINE);
170 }
171
irq_2_ctrl_w(offs_t offset,uint8_t data)172 void gaplus_base_state::irq_2_ctrl_w(offs_t offset, uint8_t data)
173 {
174 int bit = offset & 1;
175 m_sub_irq_mask = bit & 1;
176 if (!bit)
177 m_subcpu->set_input_line(0, CLEAR_LINE);
178 }
179
irq_3_ctrl_w(offs_t offset,uint8_t data)180 void gaplus_base_state::irq_3_ctrl_w(offs_t offset, uint8_t data)
181 {
182 int bit = !BIT(offset, 13);
183 m_sub2_irq_mask = bit & 1;
184 if (!bit)
185 m_subcpu2->set_input_line(0, CLEAR_LINE);
186 }
187
sreset_w(offs_t offset,uint8_t data)188 void gaplus_base_state::sreset_w(offs_t offset, uint8_t data)
189 {
190 int bit = !BIT(offset, 11);
191 m_subcpu->set_input_line(INPUT_LINE_RESET, bit ? CLEAR_LINE : ASSERT_LINE);
192 m_subcpu2->set_input_line(INPUT_LINE_RESET, bit ? CLEAR_LINE : ASSERT_LINE);
193 m_namco_15xx->sound_enable_w(bit);
194 }
195
freset_w(offs_t offset,uint8_t data)196 void gaplus_base_state::freset_w(offs_t offset, uint8_t data)
197 {
198 int bit = !BIT(offset, 11);
199
200 logerror("%04x: freset %d\n",m_maincpu->pc(), bit);
201
202 m_namco58xx->set_reset_line(bit ? CLEAR_LINE : ASSERT_LINE);
203 m_namco56xx->set_reset_line(bit ? CLEAR_LINE : ASSERT_LINE);
204 }
205
machine_reset()206 void gaplus_base_state::machine_reset()
207 {
208 /* on reset, VINTON is reset, while the other flags don't seem to be affected */
209 m_sub_irq_mask = 0;
210 m_subcpu->set_input_line(0, CLEAR_LINE);
211 }
212
device_timer(emu_timer & timer,device_timer_id id,int param,void * ptr)213 void gaplus_base_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
214 {
215 switch (id)
216 {
217 case TIMER_NAMCOIO0_RUN:
218 namcoio0_run(ptr, param);
219 break;
220 case TIMER_NAMCOIO1_RUN:
221 namcoio1_run(ptr, param);
222 break;
223 default:
224 throw emu_fatalerror("Unknown id in gaplus_base_state::device_timer");
225 }
226 }
227
TIMER_CALLBACK_MEMBER(gaplus_base_state::namcoio0_run)228 TIMER_CALLBACK_MEMBER(gaplus_base_state::namcoio0_run)
229 {
230 m_namco58xx->customio_run();
231 }
232
TIMER_CALLBACK_MEMBER(gaplus_base_state::namcoio1_run)233 TIMER_CALLBACK_MEMBER(gaplus_base_state::namcoio1_run)
234 {
235 m_namco56xx->customio_run();
236 }
237
WRITE_LINE_MEMBER(gaplus_base_state::vblank_irq)238 WRITE_LINE_MEMBER(gaplus_base_state::vblank_irq)
239 {
240 if (!state)
241 return;
242
243 if (m_main_irq_mask)
244 m_maincpu->set_input_line(0, ASSERT_LINE);
245
246 if (!m_namco58xx->read_reset_line()) /* give the cpu a tiny bit of time to write the command before processing it */
247 m_namcoio0_run_timer->adjust(attotime::from_usec(50));
248
249 if (!m_namco56xx->read_reset_line()) /* give the cpu a tiny bit of time to write the command before processing it */
250 m_namcoio1_run_timer->adjust(attotime::from_usec(50));
251
252 if (m_sub_irq_mask)
253 m_subcpu->set_input_line(0, ASSERT_LINE);
254
255 if (m_sub2_irq_mask)
256 m_subcpu2->set_input_line(0, ASSERT_LINE);
257 }
258
WRITE_LINE_MEMBER(gapluso_state::vblank_irq)259 WRITE_LINE_MEMBER(gapluso_state::vblank_irq)
260 {
261 if (!state)
262 return;
263
264 if (m_main_irq_mask)
265 m_maincpu->set_input_line(0, ASSERT_LINE);
266
267 if (!m_namco58xx->read_reset_line()) /* give the cpu a tiny bit of time to write the command before processing it */
268 m_namcoio1_run_timer->adjust(attotime::from_usec(50));
269
270 if (!m_namco56xx->read_reset_line()) /* give the cpu a tiny bit of time to write the command before processing it */
271 m_namcoio0_run_timer->adjust(attotime::from_usec(50));
272
273 if (m_sub_irq_mask)
274 m_subcpu->set_input_line(0, ASSERT_LINE);
275
276 if (m_sub2_irq_mask)
277 m_subcpu2->set_input_line(0, ASSERT_LINE);
278 }
279
280
cpu1_map(address_map & map)281 void gaplus_base_state::cpu1_map(address_map &map)
282 {
283 map(0x0000, 0x07ff).ram().w(FUNC(gaplus_base_state::videoram_w)).share("videoram"); /* tilemap RAM (shared with CPU #2) */
284 map(0x0800, 0x1fff).ram().share("spriteram"); /* shared RAM with CPU #2 (includes sprite RAM) */
285 map(0x6000, 0x63ff).rw(m_namco_15xx, FUNC(namco_15xx_device::sharedram_r), FUNC(namco_15xx_device::sharedram_w)); /* shared RAM with CPU #3 */
286 map(0x6800, 0x680f).rw("namcoio_1", FUNC(namcoio_device::read), FUNC(namcoio_device::write)); /* custom I/O chips interface */
287 map(0x6810, 0x681f).rw("namcoio_2", FUNC(namcoio_device::read), FUNC(namcoio_device::write)); /* custom I/O chips interface */
288 map(0x6820, 0x682f).rw(FUNC(gaplus_base_state::customio_3_r), FUNC(gaplus_base_state::customio_3_w)).share("customio_3"); /* custom I/O chip #3 interface */
289 map(0x7000, 0x7fff).w(FUNC(gaplus_base_state::irq_1_ctrl_w)); /* main CPU irq control */
290 map(0x7800, 0x7fff).r("watchdog", FUNC(watchdog_timer_device::reset_r));
291 map(0x8000, 0x8fff).w(FUNC(gaplus_base_state::sreset_w)); /* reset CPU #2 & #3, enable sound */
292 map(0x9000, 0x9fff).w(FUNC(gaplus_base_state::freset_w)); /* reset I/O chips */
293 map(0xa000, 0xa7ff).w(FUNC(gaplus_base_state::starfield_control_w)); /* starfield control */
294 map(0xa000, 0xffff).rom(); /* ROM */
295 }
296
cpu2_map(address_map & map)297 void gaplus_base_state::cpu2_map(address_map &map)
298 {
299 map(0x0000, 0x07ff).ram().w(FUNC(gaplus_base_state::videoram_w)).share("videoram"); /* tilemap RAM (shared with CPU #1) */
300 map(0x0800, 0x1fff).ram().share("spriteram"); /* shared RAM with CPU #1 */
301 // map(0x500f, 0x500f).nopw(); /* ??? written 256 times on startup */
302 map(0x6000, 0x6fff).w(FUNC(gaplus_base_state::irq_2_ctrl_w)); /* IRQ 2 control */
303 map(0xa000, 0xffff).rom(); /* ROM */
304 }
305
cpu3_map(address_map & map)306 void gaplus_base_state::cpu3_map(address_map &map)
307 {
308 map(0x0000, 0x03ff).rw(m_namco_15xx, FUNC(namco_15xx_device::sharedram_r), FUNC(namco_15xx_device::sharedram_w)); /* shared RAM with the main CPU + sound registers */
309 map(0x2000, 0x3fff).rw("watchdog", FUNC(watchdog_timer_device::reset_r), FUNC(watchdog_timer_device::reset_w)); /* watchdog? */
310 map(0x4000, 0x7fff).w(FUNC(gaplus_base_state::irq_3_ctrl_w)); /* interrupt enable/disable */
311 map(0xe000, 0xffff).rom(); /* ROM */
312 }
313
314 static INPUT_PORTS_START( gaplus )
315 /* The inputs are not memory mapped, they are handled by three I/O chips. */
316 PORT_START("P1") /* 56XX #0 pins 22-29 */
317 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
318 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
319 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
320 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
321
322 PORT_START("P2") /* 56XX #0 pins 22-29 */
323 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
324 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
325 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
326 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
327
328 PORT_START("BUTTONS") /* 56XX #0 pins 30-33 and 38-41 */
329 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
330 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
331 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
332 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
333
334 PORT_START("COINS") /* 56XX #0 pins 30-33 and 38-41 */
335 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
336 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
337 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
338 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE1 )
339
340 PORT_START("DSWA_LOW") /* 58XX #1 pins 30-33 and 38-41 */
341 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:7,8")
342 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
343 PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
344 PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
345 PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
346 PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW1:6" ) /* Listed as "Unused" */
347 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW1:5")
348 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
349 PORT_DIPSETTING( 0x08, DEF_STR( On ) )
350
351 PORT_START("DSWA_HIGH") /* 58XX #1 pins 30-33 and 38-41 */
352 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:3,4")
353 PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
354 PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
355 PORT_DIPSETTING( 0x03, DEF_STR( 1C_1C ) )
356 PORT_DIPSETTING( 0x02, DEF_STR( 1C_2C ) )
357 PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) ) PORT_DIPLOCATION("SW1:1,2")
358 PORT_DIPSETTING( 0x08, "2" )
359 PORT_DIPSETTING( 0x0c, "3" )
360 PORT_DIPSETTING( 0x04, "4" )
361 PORT_DIPSETTING( 0x00, "5" )
362
363 PORT_START("DSWB_LOW") /* 58XX #1 pins 22-29 */
364 PORT_DIPNAME( 0x08, 0x08, "Round Advance" ) PORT_DIPLOCATION("SW2:5")
365 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
366 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
367 PORT_DIPNAME( 0x07, 0x07, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:6,7,8")
368 PORT_DIPSETTING( 0x00, "30k 70k and every 70k" )
369 PORT_DIPSETTING( 0x01, "30k 100k and every 100k" )
370 PORT_DIPSETTING( 0x02, "30k 100k and every 200k" )
371 PORT_DIPSETTING( 0x03, "50k 100k and every 100k" )
372 PORT_DIPSETTING( 0x04, "50k 100k and every 200k" )
373 PORT_DIPSETTING( 0x07, "50k 150k and every 150k" )
374 PORT_DIPSETTING( 0x05, "50k 150k and every 300k" )
375 PORT_DIPSETTING( 0x06, "50k 150k" )
376
377 PORT_START("DSWB_HIGH") /* 58XX #1 pins 22-29 */
378 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW2:1")
379 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
380 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
381 PORT_DIPNAME( 0x07, 0x07, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:2,3,4")
382 PORT_DIPSETTING( 0x07, "0 - Standard" )
383 PORT_DIPSETTING( 0x06, "1 - Easiest" )
384 PORT_DIPSETTING( 0x05, "2" )
385 PORT_DIPSETTING( 0x04, "3" )
386 PORT_DIPSETTING( 0x03, "4" )
387 PORT_DIPSETTING( 0x02, "5" )
388 PORT_DIPSETTING( 0x01, "6" )
389 PORT_DIPSETTING( 0x00, "7 - Hardest" )
390
391 PORT_START("IN2") /* 62XX #2 pins 24-27 */
392 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
393 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
394 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Cabinet ) )
395 PORT_DIPSETTING( 0x04, DEF_STR( Upright ) )
396 PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
397 PORT_SERVICE( 0x08, IP_ACTIVE_LOW )
398 INPUT_PORTS_END
399
400 /* identical to gaplus, but service mode is a dip switch instead of coming from edge connector */
401 static INPUT_PORTS_START( gapluso )
402 PORT_INCLUDE( gaplus )
403
404 PORT_MODIFY("DSWB_HIGH")
405 PORT_SERVICE_DIPLOC( 0x08, IP_ACTIVE_LOW, "SW2:1" )
406
407 PORT_MODIFY("IN2")
408 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) // doesn't seem to be used
409 INPUT_PORTS_END
410
411 /* identical to gaplus, but different bonus life settings */
412 static INPUT_PORTS_START( galaga3a )
413 PORT_INCLUDE( gaplus )
414
415 PORT_MODIFY("DSWB_LOW")
416 PORT_DIPNAME( 0x07, 0x02, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:6,7,8")
417 PORT_DIPSETTING( 0x02, "30k 80k and every 100k" )
418 PORT_DIPSETTING( 0x03, "30k 100k and every 100k" )
419 PORT_DIPSETTING( 0x04, "30k 100k and every 150k" )
420 PORT_DIPSETTING( 0x07, "30k 100k and every 200k" )
421 PORT_DIPSETTING( 0x05, "30k 100k and every 300k" )
422 PORT_DIPSETTING( 0x06, "30k 150k" )
423 PORT_DIPSETTING( 0x00, "50k 150k and every 150k" )
424 PORT_DIPSETTING( 0x01, "50k 150k and every 200k" )
425 INPUT_PORTS_END
426
427 /* identical to gaplus, but different bonus life settings */
428 static INPUT_PORTS_START( galaga3m )
429 PORT_INCLUDE( gaplus )
430
431 PORT_MODIFY("DSWB_LOW")
432 PORT_DIPNAME( 0x07, 0x00, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:6,7,8")
433 PORT_DIPSETTING( 0x00, "30k 150k and every 600k" )
434 PORT_DIPSETTING( 0x01, "50k 150k and every 300k" )
435 PORT_DIPSETTING( 0x02, "50k 150k and every 600k" )
436 PORT_DIPSETTING( 0x03, "50k 200k and every 300k" )
437 PORT_DIPSETTING( 0x04, "100k 300k and every 300k" )
438 PORT_DIPSETTING( 0x07, "100k 300k and every 600k" )
439 PORT_DIPSETTING( 0x05, "150k 400k and every 900k" )
440 PORT_DIPSETTING( 0x06, "150k 400k" )
441 INPUT_PORTS_END
442
443
444
445 static const gfx_layout charlayout =
446 {
447 8,8,
448 RGN_FRAC(1,1),
449 2,
450 { 4, 6 },
451 { 16*8, 16*8+1, 24*8, 24*8+1, 0, 1, 8*8, 8*8+1 },
452 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
453 32*8
454 };
455
456 static const gfx_layout spritelayout =
457 {
458 16,16,
459 RGN_FRAC(1,2),
460 3,
461 { RGN_FRAC(1,2), 0, 4 },
462 { 0, 1, 2, 3, 8*8, 8*8+1, 8*8+2, 8*8+3,
463 16*8+0, 16*8+1, 16*8+2, 16*8+3, 24*8+0, 24*8+1, 24*8+2, 24*8+3 },
464 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
465 32*8, 33*8, 34*8, 35*8, 36*8, 37*8, 38*8, 39*8 },
466 64*8
467 };
468
469 static GFXDECODE_START( gfx_gaplus )
470 GFXDECODE_ENTRY( "gfx1", 0x0000, charlayout, 0, 64 )
471 GFXDECODE_ENTRY( "gfx2", 0x0000, spritelayout, 64*4, 64 )
472 GFXDECODE_END
473
474 static const char *const gaplus_sample_names[] =
475 {
476 "*gaplus",
477 "bang",
478 nullptr
479 };
480
481 /***************************************************************************
482
483 Custom I/O initialization
484
485 ***************************************************************************/
486
out_lamps0(uint8_t data)487 void gaplus_state::out_lamps0(uint8_t data)
488 {
489 m_lamps[0] = BIT(data, 0);
490 m_lamps[1] = BIT(data, 1);
491 machine().bookkeeping().coin_lockout_global_w(data & 4);
492 machine().bookkeeping().coin_counter_w(0, ~data & 8);
493 }
494
out_lamps1(uint8_t data)495 void gaplus_state::out_lamps1(uint8_t data)
496 {
497 machine().bookkeeping().coin_counter_w(1, ~data & 1);
498 }
499
machine_start()500 void gaplus_base_state::machine_start()
501 {
502 m_namcoio0_run_timer = timer_alloc(TIMER_NAMCOIO0_RUN);
503 m_namcoio1_run_timer = timer_alloc(TIMER_NAMCOIO1_RUN);
504
505 save_item(NAME(m_main_irq_mask));
506 save_item(NAME(m_sub_irq_mask));
507 save_item(NAME(m_sub2_irq_mask));
508 }
509
machine_start()510 void gaplus_state::machine_start()
511 {
512 gaplus_base_state::machine_start();
513
514 m_lamps.resolve();
515 }
516
gaplus_base(machine_config & config)517 void gaplus_base_state::gaplus_base(machine_config &config)
518 {
519 /* basic machine hardware */
520 MC6809E(config, m_maincpu, XTAL(24'576'000) / 16); /* 1.536 MHz */
521 m_maincpu->set_addrmap(AS_PROGRAM, &gaplus_base_state::cpu1_map);
522
523 MC6809E(config, m_subcpu, XTAL(24'576'000) / 16); /* 1.536 MHz */
524 m_subcpu->set_addrmap(AS_PROGRAM, &gaplus_base_state::cpu2_map);
525
526 MC6809E(config, m_subcpu2, XTAL(24'576'000) / 16); /* 1.536 MHz */
527 m_subcpu2->set_addrmap(AS_PROGRAM, &gaplus_base_state::cpu3_map);
528
529 config.set_maximum_quantum(attotime::from_hz(6000)); /* a high value to ensure proper synchronization of the CPUs */
530
531 WATCHDOG_TIMER(config, "watchdog");
532
533 NAMCO_62XX(config, "62xx", 24576000 / 6 / 2); /* totally made up - TODO: fix */
534 //n62xx.input_callback<0>().set_ioport("IN0L");
535 //n62xx.input_callback<1>().set_ioport("IN0H");
536 //n62xx.input_callback<2>().set_ioport("IN1L");
537 //n62xx.input_callback<3>().set_ioport("IN1H");
538 //n62xx.output_callback<0>().set(FUNC(gaplus_base_state::out_0));
539 //n62xx.output_callback<1>().set(FUNC(gaplus_base_state::out_1));
540
541 /* video hardware */
542 SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
543 m_screen->set_refresh_hz(60.606060);
544 m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
545 m_screen->set_size(36 * 8, 28 * 8);
546 m_screen->set_visarea(0 * 8, 36 * 8 - 1, 0 * 8, 28 * 8 - 1);
547 m_screen->set_screen_update(FUNC(gaplus_base_state::screen_update));
548 m_screen->screen_vblank().set(FUNC(gaplus_base_state::screen_vblank));
549 m_screen->screen_vblank().append(FUNC(gaplus_base_state::vblank_irq));
550 m_screen->set_palette(m_palette);
551
552 GFXDECODE(config, m_gfxdecode, m_palette, gfx_gaplus);
553 PALETTE(config, m_palette, FUNC(gaplus_base_state::gaplus_palette), 64 * 4 + 64 * 8, 256);
554
555 /* sound hardware */
556 SPEAKER(config, "mono").front_center();
557
558 NAMCO_15XX(config, m_namco_15xx, XTAL(24'576'000) / 1024);
559 m_namco_15xx->set_voices(8);
560 m_namco_15xx->add_route(ALL_OUTPUTS, "mono", 1.0);
561
562 SAMPLES(config, m_samples);
563 m_samples->set_channels(1);
564 m_samples->set_samples_names(gaplus_sample_names);
565 m_samples->add_route(ALL_OUTPUTS, "mono", 0.80);
566 }
567
gaplus(machine_config & config)568 void gaplus_state::gaplus(machine_config &config)
569 {
570 gaplus_base(config);
571
572 NAMCO_56XX(config, m_namco56xx, 0);
573 m_namco56xx->in_callback<0>().set_ioport("COINS");
574 m_namco56xx->in_callback<1>().set_ioport("P1");
575 m_namco56xx->in_callback<2>().set_ioport("P2");
576 m_namco56xx->in_callback<3>().set_ioport("BUTTONS");
577 m_namco56xx->out_callback<0>().set(FUNC(gaplus_state::out_lamps0));
578 m_namco56xx->out_callback<1>().set(FUNC(gaplus_state::out_lamps1));
579
580 NAMCO_58XX(config, m_namco58xx, 0);
581 m_namco58xx->in_callback<0>().set_ioport("DSWA_HIGH");
582 m_namco58xx->in_callback<1>().set_ioport("DSWB_LOW");
583 m_namco58xx->in_callback<2>().set_ioport("DSWB_HIGH");
584 m_namco58xx->in_callback<3>().set_ioport("DSWA_LOW");
585 }
586
gaplusd(machine_config & config)587 void gaplusd_state::gaplusd(machine_config &config)
588 {
589 gaplus_base(config);
590
591 NAMCO_58XX(config, m_namco58xx, 0);
592 m_namco58xx->in_callback<0>().set_ioport("COINS");
593 m_namco58xx->in_callback<1>().set_ioport("P1");
594 m_namco58xx->in_callback<2>().set_ioport("P2");
595 m_namco58xx->in_callback<3>().set_ioport("BUTTONS");
596
597 NAMCO_56XX(config, m_namco56xx, 0);
598 m_namco56xx->in_callback<0>().set_ioport("DSWA_HIGH");
599 m_namco56xx->in_callback<1>().set_ioport("DSWB_LOW");
600 m_namco56xx->in_callback<2>().set_ioport("DSWB_HIGH");
601 m_namco56xx->in_callback<3>().set_ioport("DSWA_LOW");
602 }
603
gapluso(machine_config & config)604 void gapluso_state::gapluso(machine_config &config)
605 {
606 gaplus_base(config);
607
608 /* basic machine hardware */
609 m_screen->screen_vblank().set(FUNC(gaplus_base_state::screen_vblank));
610 m_screen->screen_vblank().append(FUNC(gapluso_state::vblank_irq));
611
612 NAMCO_56XX(config, m_namco56xx, 0);
613 m_namco56xx->in_callback<0>().set_ioport("COINS");
614 m_namco56xx->in_callback<1>().set_ioport("P1");
615 m_namco56xx->in_callback<2>().set_ioport("P2");
616 m_namco56xx->in_callback<3>().set_ioport("BUTTONS");
617
618 NAMCO_58XX(config, m_namco58xx, 0);
619 m_namco58xx->in_callback<0>().set_ioport("DSWA_HIGH");
620 m_namco58xx->in_callback<1>().set_ioport("DSWB_LOW");
621 m_namco58xx->in_callback<2>().set_ioport("DSWB_HIGH");
622 m_namco58xx->in_callback<3>().set_ioport("DSWA_LOW");
623 }
624
625
626
627 ROM_START( gaplus ) /* Version 2 or 3 PCB */
628 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
CRC(e525d75d)629 ROM_LOAD( "gp2-4.8d", 0xa000, 0x2000, CRC(e525d75d) SHA1(93fcd8b940491abf6344181811d0b35765d7e45c) )
630 ROM_LOAD( "gp2-3b.8c", 0xc000, 0x2000, CRC(d77840a4) SHA1(81402b28a2d5ac2d1301252534afa0cb65d7e162) )
631 ROM_LOAD( "gp2-2b.8b", 0xe000, 0x2000, CRC(b3cb90db) SHA1(025c2f3978772e1ecbbf36842dc7c2203ee91a1f) )
632
633 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
634 ROM_LOAD( "gp2-8.11d", 0xa000, 0x2000, CRC(42b9fd7c) SHA1(f230eb0ad757f0714c0ac81c812e950778452947) )
635 ROM_LOAD( "gp2-7.11c", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
636 ROM_LOAD( "gp2-6.11b", 0xe000, 0x2000, CRC(75b18652) SHA1(398059da967c80321a9ec94d982a6c0b3c970c5f) )
637
638 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
639 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
640
641 ROM_REGION( 0x4000, "gfx1", 0 )
642 ROM_LOAD( "gp2-5.8s", 0x0000, 0x2000, CRC(f3d19987) SHA1(a0107fa4659597ac42c875ab1c0deb845534268b) ) /* characters */
643 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
644
645 ROM_REGION( 0xc000, "gfx2", 0 )
646 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
647 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
648 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
649 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
650 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
651 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
652
653 ROM_REGION( 0x0800, "proms", 0 )
654 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
655 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
656 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
657 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
658 ROM_LOAD( "gp2-6.6p", 0x0400, 0x0200, CRC(6f99c2da) SHA1(955dcef363870ee8e91edc73b9ea3ce489738aad) ) /* sprite color ROM (lower 4 bits) */
659 ROM_LOAD( "gp2-5.6n", 0x0600, 0x0200, CRC(c7d31657) SHA1(a93a5bc448dc127e1389d10a9cb06acadfe940cf) ) /* sprite color ROM (upper 4 bits) */
660
661 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
662 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
663
664 ROM_REGION( 0x0100, "plds", 0 )
665 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
666 ROM_END
667
668 ROM_START( gaplusa ) /* Version 2 or 3 PCB */
669 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
670 ROM_LOAD( "gp2-4.8d", 0xa000, 0x2000, CRC(e525d75d) SHA1(93fcd8b940491abf6344181811d0b35765d7e45c) )
671 ROM_LOAD( "gp2-3b.8c", 0xc000, 0x2000, CRC(d77840a4) SHA1(81402b28a2d5ac2d1301252534afa0cb65d7e162) )
672 ROM_LOAD( "gp2-2.8b", 0xe000, 0x2000, CRC(61f6cc65) SHA1(0f9b30722ba03a63c70ff9f1bd9712aa1a4a6a3d) )
673
674 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
675 ROM_LOAD( "gp2-8.11d", 0xa000, 0x2000, CRC(42b9fd7c) SHA1(f230eb0ad757f0714c0ac81c812e950778452947) )
676 ROM_LOAD( "gp2-7.11c", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
677 ROM_LOAD( "gp2-6.11b", 0xe000, 0x2000, CRC(75b18652) SHA1(398059da967c80321a9ec94d982a6c0b3c970c5f) )
678
679 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
680 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
681
682 ROM_REGION( 0x4000, "gfx1", 0 )
683 ROM_LOAD( "gp2-5.8s", 0x0000, 0x2000, CRC(f3d19987) SHA1(a0107fa4659597ac42c875ab1c0deb845534268b) ) /* characters */
684 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
685
686 ROM_REGION( 0xc000, "gfx2", 0 )
687 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
688 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
689 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
690 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
691 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
692 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
693
694 ROM_REGION( 0x0800, "proms", 0 )
695 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
696 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
697 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
698 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
699 ROM_LOAD( "gp2-6.6p", 0x0400, 0x0200, CRC(6f99c2da) SHA1(955dcef363870ee8e91edc73b9ea3ce489738aad) ) /* sprite color ROM (lower 4 bits) */
700 ROM_LOAD( "gp2-5.6n", 0x0600, 0x0200, CRC(c7d31657) SHA1(a93a5bc448dc127e1389d10a9cb06acadfe940cf) ) /* sprite color ROM (upper 4 bits) */
701
702 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
703 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
704
705 ROM_REGION( 0x0100, "plds", 0 )
706 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
707 ROM_END
708
709 ROM_START( gaplusd ) /* Alternate hardware */
710 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
711 ROM_LOAD( "gp2-4b.8d", 0xa000, 0x2000, CRC(484f11e0) SHA1(659756ae183dac3817440c8975f203c7dbe08c6b) )
712 ROM_LOAD( "gp2-3c.8c", 0xc000, 0x2000, CRC(a74b0266) SHA1(a534c6b4af569ed545bf52769c7d5ceb5f2c4935) )
713 ROM_LOAD( "gp2-2d.8b", 0xe000, 0x2000, CRC(69fdfdb7) SHA1(aec611336b8767897ad493d581d70b1f0e75aeba) )
714
715 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
716 ROM_LOAD( "gp2-8b.11d", 0xa000, 0x2000, CRC(bff601a6) SHA1(e1a04354d8d0bc0d51d7341a46bd23cbd2158ee9) ) /* Revised for alternate hardware */
717 ROM_LOAD( "gp2-7.11c", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
718 ROM_LOAD( "gp2-6b.11b", 0xe000, 0x2000, CRC(14cd61ea) SHA1(05605abebcf2791e60b2d810dafcdd8582a87d9b) ) /* Revised for alternate hardware */
719
720 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
721 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
722
723 ROM_REGION( 0x4000, "gfx1", 0 )
724 ROM_LOAD( "gp2-5.8s", 0x0000, 0x2000, CRC(f3d19987) SHA1(a0107fa4659597ac42c875ab1c0deb845534268b) ) /* characters */
725 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
726
727 ROM_REGION( 0xc000, "gfx2", 0 )
728 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
729 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
730 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
731 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
732 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
733 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
734
735 ROM_REGION( 0x0800, "proms", 0 )
736 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
737 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
738 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
739 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
740 ROM_LOAD( "gp2-6.6p", 0x0400, 0x0200, CRC(6f99c2da) SHA1(955dcef363870ee8e91edc73b9ea3ce489738aad) ) /* sprite color ROM (lower 4 bits) */
741 ROM_LOAD( "gp2-5.6n", 0x0600, 0x0200, CRC(c7d31657) SHA1(a93a5bc448dc127e1389d10a9cb06acadfe940cf) ) /* sprite color ROM (upper 4 bits) */
742
743 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
744 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
745
746 ROM_REGION( 0x0100, "plds", 0 )
747 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
748 ROM_END
749
750 ROM_START( gaplust ) /* Tecfri PCB */
751 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
752 ROM_LOAD( "gp2_4.4", 0xa000, 0x2000, CRC(d891a70d) SHA1(ec906d623f936335e194d3bf9484ca4e82691272) ) // galaga3m - m1.9e 99.865723%
753 ROM_LOAD( "gp2_3.3", 0xc000, 0x2000, CRC(1df6e319) SHA1(beb7bd22ff8bcb1c39f676e8bbb607e06e4f20d6) ) // galaga3m - m2.9d 6.762695%
754 ROM_LOAD( "gp2_2.2", 0xe000, 0x2000, CRC(fc764728) SHA1(5a8bd3e83fbea2bb6cc06748c85b56e24a706f37) ) // galaga3m - m3.9c 81.530762%
755
756 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
757 ROM_LOAD( "gp2_8.8", 0xa000, 0x2000, CRC(9ec3dce5) SHA1(196a975aff59be19f55041a44b201aafef083ba7) ) // matches roms from the Midway PCB sets
758 ROM_LOAD( "gp2_7.7", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
759 ROM_LOAD( "gp2_6.6", 0xe000, 0x2000, CRC(6a2942c5) SHA1(6fb2c4dcb2ad393220917b81f1a42e571d209d76) )
760
761 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
762 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
763
764 ROM_REGION( 0x4000, "gfx1", 0 )
765 ROM_LOAD( "gp2-5.8s", 0x0000, 0x2000, CRC(f3d19987) SHA1(a0107fa4659597ac42c875ab1c0deb845534268b) ) /* characters */
766 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
767
768 ROM_REGION( 0xc000, "gfx2", 0 )
769 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
770 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
771 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
772 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
773 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
774 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
775
776 ROM_REGION( 0x0800, "proms", 0 )
777 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
778 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
779 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
780 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
781 ROM_LOAD( "gp2-6.6p", 0x0400, 0x0200, CRC(6f99c2da) SHA1(955dcef363870ee8e91edc73b9ea3ce489738aad) ) /* sprite color ROM (lower 4 bits) */
782 ROM_LOAD( "gp2-5.6n", 0x0600, 0x0200, CRC(c7d31657) SHA1(a93a5bc448dc127e1389d10a9cb06acadfe940cf) ) /* sprite color ROM (upper 4 bits) */
783
784 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
785 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
786
787 ROM_REGION( 0x0100, "plds", 0 )
788 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
789 ROM_END
790
791 ROM_START( galaga3 ) /* Version 2 or 3 PCB */
792 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
793 ROM_LOAD( "gp3-4c.8d", 0xa000, 0x2000, CRC(10d7f64c) SHA1(e39f77af16016d28170e4ac1c2a784b0a7ec5454) )
794 ROM_LOAD( "gp3-3c.8c", 0xc000, 0x2000, CRC(962411e8) SHA1(2b6bb2a5d77a837810180391ef6c0ce745bfed64) )
795 ROM_LOAD( "gp3-2d.8b", 0xe000, 0x2000, CRC(ecc01bdb) SHA1(b176b46bd6f2501d3a74ed11186be8411fd1105b) )
796
797 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
798 ROM_LOAD( "gp3-8b.11d", 0xa000, 0x2000, CRC(f5e056d1) SHA1(bbed2056dc28dc2828e29987c16d89fb16e7059e) )
799 ROM_LOAD( "gp2-7.11c", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
800 ROM_LOAD( "gp3-6b.11b", 0xe000, 0x2000, CRC(026491b6) SHA1(a19f2942dafc899d686a42240fc2f7a7a7d3b1f5) )
801
802 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
803 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
804
805 ROM_REGION( 0x4000, "gfx1", 0 )
806 ROM_LOAD( "gp3-5.8s", 0x0000, 0x2000, CRC(8d4dcebf) SHA1(0a556b45976bc36eb99048b1512c446b472da1d2) ) /* characters */
807 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
808
809 ROM_REGION( 0xc000, "gfx2", 0 )
810 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
811 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
812 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
813 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
814 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
815 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
816
817 ROM_REGION( 0x0800, "proms", 0 )
818 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
819 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
820 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
821 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
822 ROM_LOAD( "gp3-6.6p", 0x0400, 0x0200, CRC(d48c0eef) SHA1(6d0512958bc522d22e69336677369507847f8f6f) ) /* sprite color ROM (lower 4 bits) */
823 ROM_LOAD( "gp3-5.6n", 0x0600, 0x0200, CRC(417ba0dc) SHA1(2ba51ccdd0428fc48758ed8fea36c8ce0e752a45) ) /* sprite color ROM (upper 4 bits) */
824
825 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
826 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
827
828 ROM_REGION( 0x0100, "plds", 0 )
829 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
830 ROM_END
831
832 ROM_START( galaga3a ) /* Version 2 or 3 PCB */
833 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
834 ROM_LOAD( "gp3-4c.8d", 0xa000, 0x2000, CRC(10d7f64c) SHA1(e39f77af16016d28170e4ac1c2a784b0a7ec5454) )
835 ROM_LOAD( "gp3-3c.8c", 0xc000, 0x2000, CRC(962411e8) SHA1(2b6bb2a5d77a837810180391ef6c0ce745bfed64) )
836 ROM_LOAD( "gp3-2c.8b", 0xe000, 0x2000, CRC(f72d6fc5) SHA1(7031c4a2c4374fb786fc563cbad3e3de0dbaa8d2) )
837
838 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
839 ROM_LOAD( "gp3-8b.11d", 0xa000, 0x2000, CRC(f5e056d1) SHA1(bbed2056dc28dc2828e29987c16d89fb16e7059e) )
840 ROM_LOAD( "gp2-7.11c", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
841 ROM_LOAD( "gp3-6b.11b", 0xe000, 0x2000, CRC(026491b6) SHA1(a19f2942dafc899d686a42240fc2f7a7a7d3b1f5) )
842
843 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
844 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
845
846 ROM_REGION( 0x4000, "gfx1", 0 )
847 ROM_LOAD( "gp3-5.8s", 0x0000, 0x2000, CRC(8d4dcebf) SHA1(0a556b45976bc36eb99048b1512c446b472da1d2) ) /* characters */
848 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
849
850 ROM_REGION( 0xc000, "gfx2", 0 )
851 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
852 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
853 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
854 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
855 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
856 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
857
858 ROM_REGION( 0x0800, "proms", 0 )
859 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
860 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
861 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
862 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
863 ROM_LOAD( "gp3-6.6p", 0x0400, 0x0200, CRC(d48c0eef) SHA1(6d0512958bc522d22e69336677369507847f8f6f) ) /* sprite color ROM (lower 4 bits) */
864 ROM_LOAD( "gp3-5.6n", 0x0600, 0x0200, CRC(417ba0dc) SHA1(2ba51ccdd0428fc48758ed8fea36c8ce0e752a45) ) /* sprite color ROM (upper 4 bits) */
865
866 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
867 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
868
869 ROM_REGION( 0x0100, "plds", 0 )
870 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
871 ROM_END
872
873 ROM_START( galaga3b ) /* Version 2 or 3 PCB */
874 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
875 ROM_LOAD( "gp3-4.8d", 0xa000, 0x2000, CRC(58de387c) SHA1(9a2519e345e2599bb9ea28b916cff95c03d7b262) )
876 ROM_LOAD( "gp3-3.8c", 0xc000, 0x2000, CRC(94a3fd4e) SHA1(e566b7a76fb8db849c3c1660a1551a7a94caddc2) )
877 ROM_LOAD( "gp3-2.8b", 0xe000, 0x2000, CRC(4b1cb589) SHA1(1f016341f8c73a2b379362be091f0a95ef81c2fa) )
878
879 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
880 ROM_LOAD( "gp3-8.11d", 0xa000, 0x2000, CRC(d390ef28) SHA1(fa3325ce7b8d29edea467678646ab0e4c1f6d1f8) )
881 ROM_LOAD( "gp2-7.11c", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
882 ROM_LOAD( "gp3-6.11b", 0xe000, 0x2000, CRC(b36a9a2b) SHA1(8d11252c23ca6e10c994a58aa4a48690255e2268) )
883
884 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
885 ROM_LOAD( "gp2-1.4b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
886
887 ROM_REGION( 0x4000, "gfx1", 0 )
888 ROM_LOAD( "gp3-5.8s", 0x0000, 0x2000, CRC(8d4dcebf) SHA1(0a556b45976bc36eb99048b1512c446b472da1d2) ) /* characters */
889 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
890
891 ROM_REGION( 0xc000, "gfx2", 0 )
892 ROM_LOAD( "gp2-11.11p", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
893 ROM_LOAD( "gp2-10.11n", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
894 ROM_LOAD( "gp2-12.11r", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
895 ROM_LOAD( "gp2-9.11m", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
896 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
897 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
898
899 ROM_REGION( 0x0800, "proms", 0 )
900 ROM_LOAD( "gp2-3.1p", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
901 ROM_LOAD( "gp2-1.1n", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
902 ROM_LOAD( "gp2-2.2n", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
903 ROM_LOAD( "gp2-7.6s", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
904 ROM_LOAD( "gp3-6.6p", 0x0400, 0x0200, CRC(d48c0eef) SHA1(6d0512958bc522d22e69336677369507847f8f6f) ) /* sprite color ROM (lower 4 bits) */
905 ROM_LOAD( "gp3-5.6n", 0x0600, 0x0200, CRC(417ba0dc) SHA1(2ba51ccdd0428fc48758ed8fea36c8ce0e752a45) ) /* sprite color ROM (upper 4 bits) */
906
907 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
908 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
909
910 ROM_REGION( 0x0100, "plds", 0 )
911 ROM_LOAD( "pal10l8.8n", 0x0000, 0x002c, CRC(08e5b2fe) SHA1(1aa7fa1a61795703af84ae427d0d8588ef8c4c3f) )
912 ROM_END
913
914
915 ROM_START( galaga3c ) /* Version (AKA Midway) 1 PCB */
916 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
917 ROM_LOAD( "gal3_9e.9e", 0xa000, 0x2000, CRC(f4845e7f) SHA1(7b1377254f594bea4a8ffc7e388d9106e0266b55) )
918 ROM_LOAD( "gal3_9d.9d", 0xc000, 0x2000, CRC(86fac687) SHA1(07f76af524dbb3e79de41ef4bf32e7380776d9f5) )
919 ROM_LOAD( "gal3_9c.9c", 0xe000, 0x2000, CRC(f1b00073) SHA1(5d998d938251f173cedf742b95d02cc0a2b9d3be) )
920
921 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
922 ROM_LOAD( "gal3_6l.6l", 0xa000, 0x2000, CRC(9ec3dce5) SHA1(196a975aff59be19f55041a44b201aafef083ba7) )
923 ROM_LOAD( "gal3_6m.6m", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
924 ROM_LOAD( "gal3_6n.6n", 0xe000, 0x2000, CRC(6a2942c5) SHA1(6fb2c4dcb2ad393220917b81f1a42e571d209d76) )
925
926 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
927 ROM_LOAD( "gp2-1.7b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
928
929 ROM_REGION( 0x4000, "gfx1", 0 )
930 ROM_LOAD( "gal3_9l.bin", 0x0000, 0x2000, CRC(8d4dcebf) SHA1(0a556b45976bc36eb99048b1512c446b472da1d2) ) /* characters */
931 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
932
933 ROM_REGION( 0xc000, "gfx2", 0 )
934 ROM_LOAD( "gp2-11.5m", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
935 ROM_LOAD( "gp2-10.5l", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
936 ROM_LOAD( "gp2-12.5k", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
937 ROM_LOAD( "gp2-9.5n", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
938 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
939 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
940
941 ROM_REGION( 0x0800, "proms", 0 )
942 ROM_LOAD( "gp2-3.1c", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
943 ROM_LOAD( "gp2-1.1d", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
944 ROM_LOAD( "gp2-2.2d", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
945 ROM_LOAD( "gp2-7.4f", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
946 ROM_LOAD( "g3_3f.3f", 0x0400, 0x0200, CRC(d48c0eef) SHA1(6d0512958bc522d22e69336677369507847f8f6f) ) /* sprite color ROM (lower 4 bits) */
947 ROM_LOAD( "g3_3e.3e", 0x0600, 0x0200, CRC(417ba0dc) SHA1(2ba51ccdd0428fc48758ed8fea36c8ce0e752a45) ) /* sprite color ROM (upper 4 bits) */
948
949 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
950 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
951 ROM_END
952
953 ROM_START( galaga3m ) /* Version (AKA Midway) 1 PCB */
954 ROM_REGION( 0x10000, "maincpu", 0 ) /* 64k for the MAIN CPU */
955 ROM_LOAD( "m1.9e", 0xa000, 0x2000, CRC(e392704e) SHA1(8eebd48dfe8491f491e844d4ad0964e25efb013b) )
956 ROM_LOAD( "m2.9d", 0xc000, 0x2000, CRC(86fac687) SHA1(07f76af524dbb3e79de41ef4bf32e7380776d9f5) )
957 ROM_LOAD( "m3.9c", 0xe000, 0x2000, CRC(f1b00073) SHA1(5d998d938251f173cedf742b95d02cc0a2b9d3be) )
958
959 ROM_REGION( 0x10000, "sub", 0 ) /* 64k for the SUB CPU */
960 ROM_LOAD( "m6.6l", 0xa000, 0x2000, CRC(9ec3dce5) SHA1(196a975aff59be19f55041a44b201aafef083ba7) )
961 ROM_LOAD( "m5.6m", 0xc000, 0x2000, CRC(0621f7df) SHA1(b86020f819fefb134cb57e203f7c90b1b29581c8) )
962 ROM_LOAD( "m4.6n", 0xe000, 0x2000, CRC(6a2942c5) SHA1(6fb2c4dcb2ad393220917b81f1a42e571d209d76) )
963
964 ROM_REGION( 0x10000, "sub2", 0 ) /* 64k for the SOUND CPU */
965 ROM_LOAD( "gp2-1.7b", 0xe000, 0x2000, CRC(ed8aa206) SHA1(4e0a31d84cb7aca497485dbe0240009d58275765) )
966
967 ROM_REGION( 0x4000, "gfx1", 0 )
968 ROM_LOAD( "gal3_9l.bin", 0x0000, 0x2000, CRC(8d4dcebf) SHA1(0a556b45976bc36eb99048b1512c446b472da1d2) ) /* characters */
969 /* 0x2000-0x3fff will be unpacked from 0x0000-0x1fff */
970
971 ROM_REGION( 0xc000, "gfx2", 0 )
972 ROM_LOAD( "gp2-11.5m", 0x0000, 0x2000, CRC(57740ff9) SHA1(16873e0ac5f975768d596d7d32af7571f4817f2b) ) /* objects */
973 ROM_LOAD( "gp2-10.5l", 0x2000, 0x2000, CRC(6cd8ce11) SHA1(fc346e98737c9fc20810e32d4c150ae4b4051979) ) /* objects */
974 ROM_LOAD( "gp2-12.5k", 0x4000, 0x2000, CRC(7316a1f1) SHA1(368e4541a5151e906a189712bc05192c2ceec8ae) ) /* objects */
975 ROM_LOAD( "gp2-9.5n", 0x6000, 0x2000, CRC(e6a9ae67) SHA1(99c1e67c3b216aa1b63f199e21c73cdedde80e1b) ) /* objects */
976 /* 0x8000-0x9fff will be unpacked from 0x6000-0x7fff */
977 ROM_FILL( 0xa000, 0x2000, 0x00 ) // optional ROM, not used
978
979 ROM_REGION( 0x0800, "proms", 0 )
980 ROM_LOAD( "gp2-3.1c", 0x0000, 0x0100, CRC(a5091352) SHA1(dcd6dfbfbd5281ba0c7b7c189d6fde23617ed3e3) ) /* red palette ROM (4 bits) */
981 ROM_LOAD( "gp2-1.1d", 0x0100, 0x0100, CRC(8bc8022a) SHA1(c76f9d9b066e268621d41a703c5280261234709a) ) /* green palette ROM (4 bits) */
982 ROM_LOAD( "gp2-2.2d", 0x0200, 0x0100, CRC(8dabc20b) SHA1(64d7b333f529d3ba66aeefd380fd1cbf9ddf460d) ) /* blue palette ROM (4 bits) */
983 ROM_LOAD( "gp2-7.4f", 0x0300, 0x0100, CRC(2faa3e09) SHA1(781ffe9088476798409cb922350eff881590cf35) ) /* char color ROM */
984 ROM_LOAD( "g3_3f.3f", 0x0400, 0x0200, CRC(d48c0eef) SHA1(6d0512958bc522d22e69336677369507847f8f6f) ) /* sprite color ROM (lower 4 bits) */
985 ROM_LOAD( "g3_3e.3e", 0x0600, 0x0200, CRC(417ba0dc) SHA1(2ba51ccdd0428fc48758ed8fea36c8ce0e752a45) ) /* sprite color ROM (upper 4 bits) */
986
987 ROM_REGION( 0x0100, "namco", 0 ) /* sound prom */
988 ROM_LOAD( "gp2-4.3f", 0x0000, 0x0100, CRC(2d9fbdd8) SHA1(e6a23cd5ce3d3e76de3b70c8ab5a3c45b1147af4) )
989 ROM_END
990
991
992 void gaplus_base_state::driver_init()
993 {
994 uint8_t *rom = m_gfx1_region->base();
995 for (int i = 0;i < 0x2000;i++)
996 rom[i + 0x2000] = rom[i] >> 4;
997
998 rom = m_gfx2_region->base() + 0x6000;
999 for (int i = 0;i < 0x2000;i++)
1000 rom[i + 0x2000] = rom[i] << 4;
1001 }
1002
1003
1004 /* These sets are on revision 2 or 3 PCBs AKA "Namco" PCBs */
1005 GAME( 1984, gaplus, 0, gapluso, gapluso, gapluso_state, driver_init, ROT90, "Namco", "Gaplus (GP2 rev. B)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1006 GAME( 1984, gaplusa, gaplus, gapluso, gapluso, gapluso_state, driver_init, ROT90, "Namco", "Gaplus (GP2)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1007 GAME( 1984, gaplusd, gaplus, gaplusd, gapluso, gaplusd_state, driver_init, ROT90, "Namco", "Gaplus (GP2 rev D, alternate hardware)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1008 GAME( 1984, galaga3, gaplus, gaplus, gaplus, gaplus_state, driver_init, ROT90, "Namco", "Galaga 3 (GP3 rev. D)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1009 GAME( 1984, galaga3a, gaplus, gaplus, gaplus, gaplus_state, driver_init, ROT90, "Namco", "Galaga 3 (GP3 rev. C)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1010 GAME( 1984, galaga3b, gaplus, gaplus, gaplus, gaplus_state, driver_init, ROT90, "Namco", "Galaga 3 (GP3)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1011
1012 /* These sets are on older revision (AKA Midway) 1 PCBs */
1013 GAME( 1984, galaga3c, gaplus, gaplus, galaga3a, gaplus_state, driver_init, ROT90, "Namco", "Galaga 3 (set 4)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1014 GAME( 1984, galaga3m, gaplus, gaplus, galaga3m, gaplus_state, driver_init, ROT90, "Namco", "Galaga 3 (set 5)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1015
1016 /* This is an odd mix of Galaga3 and Gaplus, main code seems closest to galaga3m but still has significant changes, copyright is modified to 1992, has Galaga 3 style high scores, PARSEF spelling error on high score table */
1017 GAME( 1992, gaplust, gaplus, gaplus, galaga3m, gaplus_state, driver_init, ROT90, "bootleg (Tecfri)", "Gaplus (Tecfri PCB)", MACHINE_IMPERFECT_SOUND | MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
1018