1 // license:BSD-3-Clause 2 // copyright-holders:Lukasz Markowski 3 #ifndef MAME_INCLUDES_DM7000_H 4 #define MAME_INCLUDES_DM7000_H 5 6 #pragma once 7 8 #include "cpu/powerpc/ppc.h" 9 #include "machine/terminal.h" 10 11 12 class dm7000_state : public driver_device 13 { 14 public: dm7000_state(const machine_config & mconfig,device_type type,const char * tag)15 dm7000_state(const machine_config &mconfig, device_type type, const char *tag) 16 : driver_device(mconfig, type, tag) 17 , m_maincpu(*this, "maincpu") 18 , m_terminal(*this, "terminal") 19 { 20 } 21 22 void dm7000(machine_config &config); 23 24 private: 25 required_device<ppc4xx_device> m_maincpu; 26 required_device<generic_terminal_device> m_terminal; 27 28 void dm7000_iic0_w(offs_t offset, uint8_t data); 29 uint8_t dm7000_iic0_r(offs_t offset); 30 void dm7000_iic1_w(offs_t offset, uint8_t data); 31 uint8_t dm7000_iic1_r(offs_t offset); 32 33 void dm7000_scc0_w(offs_t offset, uint8_t data); 34 uint8_t dm7000_scc0_r(offs_t offset); 35 void kbd_put(u8 data); 36 uint8_t m_scc0_lcr; 37 uint8_t m_scc0_lsr; 38 uint8_t m_term_data; 39 40 41 void dm7000_gpio0_w(offs_t offset, uint8_t data); 42 uint8_t dm7000_gpio0_r(offs_t offset); 43 44 void dm7000_scp0_w(offs_t offset, uint8_t data); 45 uint8_t dm7000_scp0_r(offs_t offset); 46 47 void dm7000_enet_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); 48 uint16_t dm7000_enet_r(offs_t offset); 49 50 uint32_t dcr_r(offs_t offset); 51 void dcr_w(offs_t offset, uint32_t data); 52 53 54 uint16_t m_enet_regs[32]; 55 56 uint32_t dcr[1024]; 57 virtual void machine_reset() override; 58 virtual void video_start() override; 59 uint32_t screen_update_dm7000(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 60 void dm7000_mem(address_map &map); 61 }; 62 63 /* */ 64 #define UART_DLL 0 65 #define UART_RBR 0 66 #define UART_THR 0 67 #define UART_DLH 1 68 #define UART_IER 1 69 #define UART_IIR 2 70 #define UART_FCR 2 71 #define UART_LCR 3 72 #define UART_LCR_DLAB 0x80 73 #define UART_MCR 4 74 #define UART_LSR 5 75 #define UART_LSR_TEMT 0x20 76 #define UART_LSR_THRE 0x40 77 #define UART_MSR 6 78 #define UART_SCR 7 79 80 /* */ 81 #define SCP_SPMODE 0 82 #define SCP_RXDATA 1 83 #define SCP_TXDATA 2 84 #define SCP_SPCOM 3 85 #define SCP_STATUS 4 86 #define SCP_STATUS_RXRDY 1 87 #define SCP_CDM 6 88 89 /* STB045xxx DCRs */ 90 91 #define DCRSTB045_CICVCR 0x033 /* CIC Video Control Register */ 92 #define DCRSTB045_SCCR 0x120 /* Serial Clock Control Register */ 93 #define DCRSTB045_VIDEO_CNTL 0x140 /* Video Control Register */ 94 #define DCRSTB045_CMD_STAT 0x14a /* Command status */ 95 #define DCRSTB045_DISP_MODE 0x154 /* Display Mode Register */ 96 #define DCRSTB045_FRAME_BUFR_BASE 0x179 /* Frame Buffers Base Address Register */ 97 98 #endif // MAME_INCLUDES_DM7000_H 99