1 // license:BSD-3-Clause
2 // copyright-holders: Aaron Giles, Ted Green
3 // Galileo GT-64xxx System Controller
4 // Skeleton code based off seattle machine driver.
5 // TODO:
6 // Need PCI to be able to have a target delay (pci bus stall) a dma transfer
7 // Configurable byte swapping on cpu and pci busses.
8
9 #ifndef MAME_MACHINE_GT64XXX_H
10 #define MAME_MACHINE_GT64XXX_H
11
12 #include "pci.h"
13 #include "cpu/mips/mips3.h"
14
DECLARE_DEVICE_TYPE(GT64010,gt64010_device)15 DECLARE_DEVICE_TYPE(GT64010, gt64010_device)
16 DECLARE_DEVICE_TYPE(GT64111, gt64111_device)
17
18 /*************************************
19 * Structures
20 *************************************/
21 class gt64xxx_device : public pci_host_device {
22 public:
23 virtual void reset_all_mappings() override;
24 virtual void map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
25 uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
26
27 template <typename T> void set_cpu_tag(T &&tag) { m_cpu.set_tag(std::forward<T>(tag)); }
28 void set_be(int be) { m_be = be; }
29 void set_autoconfig(int autoconfig) { m_autoconfig = autoconfig; }
30 void set_irq_num(int irq_num) { m_irq_num = irq_num; }
31 virtual void config_map(address_map &map) override;
32 void set_simm_size(int index, int size) { m_simm_size[index] = size; };
33 void set_simm0_size(int size) { m_simm_size[0] = size; };
34 void set_simm1_size(int size) { m_simm_size[1] = size; };
35
36 DECLARE_WRITE_LINE_MEMBER(pci_stall);
37
38 // pci bus
39 uint32_t pci_config_r(offs_t offset, uint32_t mem_mask = ~0);
40 void pci_config_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
41
42 // cpu bus
43 uint32_t cpu_if_r(offs_t offset);
44 void cpu_if_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
45
46 uint32_t master_mem0_r(offs_t offset, uint32_t mem_mask = ~0);
47 void master_mem0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
48
49 uint32_t master_mem1_r(offs_t offset, uint32_t mem_mask = ~0);
50 void master_mem1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
51
52 uint32_t master_io_r(offs_t offset, uint32_t mem_mask = ~0);
53 void master_io_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
54
55 // devices
56 uint32_t ras_0_r(offs_t offset, uint32_t mem_mask = ~0);
57 void ras_0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
58 uint32_t ras_1_r(offs_t offset, uint32_t mem_mask = ~0);
59 void ras_1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
60 uint32_t ras_2_r(offs_t offset, uint32_t mem_mask = ~0);
61 void ras_2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
62 uint32_t ras_3_r(offs_t offset, uint32_t mem_mask = ~0);
63 void ras_3_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
64
65 // Enums
66 enum proc_addr_bank {ADDR_RAS1_0, ADDR_RAS3_2, ADDR_CS2_0, ADDR_CS3_BCS, ADDR_PCI_IO, ADDR_PCI_MEM0, ADDR_PCI_MEM1, ADDR_NUM};
67
68 void set_map(int id, const address_map_constructor &map, device_t *device);
69 virtual void device_post_load() override;
70
71 protected:
72 gt64xxx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
73
74 address_space *m_cpu_space;
75 virtual space_config_vector memory_space_config() const override;
76 virtual void device_start() override;
77 virtual void device_reset() override;
78
79
80 private:
81 enum
82 {
83 AS_PCI_MEM = 1,
84 AS_PCI_IO = 2
85 };
86
87 struct galileo_timer
88 {
89 emu_timer * timer;
90 uint32_t count;
91 uint8_t active;
92 };
93
94 struct galileo_addr_map
95 {
96 uint32_t low_addr;
97 uint32_t high_addr;
98 address_space* space;
99 galileo_addr_map() : low_addr(0xffffffff), high_addr(0x0) {}
100 };
101
102 required_device<mips3_device> m_cpu;
103 int m_be, m_autoconfig;
104 int m_irq_num;
105 int m_simm_size[4];
106
107 int m_pci_stall_state;
108 int m_retry_count;
109 int m_pci_cpu_stalled;
110 uint32_t m_stall_windex;
111 uint32_t m_cpu_stalled_offset[2];
112 uint32_t m_cpu_stalled_data[2];
113 uint32_t m_cpu_stalled_mem_mask[2];
114
115 address_space_config m_mem_config, m_io_config;
116
117 required_memory_region m_romRegion;
118 optional_memory_region m_updateRegion;
119
120 void cpu_map(address_map &map);
121
122 void map_cpu_space();
123
124 uint32_t m_prev_addr;
125 /* raw register data */
126 uint32_t m_reg[0xd00/4];
127
128 /* timer info */
129 galileo_timer m_timer[4];
130 TIMER_CALLBACK_MEMBER(timer_callback);
131
132 /* DMA info */
133 int8_t m_dma_active;
134
135 // Ram
136 std::vector<uint32_t> m_ram[4];
137
138 // Chip Select
139 device_t *m_cs_devices[4];
140 address_map_constructor m_cs_maps[4];
141
142 void update_irqs();
143
144 int m_last_dma;
145 emu_timer* m_dma_timer;
146 galileo_addr_map dma_addr_map[proc_addr_bank::ADDR_NUM];
147 int dma_fetch_next(address_space &space, int which);
148 TIMER_CALLBACK_MEMBER(perform_dma);
149 address_space* dma_decode_address(uint32_t &addr);
150 };
151
152 // Supports R4600/4650/4700/R5000 CPUs
153 class gt64010_device : public gt64xxx_device {
154 public:
155 template <typename T>
gt64010_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock,T && cpu_tag,int irq_num)156 gt64010_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, int irq_num)
157 : gt64010_device(mconfig, tag, owner, clock)
158 {
159 set_ids_host(0x11ab0146, 0x03, 0x00000000);
160 set_cpu_tag(std::forward<T>(cpu_tag));
161 set_irq_num(irq_num);
162 }
gt64010_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)163 gt64010_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
164 : gt64xxx_device(mconfig, GT64010, tag, owner, clock) {}
165 };
166
167 // Supports the following 32-bit bus CPUs:
168 // IDT RC4640 and RC4650 (in 32-bit mode)
169 // QED RM523X
170 // NEC/Toshiba VR4300
171 class gt64111_device : public gt64xxx_device {
172 public:
173 template <typename T>
gt64111_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock,T && cpu_tag,int irq_num)174 gt64111_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag, int irq_num)
175 : gt64111_device(mconfig, tag, owner, clock)
176 {
177 set_ids(0x414611ab, 0x10, 0x058000, 0x00000000);
178 set_cpu_tag(std::forward<T>(cpu_tag));
179 set_irq_num(irq_num);
180 }
gt64111_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)181 gt64111_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
182 : gt64xxx_device(mconfig, GT64111, tag, owner, clock) {}
183 };
184
185 #endif // MAME_MACHINE_GT64XXX_H
186