1 // license:BSD-3-Clause
2 // copyright-holders:Aaron Giles
3 /*
4 Flash ROM emulation
5
6 Explicitly supports:
7 Intel 28F016S5 (byte-wide)
8 AMD/Fujitsu 29F016 (byte-wide)
9 Sharp LH28F400 (word-wide)
10
11 Flash ROMs use a standardized command set across manufacturers,
12 so this emulation should work even for non-Intel and non-Sharp chips
13 as long as the game doesn't query the maker ID.
14 */
15
16 #include "emu.h"
17 #include "intelfsh.h"
18
19
20 //**************************************************************************
21 // CONSTANTS
22 //**************************************************************************
23
24 enum
25 {
26 FM_NORMAL, // normal read/write
27 FM_READID, // read ID
28 FM_READSTATUS, // read status
29 FM_WRITEPART1, // first half of programming, awaiting second
30 FM_CLEARPART1, // first half of clear, awaiting second
31 FM_SETMASTER, // first half of set master lock, awaiting on/off
32 FM_READAMDID1, // part 1 of alt ID sequence
33 FM_READAMDID2, // part 2 of alt ID sequence
34 FM_READAMDID3, // part 3 of alt ID sequence
35 FM_ERASEAMD1, // part 1 of AMD erase sequence
36 FM_ERASEAMD2, // part 2 of AMD erase sequence
37 FM_ERASEAMD3, // part 3 of AMD erase sequence
38 FM_ERASEAMD4, // part 4 of AMD erase sequence
39 FM_BYTEPROGRAM,
40 FM_BANKSELECT,
41 FM_WRITEPAGEATMEL
42 };
43
44
45 enum
46 {
47 MFG_ALLIANCE = 0x52,
48 MFG_AMD = 0x01,
49 MFG_AMIC = 0x37,
50 MFG_ATMEL = 0x1f,
51 MFG_BRIGHT = 0xad,
52 MFG_CATALYST = 0x31,
53 MFG_EON = 0x1c,
54 MFG_FUJITSU = 0x04,
55 MFG_GIGADEVICE = 0xc8,
56 MFG_HYUNDAI = 0xad,
57 MFG_INTEL = 0x89,
58 MFG_ISSI = 0xd5,
59 MFG_MACRONIX = 0xc2,
60 MFG_PANASONIC = 0x32,
61 MFG_PMC = 0x9d,
62 MFG_SANYO = 0x62,
63 MFG_SHARP = 0xb0,
64 MFG_SPANSION = 0x01,
65 MFG_SST = 0xbf,
66 MFG_ST = 0x20,
67 MFG_SYNCMOS = 0x40,
68 MFG_TI = 0x97,
69 MFG_TI_OLD = 0x01,
70 MFG_WINBOND_NEX = 0xef,
71 MFG_WINBOND = 0xda
72 };
73
74
75
76 //**************************************************************************
77 // GLOBAL VARIABLES
78 //**************************************************************************
79
80 // device type definition
81 DEFINE_DEVICE_TYPE(INTEL_28F016S5, intel_28f016s5_device, "intel_28f016s5", "Intel 28F016S5 Flash")
82 DEFINE_DEVICE_TYPE(SHARP_LH28F016S, sharp_lh28f016s_device, "sharp_lh28f016s", "Sharp LH28F016S Flash")
83 DEFINE_DEVICE_TYPE(SHARP_LH28F016S_16BIT, sharp_lh28f016s_16bit_device, "sharp_lh28f016s_16bit", "Sharp LH28F016S Flash (16-bit)")
84 DEFINE_DEVICE_TYPE(ATMEL_29C010, atmel_29c010_device, "atmel_29c010", "Atmel 29C010 Flash")
85 DEFINE_DEVICE_TYPE(AMD_29F010, amd_29f010_device, "amd_29f010", "AMD 29F010 Flash")
86 DEFINE_DEVICE_TYPE(AMD_29F040, amd_29f040_device, "amd_29f040", "AMD 29F040 Flash")
87 DEFINE_DEVICE_TYPE(AMD_29F080, amd_29f080_device, "amd_29f080", "AMD 29F080 Flash")
88 DEFINE_DEVICE_TYPE(AMD_29F400T, amd_29f400t_device, "amd_29f400t", "AMD 29F400T Flash")
89 DEFINE_DEVICE_TYPE(AMD_29F800T, amd_29f800t_device, "amd_29f800t", "AMD 29F800T Flash")
90 DEFINE_DEVICE_TYPE(AMD_29F800B_16BIT, amd_29f800b_16bit_device, "amd_29f800b_16bit", "AMD 29F800B Flash (16-bit)")
91 DEFINE_DEVICE_TYPE(AMD_29LV200T, amd_29lv200t_device, "amd_29lv200t", "AMD 29LV200T Flash")
92 DEFINE_DEVICE_TYPE(FUJITSU_29F160TE, fujitsu_29f160te_device, "mbm29f160te", "Fujitsu MBM29F160TE Flash")
93 DEFINE_DEVICE_TYPE(FUJITSU_29F016A, fujitsu_29f016a_device, "mbm29f016a", "Fujitsu MBM29F016A Flash")
94 DEFINE_DEVICE_TYPE(FUJITSU_29DL164BD, fujitsu_29dl164bd_device, "mbm29dl164bd", "Fujitsu MBM29DL164BD Flash")
95 DEFINE_DEVICE_TYPE(FUJITSU_29LV002TC, fujitsu_29lv002tc_device, "mbm29lv002tc", "Fujitsu MBM29LV002TC Flash")
96 DEFINE_DEVICE_TYPE(FUJITSU_29LV800B, fujitsu_29lv800b_device, "mbm29lv800b", "Fujitsu MBM29LV800B Flash")
97 DEFINE_DEVICE_TYPE(INTEL_E28F400B, intel_e28f400b_device, "intel_e28f400b", "Intel E28F400B Flash")
98 DEFINE_DEVICE_TYPE(MACRONIX_29L001MC, macronix_29l001mc_device, "macronix_29l001mc", "Macronix 29L001MC Flash")
99 DEFINE_DEVICE_TYPE(MACRONIX_29LV160TMC, macronix_29lv160tmc_device, "macronix_29lv160tmc", "Macronix 29LV160TMC Flash")
100 DEFINE_DEVICE_TYPE(TMS_29F040, tms_29f040_device, "tms_29f040", "Texas Instruments 29F040 Flash")
101
102 DEFINE_DEVICE_TYPE(PANASONIC_MN63F805MNP, panasonic_mn63f805mnp_device, "panasonic_mn63f805mnp", "Panasonic MN63F805MNP Flash")
103 DEFINE_DEVICE_TYPE(SANYO_LE26FV10N1TS, sanyo_le26fv10n1ts_device, "sanyo_le26fv10n1ts", "Sanyo LE26FV10N1TS Flash")
104 DEFINE_DEVICE_TYPE(SST_28SF040, sst_28sf040_device, "sst_28sf040", "SST 28SF040 Flash")
105 DEFINE_DEVICE_TYPE(SST_39SF040, sst_39sf040_device, "sst_39sf040", "SST 39SF040 Flash")
106 DEFINE_DEVICE_TYPE(SST_39VF020, sst_39vf020_device, "sst_39vf020", "SST 39VF020 Flash")
107 DEFINE_DEVICE_TYPE(SST_49LF020, sst_49lf020_device, "sst_49lf020", "SST 49LF020 Flash")
108
109 DEFINE_DEVICE_TYPE(SHARP_LH28F400, sharp_lh28f400_device, "sharp_lh28f400", "Sharp LH28F400 Flash")
110 DEFINE_DEVICE_TYPE(INTEL_E28F008SA, intel_e28f008sa_device, "intel_e28f008sa", "Intel E28F008SA Flash")
111 DEFINE_DEVICE_TYPE(INTEL_TE28F160, intel_te28f160_device, "intel_te28f160", "Intel TE28F160 Flash")
112 DEFINE_DEVICE_TYPE(SHARP_LH28F160S3, sharp_lh28f160s3_device, "sharp_lh28f160s3", "Sharp LH28F160S3 Flash")
113 DEFINE_DEVICE_TYPE(INTEL_TE28F320, intel_te28f320_device, "intel_te28f320", "Intel TE28F320 Flash")
114 DEFINE_DEVICE_TYPE(SHARP_LH28F320BF, sharp_lh28f320bf_device, "sharp_lh28f320bf", "Sharp LH28F320BFHE-PBTL Flash")
115 DEFINE_DEVICE_TYPE(INTEL_28F320J3D, intel_28f320j3d_device, "intel_28f320j3d", "Intel 28F320J3D Flash")
116 DEFINE_DEVICE_TYPE(SPANSION_S29GL064S, spansion_s29gl064s_device, "spansion_s29gl064s", "Spansion / Cypress S29GL064S Flash" )
117 DEFINE_DEVICE_TYPE(INTEL_28F320J5, intel_28f320j5_device, "intel_28f320j5", "Intel 28F320J5 Flash")
118
119 DEFINE_DEVICE_TYPE(SST_39VF400A, sst_39vf400a_device, "sst_39vf400a", "SST 39VF400A Flash")
120
121 DEFINE_DEVICE_TYPE(ATMEL_49F4096, atmel_49f4096_device, "atmel_49f4096", "Atmel AT49F4096 Flash")
122
123 DEFINE_DEVICE_TYPE(CAT28F020, cat28f020_device, "cat28f020", "CSI CAT28F020 Flash")
124
125
126
127 //**************************************************************************
128 // LIVE DEVICE
129 //**************************************************************************
130
131 //-------------------------------------------------
132 // intelfsh_device - constructor
133 //-------------------------------------------------
134
intelfsh_device(const machine_config & mconfig,device_type type,const char * tag,device_t * owner,uint32_t clock,uint32_t variant)135 intelfsh_device::intelfsh_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant)
136 : device_t(mconfig, type, tag, owner, clock),
137 device_nvram_interface(mconfig, *this),
138 m_region(*this, DEVICE_SELF),
139 m_type(variant),
140 m_size(0),
141 m_bits(8),
142 m_addrmask(0),
143 m_device_id(0),
144 m_maker_id(0),
145 m_sector_is_4k(false),
146 m_sector_is_16k(false),
147 m_top_boot_sector(false),
148 m_bot_boot_sector(false),
149 m_status(0x80),
150 m_erase_sector(0),
151 m_flash_mode(FM_NORMAL),
152 m_flash_master_lock(false),
153 m_timer(nullptr),
154 m_bank(0)
155 {
156 switch( variant )
157 {
158 case FLASH_INTEL_28F016S5:
159 case FLASH_SHARP_LH28F016S:
160 m_bits = 8;
161 m_size = 0x200000;
162 m_maker_id = MFG_INTEL;
163 m_device_id = 0xaa;
164 break;
165 case FLASH_SHARP_LH28F016S_16BIT:
166 m_bits = 16;
167 m_size = 0x200000;
168 m_maker_id = MFG_INTEL;
169 m_device_id = 0xaa;
170 break;
171 case FLASH_ATMEL_29C010:
172 m_bits = 8;
173 m_size = 0x20000;
174 m_page_size = 0x80;
175 m_maker_id = MFG_ATMEL;
176 m_device_id = 0xd5;
177 break;
178 case FLASH_ATMEL_49F4096:
179 m_bits = 16;
180 m_size = 0x80000;
181 m_maker_id = MFG_ATMEL;
182 m_device_id = 0x92;
183 m_sector_is_16k = true;
184 break;
185 case FLASH_AMD_29F010:
186 m_bits = 8;
187 m_size = 0x20000;
188 m_maker_id = MFG_AMD;
189 m_device_id = 0x20;
190 break;
191 case FLASH_AMD_29F040:
192 m_bits = 8;
193 m_size = 0x80000;
194 m_maker_id = MFG_AMD;
195 m_device_id = 0xa4;
196 break;
197 case FLASH_AMD_29F080:
198 m_bits = 8;
199 m_size = 0x100000;
200 m_addrmask = 0x7ff;
201 m_maker_id = MFG_AMD;
202 m_device_id = 0xd5;
203 break;
204 case FLASH_AMD_29F400T:
205 m_bits = 8;
206 m_size = 0x80000;
207 m_maker_id = MFG_AMD;
208 m_device_id = 0x23;
209 m_top_boot_sector = true;
210 break;
211 case FLASH_AMD_29F800T:
212 m_bits = 8;
213 m_size = 0x100000;
214 m_maker_id = MFG_AMD;
215 m_device_id = 0xda;
216 m_top_boot_sector = true;
217 break;
218 case FLASH_AMD_29F800B_16BIT:
219 m_bits = 16;
220 m_size = 0x100000;
221 m_maker_id = MFG_AMD;
222 m_device_id = 0x2258;
223 m_top_boot_sector = false;
224 break;
225 case FLASH_AMD_29LV200T:
226 m_bits = 8;
227 m_size = 0x40000;
228 m_maker_id = MFG_AMD;
229 m_device_id = 0x3b;
230 break;
231 case FLASH_CAT28F020:
232 m_bits = 8;
233 m_size = 0x40000;
234 m_maker_id = MFG_CATALYST;
235 m_device_id = 0xbd;
236 break;
237 case FLASH_INTEL_28F320J3D:
238 m_bits = 16;
239 m_size = 0x400000;
240 m_maker_id = MFG_INTEL;
241 m_device_id = 0x16;
242 m_sector_is_4k = true;
243 break;
244 case FLASH_SPANSION_S29GL064S: // senbbs
245 m_bits = 16;
246 m_size = 0x800000;
247 m_maker_id = MFG_SPANSION;
248 m_device_id = 0x227e;
249 m_sector_is_4k = false;
250 break;
251 case FLASH_INTEL_28F320J5: // funkball
252 m_bits = 16;
253 m_size = 0x400000;
254 m_maker_id = MFG_INTEL;
255 m_device_id = 0x14;
256 // m_sector_is_4k = true; 128kb?
257 break;
258 case FLASH_SST_39SF040:
259 m_bits = 8;
260 m_size = 0x80000;
261 m_maker_id = MFG_SST;
262 m_device_id = 0xb7;
263 m_sector_is_4k = true;
264 break;
265 case FLASH_SST_39VF020:
266 m_bits = 8;
267 m_size = 0x40000;
268 m_maker_id = MFG_SST;
269 m_device_id = 0xd6;
270 m_sector_is_4k = true;
271 break;
272 case FLASH_SST_49LF020:
273 m_bits = 8;
274 m_size = 0x40000;
275 m_maker_id = MFG_SST;
276 m_device_id = 0x61;
277 m_sector_is_4k = true;
278 break;
279 case FLASH_SST_39VF400A:
280 m_bits = 16;
281 m_size = 0x80000;
282 m_maker_id = MFG_SST;
283 m_device_id = 0xd6;
284 m_sector_is_4k = true;
285 break;
286 case FLASH_SHARP_LH28F400:
287 m_bits = 16;
288 m_size = 0x80000;
289 m_maker_id = MFG_SHARP;
290 m_device_id = 0xed;
291 break;
292 case FLASH_INTEL_E28F400B:
293 m_bits = 16;
294 m_size = 0x80000;
295 m_maker_id = MFG_INTEL;
296 m_device_id = 0x4471;
297 break;
298 case FLASH_FUJITSU_29F160TE:
299 m_bits = 8;
300 m_size = 0x200000;
301 m_maker_id = MFG_FUJITSU;
302 m_device_id = 0xd2;
303 m_top_boot_sector = true;
304 break;
305 case FLASH_FUJITSU_29F016A:
306 m_bits = 8;
307 m_size = 0x200000;
308 m_maker_id = MFG_FUJITSU;
309 m_device_id = 0xad;
310 break;
311 case FLASH_FUJITSU_29DL164BD:
312 m_bits = 8;
313 m_size = 0x200000;
314 m_maker_id = MFG_FUJITSU;
315 m_device_id = 0x35;
316 break;
317 case FLASH_FUJITSU_29LV002TC:
318 m_bits = 8;
319 m_size = 0x40000;
320 m_maker_id = MFG_FUJITSU;
321 m_device_id = 0x40;
322 break;
323 case FLASH_FUJITSU_29LV800B:
324 m_bits = 16;
325 m_size = 0x100000;
326 m_maker_id = MFG_FUJITSU;
327 m_device_id = 0x225b;
328 m_bot_boot_sector = true;
329 break;
330 case FLASH_INTEL_E28F008SA:
331 m_bits = 8;
332 m_size = 0x100000;
333 m_maker_id = MFG_INTEL;
334 m_device_id = 0xa2;
335 break;
336 case FLASH_INTEL_TE28F160:
337 case FLASH_SHARP_LH28F160S3:
338 m_bits = 16;
339 m_size = 0x200000;
340 m_maker_id = MFG_SHARP;
341 m_device_id = 0xd0;
342 break;
343 case FLASH_INTEL_TE28F320:
344 m_bits = 16;
345 m_size = 0x400000;
346 m_maker_id = MFG_INTEL;
347 m_device_id = 0x8896;
348 break;
349 case FLASH_SHARP_LH28F320BF:
350 m_bits = 16;
351 m_size = 0x400000;
352 m_maker_id = MFG_SHARP;
353 m_device_id = 0xb5;
354 break;
355 case FLASH_MACRONIX_29L001MC:
356 m_bits = 8;
357 m_size = 0x20000;
358 m_maker_id = MFG_MACRONIX;
359 m_device_id = 0x51;
360 break;
361 case FLASH_MACRONIX_29LV160TMC:
362 m_bits = 8;
363 m_size = 0x20000;
364 m_maker_id = MFG_MACRONIX;
365 m_device_id = 0x49;
366 m_sector_is_16k = true;
367 break;
368 case FLASH_PANASONIC_MN63F805MNP:
369 m_bits = 8;
370 m_size = 0x10000;
371 m_maker_id = MFG_PANASONIC;
372 m_device_id = 0x1b;
373 m_sector_is_4k = true;
374 break;
375 case FLASH_SANYO_LE26FV10N1TS:
376 m_bits = 8;
377 m_size = 0x20000;
378 m_maker_id = MFG_SANYO;
379 m_device_id = 0x13;
380 m_sector_is_4k = true;
381 break;
382 case FLASH_SST_28SF040:
383 m_bits = 8;
384 m_size = 0x80000;
385 m_maker_id = MFG_SST;
386 m_device_id = 0x04;
387 break;
388 case FLASH_TMS_29F040:
389 m_bits = 8;
390 m_addrmask = 0x7fff;
391 m_size = 0x80000;
392 m_maker_id = MFG_AMD;
393 m_device_id = 0xa4;
394 break;
395 }
396
397 int addrbits;
398 for (addrbits = 24; addrbits > 0; addrbits--)
399 if ((m_size & (1 << addrbits)) != 0)
400 break;
401 }
402
intelfsh8_device(const machine_config & mconfig,device_type type,const char * tag,device_t * owner,uint32_t clock,uint32_t variant)403 intelfsh8_device::intelfsh8_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant)
404 : intelfsh_device(mconfig, type, tag, owner, clock, variant) { }
405
intelfsh16_device(const machine_config & mconfig,device_type type,const char * tag,device_t * owner,uint32_t clock,uint32_t variant)406 intelfsh16_device::intelfsh16_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t variant)
407 : intelfsh_device(mconfig, type, tag, owner, clock, variant) { }
408
409
intel_28f016s5_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)410 intel_28f016s5_device::intel_28f016s5_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
411 : intelfsh8_device(mconfig, INTEL_28F016S5, tag, owner, clock, FLASH_INTEL_28F016S5) { }
412
fujitsu_29f160te_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)413 fujitsu_29f160te_device::fujitsu_29f160te_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
414 : intelfsh8_device(mconfig, FUJITSU_29F160TE, tag, owner, clock, FLASH_FUJITSU_29F160TE) { }
415
fujitsu_29f016a_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)416 fujitsu_29f016a_device::fujitsu_29f016a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
417 : intelfsh8_device(mconfig, FUJITSU_29F016A, tag, owner, clock, FLASH_FUJITSU_29F016A) { }
418
fujitsu_29dl164bd_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)419 fujitsu_29dl164bd_device::fujitsu_29dl164bd_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
420 : intelfsh8_device(mconfig, FUJITSU_29DL164BD, tag, owner, clock, FLASH_FUJITSU_29DL164BD) { }
421
fujitsu_29lv002tc_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)422 fujitsu_29lv002tc_device::fujitsu_29lv002tc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
423 : intelfsh8_device(mconfig, FUJITSU_29LV002TC, tag, owner, clock, FLASH_FUJITSU_29LV002TC) { }
424
fujitsu_29lv800b_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)425 fujitsu_29lv800b_device::fujitsu_29lv800b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
426 : intelfsh16_device(mconfig, FUJITSU_29LV800B, tag, owner, clock, FLASH_FUJITSU_29LV800B) { }
427
sharp_lh28f016s_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)428 sharp_lh28f016s_device::sharp_lh28f016s_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
429 : intelfsh8_device(mconfig, SHARP_LH28F016S, tag, owner, clock, FLASH_SHARP_LH28F016S) { }
430
sharp_lh28f016s_16bit_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)431 sharp_lh28f016s_16bit_device::sharp_lh28f016s_16bit_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
432 : intelfsh16_device(mconfig, SHARP_LH28F016S_16BIT, tag, owner, clock, FLASH_SHARP_LH28F016S_16BIT) { }
433
atmel_29c010_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)434 atmel_29c010_device::atmel_29c010_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
435 : intelfsh8_device(mconfig, ATMEL_29C010, tag, owner, clock, FLASH_ATMEL_29C010) { }
436
atmel_49f4096_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)437 atmel_49f4096_device::atmel_49f4096_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
438 : intelfsh16_device(mconfig, ATMEL_49F4096, tag, owner, clock, FLASH_ATMEL_49F4096) { }
439
amd_29f010_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)440 amd_29f010_device::amd_29f010_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
441 : intelfsh8_device(mconfig, AMD_29F010, tag, owner, clock, FLASH_AMD_29F010) { }
442
amd_29f040_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)443 amd_29f040_device::amd_29f040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
444 : intelfsh8_device(mconfig, AMD_29F040, tag, owner, clock, FLASH_AMD_29F040) { }
445
amd_29f080_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)446 amd_29f080_device::amd_29f080_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
447 : intelfsh8_device(mconfig, AMD_29F080, tag, owner, clock, FLASH_AMD_29F080) { }
448
amd_29f400t_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)449 amd_29f400t_device::amd_29f400t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
450 : intelfsh8_device(mconfig, AMD_29F400T, tag, owner, clock, FLASH_AMD_29F400T) { }
451
amd_29f800t_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)452 amd_29f800t_device::amd_29f800t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
453 : intelfsh8_device(mconfig, AMD_29F800T, tag, owner, clock, FLASH_AMD_29F800T) { }
454
amd_29f800b_16bit_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)455 amd_29f800b_16bit_device::amd_29f800b_16bit_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
456 : intelfsh16_device(mconfig, AMD_29F800B_16BIT, tag, owner, clock, FLASH_AMD_29F800B_16BIT) { }
457
amd_29lv200t_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)458 amd_29lv200t_device::amd_29lv200t_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
459 : intelfsh8_device(mconfig, AMD_29LV200T, tag, owner, clock, FLASH_AMD_29LV200T) { }
460
cat28f020_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)461 cat28f020_device::cat28f020_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
462 : intelfsh8_device(mconfig, CAT28F020, tag, owner, clock, FLASH_CAT28F020) { }
463
intel_e28f008sa_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)464 intel_e28f008sa_device::intel_e28f008sa_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
465 : intelfsh8_device(mconfig, INTEL_E28F008SA, tag, owner, clock, FLASH_INTEL_E28F008SA) { }
466
macronix_29l001mc_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)467 macronix_29l001mc_device::macronix_29l001mc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
468 : intelfsh8_device(mconfig, MACRONIX_29L001MC, tag, owner, clock, FLASH_MACRONIX_29L001MC) { }
469
macronix_29lv160tmc_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)470 macronix_29lv160tmc_device::macronix_29lv160tmc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
471 : intelfsh8_device(mconfig, MACRONIX_29LV160TMC, tag, owner, clock, FLASH_MACRONIX_29LV160TMC) { }
472
panasonic_mn63f805mnp_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)473 panasonic_mn63f805mnp_device::panasonic_mn63f805mnp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
474 : intelfsh8_device(mconfig, PANASONIC_MN63F805MNP, tag, owner, clock, FLASH_PANASONIC_MN63F805MNP) { }
475
sanyo_le26fv10n1ts_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)476 sanyo_le26fv10n1ts_device::sanyo_le26fv10n1ts_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
477 : intelfsh8_device(mconfig, SANYO_LE26FV10N1TS, tag, owner, clock, FLASH_SANYO_LE26FV10N1TS) { }
478
sst_28sf040_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)479 sst_28sf040_device::sst_28sf040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
480 : intelfsh8_device(mconfig, SST_28SF040, tag, owner, clock, FLASH_SST_28SF040) { }
481
sst_39sf040_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)482 sst_39sf040_device::sst_39sf040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
483 : intelfsh8_device(mconfig, SST_39SF040, tag, owner, clock, FLASH_SST_39SF040) { }
484
sst_39vf020_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)485 sst_39vf020_device::sst_39vf020_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
486 : intelfsh8_device(mconfig, SST_39VF020, tag, owner, clock, FLASH_SST_39VF020) { }
487
sst_49lf020_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)488 sst_49lf020_device::sst_49lf020_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
489 : intelfsh8_device(mconfig, SST_49LF020, tag, owner, clock, FLASH_SST_49LF020) { }
490
sharp_lh28f400_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)491 sharp_lh28f400_device::sharp_lh28f400_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
492 : intelfsh16_device(mconfig, SHARP_LH28F400, tag, owner, clock, FLASH_SHARP_LH28F400) { }
493
intel_te28f160_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)494 intel_te28f160_device::intel_te28f160_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
495 : intelfsh16_device(mconfig, INTEL_TE28F160, tag, owner, clock, FLASH_INTEL_TE28F160) { }
496
sharp_lh28f160s3_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)497 sharp_lh28f160s3_device::sharp_lh28f160s3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
498 : intelfsh16_device(mconfig, SHARP_LH28F160S3, tag, owner, clock, FLASH_SHARP_LH28F160S3) { }
499
intel_te28f320_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)500 intel_te28f320_device::intel_te28f320_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
501 : intelfsh16_device(mconfig, INTEL_TE28F320, tag, owner, clock, FLASH_INTEL_TE28F320) { }
502
spansion_s29gl064s_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)503 spansion_s29gl064s_device::spansion_s29gl064s_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
504 : intelfsh16_device(mconfig, SPANSION_S29GL064S, tag, owner, clock, FLASH_SPANSION_S29GL064S) { }
505
intel_e28f400b_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)506 intel_e28f400b_device::intel_e28f400b_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
507 : intelfsh16_device(mconfig, INTEL_E28F400B, tag, owner, clock, FLASH_INTEL_E28F400B) { }
508
sharp_lh28f320bf_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)509 sharp_lh28f320bf_device::sharp_lh28f320bf_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
510 : intelfsh16_device(mconfig, SHARP_LH28F320BF, tag, owner, clock, FLASH_SHARP_LH28F320BF) { }
511
intel_28f320j3d_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)512 intel_28f320j3d_device::intel_28f320j3d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
513 : intelfsh16_device(mconfig, INTEL_28F320J3D, tag, owner, clock, FLASH_INTEL_28F320J3D) { }
514
intel_28f320j5_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)515 intel_28f320j5_device::intel_28f320j5_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
516 : intelfsh16_device(mconfig, INTEL_28F320J5, tag, owner, clock, FLASH_INTEL_28F320J5) { }
517
518
sst_39vf400a_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)519 sst_39vf400a_device::sst_39vf400a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
520 : intelfsh16_device(mconfig, SST_39VF400A, tag, owner, clock, FLASH_SST_39VF400A) { }
521
522
tms_29f040_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)523 tms_29f040_device::tms_29f040_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
524 : intelfsh8_device(mconfig, TMS_29F040, tag, owner, clock, FLASH_TMS_29F040) { }
525
526 //-------------------------------------------------
527 // device_start - device-specific startup
528 //-------------------------------------------------
529
device_start()530 void intelfsh_device::device_start()
531 {
532 m_data = std::make_unique<uint8_t []>(m_size);
533 m_timer = timer_alloc();
534
535 save_item( NAME(m_status) );
536 save_item( NAME(m_flash_mode) );
537 save_item( NAME(m_flash_master_lock) );
538 save_pointer( &m_data[0], "m_data", m_size);
539 }
540
541
542 //-------------------------------------------------
543 // device_timer - handler timer events
544 //-------------------------------------------------
545
device_timer(emu_timer & timer,device_timer_id id,int param,void * ptr)546 void intelfsh_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
547 {
548 switch( m_flash_mode )
549 {
550 case FM_READSTATUS:
551 m_status = 0x80;
552 break;
553
554 case FM_ERASEAMD4:
555 m_flash_mode = FM_NORMAL;
556 break;
557 }
558 }
559
560
561 //-------------------------------------------------
562 // nvram_default - called to initialize NVRAM to
563 // its default state
564 //-------------------------------------------------
565
nvram_default()566 void intelfsh_device::nvram_default()
567 {
568 // region always wins
569 if (m_region.found())
570 {
571 uint32_t bytes = m_region->bytes();
572 if (bytes > m_size)
573 bytes = m_size;
574
575 if (m_bits == 8)
576 {
577 for (offs_t offs = 0; offs < bytes; offs++)
578 m_data[offs] = m_region->as_u8(offs);
579 }
580 else
581 {
582 for (offs_t offs = 0; offs < bytes; offs += 2) {
583 uint16_t v = m_region->as_u16(offs / 2);
584 m_data[offs] = v >> 8;
585 m_data[offs+1] = v;
586 }
587 }
588 return;
589 }
590
591 // otherwise, default to 0xff
592 memset(&m_data[0], 0xff, m_size);
593 }
594
595
596 //-------------------------------------------------
597 // nvram_read - called to read NVRAM from the
598 // .nv file
599 //-------------------------------------------------
600
nvram_read(emu_file & file)601 void intelfsh_device::nvram_read(emu_file &file)
602 {
603 file.read(&m_data[0], m_size);
604 }
605
606
607 //-------------------------------------------------
608 // nvram_write - called to write NVRAM to the
609 // .nv file
610 //-------------------------------------------------
611
nvram_write(emu_file & file)612 void intelfsh_device::nvram_write(emu_file &file)
613 {
614 file.write(&m_data[0], m_size);
615 }
616
617
618 //-------------------------------------------------
619 // read_full - generic read, called by the
620 // bit-width-specific readers
621 //-------------------------------------------------
622
read_full(uint32_t address)623 uint32_t intelfsh_device::read_full(uint32_t address)
624 {
625 uint32_t data = 0;
626 address += m_bank << 16;
627 switch( m_flash_mode )
628 {
629 default:
630 case FM_NORMAL:
631 switch( m_bits )
632 {
633 case 8:
634 data = m_data[address];
635 break;
636 case 16:
637 data = (m_data[address*2] << 8) | m_data[address*2+1];
638 break;
639 }
640 break;
641 case FM_READSTATUS:
642 data = m_status;
643 break;
644 case FM_READAMDID3:
645 if ((m_maker_id == MFG_FUJITSU && m_device_id == 0x35) || (m_maker_id == MFG_AMD && m_device_id == 0x3b))
646 {
647 // used in Fujitsu 29DL16X 8bits mode
648 // used in AMD 29LV200 8bits mode
649 switch (address & 0xff)
650 {
651 case 0: data = m_maker_id; break;
652 case 2: data = m_device_id; break;
653 case 4: data = 0; break;
654 }
655 }
656 else
657 {
658 switch (address & 0xff)
659 {
660 case 0: data = m_maker_id; break;
661 case 1: data = m_device_id; break;
662 case 2: data = 0; break;
663 }
664 }
665 break;
666 case FM_READID:
667 if (m_maker_id == MFG_INTEL && m_device_id == 0x16)
668 {
669 switch (address & 0xff)
670 {
671 case 0: data = m_maker_id; break;
672 case 2: data = m_device_id; break;
673 case 4: data = 0; break;
674 }
675 }
676 else
677 {
678 switch (address & 0xff)
679 {
680 case 0: // maker ID
681 data = m_maker_id;
682 break;
683 case 1: // chip ID
684 data = m_device_id;
685 break;
686 case 2: // block lock config
687 data = 0; // we don't support this yet
688 break;
689 case 3: // master lock config
690 if (m_flash_master_lock)
691 {
692 data = 1;
693 }
694 else
695 {
696 data = 0;
697 }
698 break;
699 }
700 }
701 break;
702 case FM_ERASEAMD4:
703 // reads outside of the erasing sector return normal data
704 if ((address < m_erase_sector) || (address >= m_erase_sector+(64*1024)))
705 {
706 switch( m_bits )
707 {
708 case 8:
709 data = m_data[address];
710 break;
711 case 16:
712 data = (m_data[address*2] << 8) | m_data[address*2+1];
713 break;
714 }
715 }
716 else
717 {
718 m_status ^= ( 1 << 6 ) | ( 1 << 2 );
719 data = m_status;
720 }
721 break;
722 }
723
724 //if (m_flash_mode != FM_NORMAL) logerror( "intelflash_read( %08x ) %08x\n", address, data );
725
726 return data;
727 }
728
729
730 //-------------------------------------------------
731 // write_full - generic write, called by the
732 // bit-width-specific writers
733 //-------------------------------------------------
734
write_full(uint32_t address,uint32_t data)735 void intelfsh_device::write_full(uint32_t address, uint32_t data)
736 {
737 //logerror( "intelflash_write( %u : %08x, %08x )\n", m_flash_mode, address, data );
738
739 address += m_bank << 16;
740
741 switch( m_flash_mode )
742 {
743 case FM_NORMAL:
744 case FM_READSTATUS:
745 case FM_READID:
746 case FM_READAMDID3:
747 switch( data & 0xff )
748 {
749 case 0xf0:
750 case 0xff: // reset chip mode
751 m_flash_mode = FM_NORMAL;
752 break;
753 case 0x90: // read ID
754 m_flash_mode = FM_READID;
755 break;
756 case 0x40:
757 case 0x10: // program
758 m_flash_mode = FM_WRITEPART1;
759 break;
760 case 0x50: // clear status reg
761 if ((m_type == FLASH_SST_49LF020) && (m_flash_mode == FM_NORMAL))
762 logerror("Invalid flash mode byte %x\n", data & 0xff);
763 else
764 {
765 m_status = 0x80;
766 m_flash_mode = FM_READSTATUS;
767 }
768 break;
769 case 0x20: // block erase
770 if (m_type == FLASH_SST_49LF020)
771 logerror("Unknown flash mode byte %x\n", data & 0xff);
772 else
773 m_flash_mode = FM_CLEARPART1;
774 break;
775 case 0x60: // set master lock
776 m_flash_mode = FM_SETMASTER;
777 break;
778 case 0x70: // read status
779 m_flash_mode = FM_READSTATUS;
780 break;
781 case 0xaa: // AMD ID select part 1
782 if( ( address & 0xfff ) == 0x555 )
783 {
784 m_flash_mode = FM_READAMDID1;
785 }
786 else if( ( address & 0xfff ) == 0xaaa )
787 {
788 m_flash_mode = FM_READAMDID1;
789 }
790 break;
791 default:
792 logerror( "Unknown flash mode byte %x\n", data & 0xff );
793 break;
794 }
795 break;
796 case FM_READAMDID1:
797 if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 )
798 {
799 m_flash_mode = FM_READAMDID2;
800 }
801 else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 )
802 {
803 m_flash_mode = FM_READAMDID2;
804 }
805 else if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x55 )
806 {
807 m_flash_mode = FM_READAMDID2;
808 }
809 // for AMD 29F080 address bits A11-A19 don't care, for TMS 29F040 address bits A15-A18 don't care
810 else if( ( address & m_addrmask ) == ( 0xaaaa & m_addrmask ) && ( data & 0xff ) == 0x55 && m_addrmask )
811 {
812 m_flash_mode = FM_READAMDID2;
813 }
814 else
815 {
816 logerror( "unexpected %08x=%02x in FM_READAMDID1\n", address, data & 0xff );
817 m_flash_mode = FM_NORMAL;
818 }
819 break;
820 case FM_READAMDID2:
821 if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x90 )
822 {
823 m_flash_mode = FM_READAMDID3;
824 }
825 else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x90 )
826 {
827 m_flash_mode = FM_READAMDID3;
828 }
829 else if( ( address & 0xfff ) == 0xaaa && ( data & 0xff ) == 0x90 )
830 {
831 m_flash_mode = FM_READAMDID3;
832 }
833 else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x80 )
834 {
835 m_flash_mode = FM_ERASEAMD1;
836 }
837 else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x80 )
838 {
839 m_flash_mode = FM_ERASEAMD1;
840 }
841 else if( ( address & 0xfff ) == 0xaaa && ( data & 0xff ) == 0x80 )
842 {
843 m_flash_mode = FM_ERASEAMD1;
844 }
845 else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xa0 )
846 {
847 m_flash_mode = FM_BYTEPROGRAM;
848 }
849 else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xa0 )
850 {
851 if (m_type == FLASH_ATMEL_29C010)
852 {
853 m_flash_mode = FM_WRITEPAGEATMEL;
854 m_byte_count = 0;
855 }
856 else
857 {
858 m_flash_mode = FM_BYTEPROGRAM;
859 }
860 }
861 else if( ( address & 0xfff ) == 0xaaa && ( data & 0xff ) == 0xa0 )
862 {
863 m_flash_mode = FM_BYTEPROGRAM;
864 }
865 else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xf0 )
866 {
867 m_flash_mode = FM_NORMAL;
868 }
869 else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xf0 )
870 {
871 m_flash_mode = FM_NORMAL;
872 }
873 else if( ( address & 0xfff ) == 0xaaa && ( data & 0xff ) == 0xf0 )
874 {
875 m_flash_mode = FM_NORMAL;
876 }
877 else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xb0 && m_maker_id == MFG_SANYO && m_device_id == 0x13 )
878 {
879 m_flash_mode = FM_BANKSELECT;
880 }
881
882 // for AMD 29F080 address bits A11-A19 don't care, for TMS 29F040 address bits A15-A18 don't care
883 else if(( address & m_addrmask ) == ( 0x5555 & m_addrmask ) && ( data & 0xff ) == 0x80 && m_addrmask )
884 {
885 m_flash_mode = FM_ERASEAMD1;
886 }
887 else if(( address & m_addrmask ) == ( 0x5555 & m_addrmask ) && ( data & 0xff ) == 0x90 && m_addrmask )
888 {
889 m_flash_mode = FM_READAMDID3;
890 }
891 else if(( address & m_addrmask ) == ( 0x5555 & m_addrmask ) && ( data & 0xff ) == 0xa0 && m_addrmask )
892 {
893 m_flash_mode = FM_BYTEPROGRAM;
894 }
895 else if(( address & m_addrmask ) == ( 0x5555 & m_addrmask ) && ( data & 0xff ) == 0xf0 && m_addrmask )
896 {
897 m_flash_mode = FM_NORMAL;
898 }
899 else
900 {
901 logerror( "unexpected %08x=%02x in FM_READAMDID2\n", address, data & 0xff );
902 m_flash_mode = FM_NORMAL;
903 }
904 break;
905 case FM_ERASEAMD1:
906 if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0xaa )
907 {
908 m_flash_mode = FM_ERASEAMD2;
909 }
910 else if( ( address & 0xfff ) == 0xaaa && ( data & 0xff ) == 0xaa )
911 {
912 m_flash_mode = FM_ERASEAMD2;
913 }
914 else
915 {
916 logerror( "unexpected %08x=%02x in FM_ERASEAMD1\n", address, data & 0xff );
917 }
918 break;
919 case FM_ERASEAMD2:
920 if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 )
921 {
922 m_flash_mode = FM_ERASEAMD3;
923 }
924 else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 )
925 {
926 m_flash_mode = FM_ERASEAMD3;
927 }
928 else if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x55 )
929 {
930 m_flash_mode = FM_ERASEAMD3;
931 }
932 else
933 {
934 logerror( "unexpected %08x=%02x in FM_ERASEAMD2\n", address, data & 0xff );
935 }
936 break;
937 case FM_ERASEAMD3:
938 if( (( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x10 ) ||
939 (( address & 0xfff ) == 0xaaa && ( data & 0xff ) == 0x10 ) )
940 {
941 // chip erase
942 if (m_maker_id == MFG_FUJITSU && m_device_id == 0x40)
943 {
944 // hardcoded for Dreamcast, TODO properly handle sector protection
945 memset(&m_data[0], 0xff, 0x3A000);
946 memset(&m_data[0x3C000], 0xff, 0x04000);
947 }
948 else
949 memset(&m_data[0], 0xff, m_size);
950
951 m_status = 1 << 3;
952 m_flash_mode = FM_ERASEAMD4;
953
954 if (m_sector_is_4k)
955 {
956 m_timer->adjust( attotime::from_seconds( 1 ) );
957 }
958 else if(m_sector_is_16k)
959 {
960 m_timer->adjust( attotime::from_seconds( 4 ) );
961 }
962 else
963 {
964 m_timer->adjust( attotime::from_seconds( 16 ) );
965 }
966 }
967 else if( ( data & 0xff ) == 0x30 )
968 {
969 // sector erase
970 // clear the 4k/64k block containing the current address to all 0xffs
971 uint32_t base = address * ((m_bits == 16) ? 2 : 1);
972 if (m_sector_is_4k)
973 {
974 memset(&m_data[base & ~0xfff], 0xff, 4 * 1024);
975 m_erase_sector = address & ((m_bits == 16) ? ~0x7ff : ~0xfff);
976 m_timer->adjust( attotime::from_msec( 125 ) );
977 }
978 else if(m_sector_is_16k)
979 {
980 memset(&m_data[base & ~0x3fff], 0xff, 16 * 1024);
981 m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
982 m_timer->adjust( attotime::from_msec( 500 ) );
983 }
984 else if(m_top_boot_sector && address >= (m_size - 64*1024))
985 {
986 if (address >= (m_size - (16*1024)))
987 {
988 memset(&m_data[base & ~0x3fff], 0xff, 16 * 1024);
989 m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
990 m_timer->adjust( attotime::from_msec( 500 ) );
991 }
992 else if (address >= (m_size - (32*1024)))
993 {
994 memset(&m_data[base & ~0x1fff], 0xff, 8 * 1024);
995 m_erase_sector = address & ((m_bits == 16) ? ~0xfff : ~0x1fff);
996 m_timer->adjust( attotime::from_msec( 250 ) );
997 }
998 else
999 {
1000 memset(&m_data[base & ~0x7fff], 0xff, 32 * 1024);
1001 m_erase_sector = address & ((m_bits == 16) ? ~0x3fff : ~0x7fff);
1002 m_timer->adjust( attotime::from_msec( 500 ) );
1003 }
1004 }
1005 else if(m_bot_boot_sector && address < (64*1024))
1006 {
1007 if (address < (16*1024))
1008 {
1009 memset(&m_data[base & ~0x3fff], 0xff, 16 * 1024);
1010 m_erase_sector = address & ((m_bits == 16) ? ~0x1fff : ~0x3fff);
1011 m_timer->adjust( attotime::from_msec( 500 ) );
1012 }
1013 else if (address < (32*1024))
1014 {
1015 memset(&m_data[base & ~0x1fff], 0xff, 8 * 1024);
1016 m_erase_sector = address & ((m_bits == 16) ? ~0xfff : ~0x1fff);
1017 m_timer->adjust( attotime::from_msec( 250 ) );
1018 }
1019 else
1020 {
1021 memset(&m_data[base & ~0x7fff], 0xff, 32 * 1024);
1022 m_erase_sector = address & ((m_bits == 16) ? ~0x3fff : ~0x7fff);
1023 m_timer->adjust( attotime::from_msec( 500 ) );
1024 }
1025 }
1026 else if (m_maker_id == MFG_FUJITSU && m_device_id == 0x40)
1027 {
1028 constexpr u32 sectors[] = { 0x10000, 0x10000, 0x10000, 0x08000, 0x02000, 0x02000, 0x4000 };
1029
1030 u32 sec_num = 0;
1031 u32 toffset = base;
1032 while (toffset >= sectors[sec_num])
1033 toffset -= sectors[sec_num++];
1034 u32 sec_len = sectors[sec_num];
1035
1036 if (sec_num != 5) // hardcoded for Dreamcast, TODO properly handle sector protection
1037 {
1038 memset(&m_data[base & ~(sec_len - 1)], 0xff, sec_len);
1039 }
1040 m_erase_sector = address & ~(sec_len - 1);
1041 m_timer->adjust(attotime::from_seconds(1));
1042 }
1043 else
1044 {
1045 memset(&m_data[base & ~0xffff], 0xff, 64 * 1024);
1046 m_erase_sector = address & ((m_bits == 16) ? ~0x7fff : ~0xffff);
1047 m_timer->adjust( attotime::from_seconds( 1 ) );
1048 }
1049
1050 m_status = 1 << 3;
1051 m_flash_mode = FM_ERASEAMD4;
1052 }
1053 else
1054 {
1055 logerror( "unexpected %08x=%02x in FM_ERASEAMD3\n", address, data & 0xff );
1056 }
1057 break;
1058 case FM_BYTEPROGRAM:
1059 switch( m_bits )
1060 {
1061 case 8:
1062 if (m_maker_id == MFG_FUJITSU && m_device_id == 0x40)
1063 {
1064 if (address < 0x3a000 || address >= 0x3c000) // hardcoded for Dreamcast, TODO properly handle sector protection
1065 m_data[address] &= data;
1066 }
1067 else
1068 m_data[address] = data;
1069 break;
1070 case 16: // senbbs test mode requires this, note, flash type is guessed there based on manufacturer + device ident as markings were erased
1071 m_data[address*2] = data >> 8;
1072 m_data[address*2+1] = data;
1073 break;
1074 default:
1075 logerror( "FM_BYTEPROGRAM not supported when m_bits == %d (address %08x data %04x)\n", m_bits, address, data );
1076 break;
1077 }
1078 m_flash_mode = FM_NORMAL;
1079 break;
1080 case FM_WRITEPART1:
1081 switch( m_bits )
1082 {
1083 case 8:
1084 m_data[address] = data;
1085 break;
1086 case 16:
1087 m_data[address*2] = data >> 8;
1088 m_data[address*2+1] = data;
1089 break;
1090 default:
1091 logerror( "FM_WRITEPART1 not supported when m_bits == %d\n", m_bits );
1092 break;
1093 }
1094 m_status = 0x80;
1095 if (m_type == FLASH_SST_28SF040)
1096 m_flash_mode = FM_NORMAL;
1097 else
1098 m_flash_mode = FM_READSTATUS;
1099 break;
1100 case FM_WRITEPAGEATMEL:
1101 switch( m_bits )
1102 {
1103 case 8:
1104 m_data[address] = data;
1105 break;
1106 case 16:
1107 m_data[address*2] = data >> 8;
1108 m_data[address*2+1] = data;
1109 break;
1110 default:
1111 logerror( "FM_WRITEPAGEATMEL not supported when m_bits == %d\n", m_bits );
1112 break;
1113 }
1114
1115 m_byte_count++;
1116
1117 if (m_byte_count == m_page_size)
1118 {
1119 m_flash_mode = FM_NORMAL;
1120 }
1121 break;
1122 case FM_CLEARPART1:
1123 if( ( data & 0xff ) == 0xd0 )
1124 {
1125 if (m_type == FLASH_SST_28SF040)
1126 {
1127 // clear the 256 bytes block containing the current address to all 0xffs
1128 uint32_t base = address * ((m_bits == 16) ? 2 : 1);
1129 memset(&m_data[base & ~0xff], 0xff, 256);
1130
1131 m_timer->adjust( attotime::from_msec( 4 ) );
1132 }
1133 else if (m_type == FLASH_INTEL_E28F400B)
1134 {
1135 // 00000-03fff - 16KB boot block (may be write protected via external pins)
1136 // 04000-05fff - 8KB parameter block
1137 // 06000-07fff - 8KB parameter block
1138 // 08000-1ffff - 96KB main block
1139 // 20000-3ffff - 128KB main block
1140 // 40000-5ffff - 128KB main block
1141 // 60000-7ffff - 128KB main block
1142 // erase duration is 0.3s for boot and parameter blocks, and 0.6s for main blocks
1143 uint32_t base = (address & 0x3ffff) * 2;
1144 int size, duration;
1145 if (base < 0x4000)
1146 {
1147 base = 0;
1148 size = 0x4000;
1149 duration = 300;
1150 }
1151 else if (base < 0x8000)
1152 {
1153 base &= 0x6000;
1154 size = 0x2000;
1155 duration = 300;
1156 }
1157 else if (base < 0x20000)
1158 {
1159 base = 0x8000;
1160 size = 0x18000;
1161 duration = 600;
1162 }
1163 else
1164 {
1165 base &= 0x60000;
1166 size = 0x20000;
1167 duration = 600;
1168 }
1169
1170 // clear the block containing the current address to all 0xffffs
1171 memset(&m_data[base], 0xff, size);
1172
1173 m_timer->adjust( attotime::from_msec( duration ) );
1174 }
1175 else
1176 {
1177 // clear the 64k block containing the current address to all 0xffs
1178 uint32_t base = address * ((m_bits == 16) ? 2 : 1);
1179 memset(&m_data[base & ~0xffff], 0xff, 64 * 1024);
1180
1181 m_timer->adjust( attotime::from_seconds( 1 ) );
1182 }
1183
1184 m_status = 0x00;
1185 m_flash_mode = FM_READSTATUS;
1186 break;
1187 }
1188 else
1189 {
1190 logerror( "unexpected %02x in FM_CLEARPART1\n", data & 0xff );
1191 }
1192 break;
1193 case FM_SETMASTER:
1194 switch( data & 0xff )
1195 {
1196 case 0xf1:
1197 m_flash_master_lock = true;
1198 break;
1199 case 0xd0:
1200 m_flash_master_lock = false;
1201 break;
1202 default:
1203 logerror( "unexpected %08x=%02x in FM_SETMASTER:\n", address, data & 0xff );
1204 break;
1205 }
1206 m_flash_mode = FM_NORMAL;
1207 break;
1208 case FM_BANKSELECT:
1209 m_bank = data & 0xff;
1210 m_flash_mode = FM_NORMAL;
1211 break;
1212 }
1213 }
1214