1 // license:BSD-3-Clause 2 // copyright-holders:Tim Schuerewegen 3 /******************************************************************************* 4 5 Samsung S3C2410 6 7 *******************************************************************************/ 8 9 #ifndef MAME_MACHINE_S3C2410_H 10 #define MAME_MACHINE_S3C2410_H 11 12 #pragma once 13 14 #include "s3c24xx.h" 15 #include "emupal.h" 16 17 18 enum 19 { 20 S3C2410_GPIO_PORT_A = 0, 21 S3C2410_GPIO_PORT_B, 22 S3C2410_GPIO_PORT_C, 23 S3C2410_GPIO_PORT_D, 24 S3C2410_GPIO_PORT_E, 25 S3C2410_GPIO_PORT_F, 26 S3C2410_GPIO_PORT_G, 27 S3C2410_GPIO_PORT_H 28 }; 29 30 enum 31 { 32 S3C2410_CORE_PIN_NCON = 0, 33 S3C2410_CORE_PIN_OM0, 34 S3C2410_CORE_PIN_OM1 35 }; 36 37 38 /******************************************************************************* 39 MACROS & CONSTANTS 40 *******************************************************************************/ 41 42 /* Interface */ 43 44 #define S3C24XX_INTERFACE_LCD_REVERSE 1 45 46 /* Memory Controller */ 47 48 #define S3C24XX_BASE_MEMCON 0x48000000 49 50 /* USB Host Controller */ 51 52 #define S3C24XX_BASE_USBHOST 0x49000000 53 54 /* Interrupt Controller */ 55 56 #define S3C24XX_BASE_INT 0x4A000000 57 58 /* DMA */ 59 60 #define S3C24XX_BASE_DMA_0 0x4B000000 61 #define S3C24XX_BASE_DMA_1 0x4B000040 62 #define S3C24XX_BASE_DMA_2 0x4B000080 63 #define S3C24XX_BASE_DMA_3 0x4B0000C0 64 65 /* Clock & Power Management */ 66 67 #define S3C24XX_BASE_CLKPOW 0x4C000000 68 69 #define S3C24XX_LOCKTIME (0x00 / 4) // PLL Lock Time Counter 70 #define S3C24XX_MPLLCON (0x04 / 4) // MPLL Control 71 #define S3C24XX_UPLLCON (0x08 / 4) // UPLL Control 72 #define S3C24XX_CLKCON (0x0C / 4) // Clock Generator Control 73 #define S3C24XX_CLKSLOW (0x10 / 4) // Slow Clock Control 74 #define S3C24XX_CLKDIVN (0x14 / 4) // Clock Divider Control 75 76 /* LCD Controller */ 77 78 #define S3C24XX_BASE_LCD 0x4D000000 79 #define S3C24XX_BASE_LCDPAL 0x4D000400 80 81 /* NAND Flash */ 82 83 #define S3C24XX_BASE_NAND 0x4E000000 84 85 /* UART */ 86 87 #define S3C24XX_BASE_UART_0 0x50000000 88 #define S3C24XX_BASE_UART_1 0x50004000 89 #define S3C24XX_BASE_UART_2 0x50008000 90 91 /* PWM Timer */ 92 93 #define S3C24XX_BASE_PWM 0x51000000 94 95 /* USB Device */ 96 97 #define S3C24XX_BASE_USBDEV 0x52000140 98 99 /* Watchdog Timer */ 100 101 #define S3C24XX_BASE_WDT 0x53000000 102 103 /* IIC */ 104 105 #define S3C24XX_BASE_IIC 0x54000000 106 107 /* IIS */ 108 109 #define S3C24XX_BASE_IIS 0x55000000 110 111 /* I/O Port */ 112 113 #define S3C24XX_BASE_GPIO 0x56000000 114 115 /* RTC */ 116 117 #define S3C24XX_BASE_RTC 0x57000040 118 119 /* A/D Converter */ 120 121 #define S3C24XX_BASE_ADC 0x58000000 122 123 /* SPI */ 124 125 #define S3C24XX_BASE_SPI_0 0x59000000 126 #define S3C24XX_BASE_SPI_1 0x59000020 127 128 /* SD Interface */ 129 130 #define S3C24XX_BASE_SDI 0x5A000000 131 132 /* ... */ 133 134 class s3c2410_device : public device_t, protected s3c24xx_peripheral_types 135 { 136 public: 137 s3c2410_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 138 ~s3c2410_device(); 139 140 // configuration set_palette_tag(T && tag)141 template <typename T> void set_palette_tag(T &&tag) { m_palette.set_tag(std::forward<T>(tag)); } set_screen_tag(T && tag)142 template <typename T> void set_screen_tag(T &&tag) { m_screen.set_tag(std::forward<T>(tag)); } core_pin_r_callback()143 auto core_pin_r_callback() { return m_pin_r_cb.bind(); } core_pin_w_callback()144 auto core_pin_w_callback() { return m_pin_w_cb.bind(); } gpio_port_r_callback()145 auto gpio_port_r_callback() { return m_port_r_cb.bind(); } gpio_port_w_callback()146 auto gpio_port_w_callback() { return m_port_w_cb.bind(); } i2c_scl_w_callback()147 auto i2c_scl_w_callback() { return m_scl_w_cb.bind(); } i2c_sda_r_callback()148 auto i2c_sda_r_callback() { return m_sda_r_cb.bind(); } i2c_sda_w_callback()149 auto i2c_sda_w_callback() { return m_sda_w_cb.bind(); } adc_data_r_callback()150 auto adc_data_r_callback() { return m_data_r_cb.bind(); } i2s_data_w_callback()151 auto i2s_data_w_callback() { return m_data_w_cb.bind(); } nand_command_w_callback()152 auto nand_command_w_callback() { return m_command_w_cb.bind(); } nand_address_w_callback()153 auto nand_address_w_callback() { return m_address_w_cb.bind(); } nand_data_r_callback()154 auto nand_data_r_callback() { return m_nand_data_r_cb.bind(); } nand_data_w_callback()155 auto nand_data_w_callback() { return m_nand_data_w_cb.bind(); } set_lcd_flags(int flags)156 void set_lcd_flags(int flags) { m_flags = flags; } 157 158 DECLARE_WRITE_LINE_MEMBER( frnb_w ); 159 160 uint32_t s3c24xx_lcd_r(offs_t offset, uint32_t mem_mask = ~0); 161 162 uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 163 164 void s3c2410_touch_screen(int state); 165 void s3c2410_request_eint(uint32_t number); 166 void s3c2410_nand_calculate_mecc(uint8_t *data, uint32_t size, uint8_t *mecc); 167 168 protected: 169 // device-level overrides 170 virtual void device_start() override; 171 virtual void device_reset() override; 172 173 void s3c24xx_reset(); 174 inline int iface_core_pin_r(int pin); 175 void s3c24xx_lcd_reset(); 176 rgb_t s3c24xx_get_color_tft_16(uint16_t data); 177 rgb_t s3c24xx_get_color_tft_24(uint32_t data); 178 rgb_t s3c24xx_get_color_stn_12(uint16_t data); 179 rgb_t s3c24xx_get_color_stn_08( uint8_t data); 180 rgb_t s3c24xx_get_color_stn_01(uint8_t data); 181 rgb_t s3c24xx_get_color_stn_02(uint8_t data); 182 rgb_t s3c24xx_get_color_stn_04(uint8_t data); 183 rgb_t s3c24xx_get_color_tpal(); 184 void s3c24xx_lcd_dma_reload(); 185 void s3c24xx_lcd_dma_init(); 186 uint32_t s3c24xx_lcd_dma_read(); 187 uint32_t s3c24xx_lcd_dma_read_bits(int count); 188 void s3c24xx_lcd_render_tpal(); 189 void s3c24xx_lcd_render_stn_01(); 190 void s3c24xx_lcd_render_stn_02(); 191 void s3c24xx_lcd_render_stn_04(); 192 void s3c24xx_lcd_render_stn_08(); 193 void s3c24xx_lcd_render_stn_12_p(); 194 void s3c24xx_lcd_render_stn_12_u(); // not tested 195 void s3c24xx_lcd_render_tft_01(); 196 void s3c24xx_lcd_render_tft_02(); 197 void s3c24xx_lcd_render_tft_04(); 198 void s3c24xx_lcd_render_tft_08(); 199 void s3c24xx_lcd_render_tft_16(); 200 TIMER_CALLBACK_MEMBER( s3c24xx_lcd_timer_exp ); 201 void s3c24xx_video_start(); 202 void bitmap_blend( bitmap_rgb32 &bitmap_dst, bitmap_rgb32 &bitmap_src_1, bitmap_rgb32 &bitmap_src_2); 203 uint32_t s3c24xx_video_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 204 int s3c24xx_lcd_configure_tft(); 205 int s3c24xx_lcd_configure_stn(); 206 int s3c24xx_lcd_configure(); 207 void s3c24xx_lcd_start(); 208 void s3c24xx_lcd_stop(); 209 void s3c24xx_lcd_recalc(); 210 void s3c24xx_lcd_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 211 uint32_t s3c24xx_lcd_palette_r(offs_t offset, uint32_t mem_mask = ~0); 212 void s3c24xx_lcd_palette_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 213 void s3c24xx_clkpow_reset(); 214 uint32_t s3c24xx_get_fclk(); 215 uint32_t s3c24xx_get_hclk(); 216 uint32_t s3c24xx_get_pclk(); 217 uint32_t s3c24xx_clkpow_r(offs_t offset, uint32_t mem_mask = ~0); 218 void s3c24xx_clkpow_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 219 void s3c24xx_irq_reset(); 220 void s3c24xx_check_pending_irq(); 221 void s3c24xx_request_irq(uint32_t int_type); 222 void s3c24xx_check_pending_subirq(); 223 void s3c24xx_request_subirq( uint32_t int_type); 224 void s3c24xx_check_pending_eint(); 225 void s3c24xx_request_eint(uint32_t number); 226 uint32_t s3c24xx_irq_r(offs_t offset, uint32_t mem_mask = ~0); 227 void s3c24xx_irq_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 228 uint32_t s3c24xx_pwm_r(offs_t offset, uint32_t mem_mask = ~0); 229 void s3c24xx_pwm_start(int timer); 230 void s3c24xx_pwm_stop(int timer); 231 void s3c24xx_pwm_recalc(int timer); 232 void s3c24xx_pwm_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 233 TIMER_CALLBACK_MEMBER( s3c24xx_pwm_timer_exp ); 234 void s3c24xx_dma_reset(); 235 void s3c24xx_dma_reload(int ch); 236 void s3c24xx_dma_trigger(int ch); 237 void s3c24xx_dma_request_iis(); 238 void s3c24xx_dma_request_pwm(); 239 void s3c24xx_dma_start(int ch); 240 void s3c24xx_dma_stop(int ch); 241 void s3c24xx_dma_recalc(int ch); 242 uint32_t s3c24xx_dma_r(uint32_t ch, uint32_t offset); 243 void s3c24xx_dma_w(uint32_t ch, uint32_t offset, uint32_t data, uint32_t mem_mask); 244 uint32_t s3c24xx_dma_0_r(offs_t offset, uint32_t mem_mask = ~0); 245 uint32_t s3c24xx_dma_1_r(offs_t offset, uint32_t mem_mask = ~0); 246 uint32_t s3c24xx_dma_2_r(offs_t offset, uint32_t mem_mask = ~0); 247 uint32_t s3c24xx_dma_3_r(offs_t offset, uint32_t mem_mask = ~0); 248 void s3c24xx_dma_0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 249 void s3c24xx_dma_1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 250 void s3c24xx_dma_2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 251 void s3c24xx_dma_3_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 252 TIMER_CALLBACK_MEMBER( s3c24xx_dma_timer_exp ); 253 void s3c24xx_gpio_reset(); 254 inline uint32_t iface_gpio_port_r(int port, uint32_t mask); 255 inline void iface_gpio_port_w(int port, uint32_t mask, uint32_t data); 256 uint16_t s3c24xx_gpio_get_mask( uint32_t con, int val); 257 uint32_t s3c24xx_gpio_r(offs_t offset, uint32_t mem_mask = ~0); 258 void s3c24xx_gpio_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 259 uint32_t s3c24xx_memcon_r(offs_t offset, uint32_t mem_mask = ~0); 260 void s3c24xx_memcon_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 261 uint32_t s3c24xx_usb_host_r(offs_t offset, uint32_t mem_mask = ~0); 262 void s3c24xx_usb_host_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 263 uint32_t s3c24xx_uart_r(uint32_t ch, uint32_t offset); 264 void s3c24xx_uart_w(uint32_t ch, uint32_t offset, uint32_t data, uint32_t mem_mask); 265 uint32_t s3c24xx_uart_0_r(offs_t offset, uint32_t mem_mask = ~0); 266 uint32_t s3c24xx_uart_1_r(offs_t offset, uint32_t mem_mask = ~0); 267 uint32_t s3c24xx_uart_2_r(offs_t offset, uint32_t mem_mask = ~0); 268 void s3c24xx_uart_0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 269 void s3c24xx_uart_1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 270 void s3c24xx_uart_2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 271 void s3c24xx_uart_fifo_w(int uart, uint8_t data); 272 void s3c24xx_usb_device_reset(); 273 uint32_t s3c24xx_usb_device_r(offs_t offset, uint32_t mem_mask = ~0); 274 void s3c24xx_usb_device_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 275 uint32_t s3c24xx_wdt_r(offs_t offset, uint32_t mem_mask = ~0); 276 void s3c24xx_wdt_start(); 277 void s3c24xx_wdt_stop(); 278 void s3c24xx_wdt_recalc(); 279 void s3c24xx_wdt_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 280 TIMER_CALLBACK_MEMBER( s3c24xx_wdt_timer_exp ); 281 void s3c24xx_iic_reset(); 282 inline void iface_i2c_scl_w( int state); 283 inline void iface_i2c_sda_w(int state); 284 inline int iface_i2c_sda_r(); 285 void i2c_send_start(); 286 void i2c_send_stop(); 287 uint8_t i2c_receive_byte(int ack); 288 int i2c_send_byte(uint8_t data); 289 void iic_start(); 290 void iic_stop(); 291 void iic_resume(); 292 uint32_t s3c24xx_iic_r(offs_t offset, uint32_t mem_mask = ~0); 293 void s3c24xx_iic_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 294 TIMER_CALLBACK_MEMBER( s3c24xx_iic_timer_exp ); 295 inline void iface_i2s_data_w(int ch, uint16_t data); 296 void s3c24xx_iis_start(); 297 void s3c24xx_iis_stop(); 298 void s3c24xx_iis_recalc(); 299 uint32_t s3c24xx_iis_r(offs_t offset, uint32_t mem_mask = ~0); 300 void s3c24xx_iis_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 301 TIMER_CALLBACK_MEMBER( s3c24xx_iis_timer_exp ); 302 uint32_t s3c24xx_rtc_r(offs_t offset, uint32_t mem_mask = ~0); 303 void s3c24xx_rtc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 304 TIMER_CALLBACK_MEMBER( s3c24xx_rtc_timer_tick_count_exp ); 305 void s3c24xx_rtc_update(); 306 void s3c24xx_rtc_check_alarm(); 307 TIMER_CALLBACK_MEMBER( s3c24xx_rtc_timer_update_exp ); 308 void s3c24xx_adc_reset(); 309 uint32_t iface_adc_data_r(int ch); 310 uint32_t s3c24xx_adc_r(offs_t offset, uint32_t mem_mask = ~0); 311 void s3c24xx_adc_start(); 312 void s3c24xx_adc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 313 void s3c24xx_touch_screen(int state); 314 void s3c24xx_spi_reset(); 315 uint32_t s3c24xx_spi_r(uint32_t ch, uint32_t offset); 316 void s3c24xx_spi_w(uint32_t ch, uint32_t offset, uint32_t data, uint32_t mem_mask); 317 uint32_t s3c24xx_spi_0_r(offs_t offset, uint32_t mem_mask = ~0); 318 uint32_t s3c24xx_spi_1_r(offs_t offset, uint32_t mem_mask = ~0); 319 void s3c24xx_spi_0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 320 void s3c24xx_spi_1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 321 void s3c24xx_sdi_reset(); 322 uint32_t s3c24xx_sdi_r(offs_t offset, uint32_t mem_mask = ~0); 323 void s3c24xx_sdi_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 324 void s3c24xx_nand_reset(); 325 inline void iface_nand_command_w(uint8_t data); 326 inline void iface_nand_address_w(uint8_t data); 327 inline uint8_t iface_nand_data_r(); 328 inline void iface_nand_data_w(uint8_t data); 329 void nand_update_mecc( uint8_t *ecc, int pos, uint8_t data); 330 void s3c24xx_nand_update_ecc(uint8_t data); 331 void s3c24xx_nand_command_w(uint8_t data); 332 void s3c24xx_nand_address_w(uint8_t data); 333 uint8_t s3c24xx_nand_data_r(); 334 void s3c24xx_nand_data_w(uint8_t data); 335 uint32_t s3c24xx_nand_r(offs_t offset, uint32_t mem_mask = ~0); 336 void s3c24xx_nand_init_ecc(); 337 void s3c24xx_nand_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); 338 ATTR_UNUSED WRITE_LINE_MEMBER( s3c24xx_pin_frnb_w ); 339 void s3c24xx_nand_auto_boot(); 340 void s3c24xx_device_reset(); 341 void s3c24xx_device_start(); 342 343 void s3c2410_uart_fifo_w( int uart, uint8_t data); 344 345 private: 346 static constexpr unsigned UART_COUNT = 3; 347 static constexpr unsigned DMA_COUNT = 4; 348 static constexpr unsigned SPI_COUNT = 2; 349 350 /******************************************************************************* 351 TYPE DEFINITIONS 352 *******************************************************************************/ 353 354 struct irq_regs_t 355 { 356 uint32_t srcpnd; 357 uint32_t intmod; 358 uint32_t intmsk; 359 uint32_t priority; 360 uint32_t intpnd; 361 uint32_t intoffset; 362 uint32_t subsrcpnd; 363 uint32_t intsubmsk; 364 }; 365 366 struct dma_regs_t 367 { 368 uint32_t disrc; 369 uint32_t disrcc; 370 uint32_t didst; 371 uint32_t didstc; 372 uint32_t dcon; 373 uint32_t dstat; 374 uint32_t dcsrc; 375 uint32_t dcdst; 376 uint32_t dmasktrig; 377 }; 378 379 struct clkpow_regs_t 380 { 381 uint32_t locktime; 382 uint32_t mpllcon; 383 uint32_t upllcon; 384 uint32_t clkcon; 385 uint32_t clkslow; 386 uint32_t clkdivn; 387 }; 388 389 struct lcd_regs_t 390 { 391 uint32_t lcdcon1; 392 uint32_t lcdcon2; 393 uint32_t lcdcon3; 394 uint32_t lcdcon4; 395 uint32_t lcdcon5; 396 uint32_t lcdsaddr1; 397 uint32_t lcdsaddr2; 398 uint32_t lcdsaddr3; 399 uint32_t redlut; 400 uint32_t greenlut; 401 uint32_t bluelut; 402 uint32_t reserved[8]; 403 uint32_t dithmode; 404 uint32_t tpal; 405 uint32_t lcdintpnd; 406 uint32_t lcdsrcpnd; 407 uint32_t lcdintmsk; 408 uint32_t lpcsel; 409 }; 410 411 struct nand_regs_t 412 { 413 uint32_t nfconf; 414 uint32_t nfcmd; 415 uint32_t nfaddr; 416 uint32_t nfdata; 417 uint32_t nfstat; 418 uint32_t nfecc; 419 }; 420 421 struct usbdev_regs_t 422 { 423 uint32_t data[0x130/4]; 424 }; 425 426 struct iic_regs_t 427 { 428 uint32_t iiccon; 429 uint32_t iicstat; 430 uint32_t iicadd; 431 uint32_t iicds; 432 }; 433 434 struct gpio_regs_t 435 { 436 uint32_t gpacon; 437 uint32_t gpadat; 438 uint32_t pad_08; 439 uint32_t pad_0c; 440 uint32_t gpbcon; 441 uint32_t gpbdat; 442 uint32_t gpbup; 443 uint32_t pad_1c; 444 uint32_t gpccon; 445 uint32_t gpcdat; 446 uint32_t gpcup; 447 uint32_t pad_2c; 448 uint32_t gpdcon; 449 uint32_t gpddat; 450 uint32_t gpdup; 451 uint32_t pad_3c; 452 uint32_t gpecon; 453 uint32_t gpedat; 454 uint32_t gpeup; 455 uint32_t pad_4c; 456 uint32_t gpfcon; 457 uint32_t gpfdat; 458 uint32_t gpfup; 459 uint32_t pad_5c; 460 uint32_t gpgcon; 461 uint32_t gpgdat; 462 uint32_t gpgup; 463 uint32_t pad_6c; 464 uint32_t gphcon; 465 uint32_t gphdat; 466 uint32_t gphup; 467 uint32_t pad_7c; 468 uint32_t misccr; 469 uint32_t dclkcon; 470 uint32_t extint0; 471 uint32_t extint1; 472 uint32_t extint2; 473 uint32_t eintflt0; 474 uint32_t eintflt1; 475 uint32_t eintflt2; 476 uint32_t eintflt3; 477 uint32_t eintmask; 478 uint32_t eintpend; 479 uint32_t gstatus0; 480 uint32_t gstatus1; 481 uint32_t gstatus2; 482 uint32_t gstatus3; 483 uint32_t gstatus4; 484 }; 485 486 struct adc_regs_t 487 { 488 uint32_t adccon; 489 uint32_t adctsc; 490 uint32_t adcdly; 491 uint32_t adcdat0; 492 uint32_t adcdat1; 493 }; 494 495 496 struct irq_t 497 { 498 irq_regs_t regs; 499 int line_irq, line_fiq; 500 }; 501 502 struct dma_t 503 { 504 dma_regs_t regs; 505 emu_timer *timer; 506 }; 507 508 struct clkpow_t 509 { 510 clkpow_regs_t regs; 511 }; 512 513 struct lcd_t 514 { 515 lcd_regs_t regs; 516 emu_timer *timer; 517 std::unique_ptr<bitmap_rgb32> bitmap[2]; 518 uint32_t vramaddr_cur; 519 uint32_t vramaddr_max; 520 uint32_t offsize; 521 uint32_t pagewidth_cur; 522 uint32_t pagewidth_max; 523 uint32_t bppmode; 524 uint32_t bswp, hwswp; 525 int vpos, hpos; 526 double framerate; 527 uint32_t tpal; 528 uint32_t hpos_min, hpos_max, vpos_min, vpos_max; 529 uint32_t dma_data, dma_bits; 530 }; 531 532 struct nand_t 533 { 534 nand_regs_t regs; 535 uint8_t mecc[3]; 536 int ecc_pos, data_count; 537 }; 538 539 struct usbdev_t 540 { 541 usbdev_regs_t regs; 542 }; 543 544 struct iic_t 545 { 546 iic_regs_t regs; 547 emu_timer *timer; 548 int count; 549 }; 550 551 struct gpio_t 552 { 553 gpio_regs_t regs; 554 }; 555 556 struct adc_t 557 { 558 adc_regs_t regs; 559 }; 560 561 // internal state 562 required_device<arm7_cpu_device> m_cpu; 563 required_device<palette_device> m_palette; 564 required_device<screen_device> m_screen; 565 memory_access<24, 2, 0, ENDIANNESS_LITTLE>::cache m_cache; 566 567 uint8_t m_steppingstone[4*1024]; 568 memcon_t m_memcon; 569 usbhost_t m_usbhost; 570 irq_t m_irq; 571 dma_t m_dma[DMA_COUNT]; 572 clkpow_t m_clkpow; 573 lcd_t m_lcd; 574 lcdpal_t m_lcdpal; 575 nand_t m_nand; 576 uart_t m_uart[UART_COUNT]; 577 pwm_t m_pwm; 578 usbdev_t m_usbdev; 579 wdt_t m_wdt; 580 iic_t m_iic; 581 iis_t m_iis; 582 gpio_t m_gpio; 583 rtc_t m_rtc; 584 adc_t m_adc; 585 spi_t m_spi[SPI_COUNT]; 586 devcb_read32 m_pin_r_cb; 587 devcb_write32 m_pin_w_cb; 588 devcb_read32 m_port_r_cb; 589 devcb_write32 m_port_w_cb; 590 devcb_write_line m_scl_w_cb; 591 devcb_read_line m_sda_r_cb; 592 devcb_write_line m_sda_w_cb; 593 devcb_read32 m_data_r_cb; 594 devcb_write16 m_data_w_cb; 595 devcb_write8 m_command_w_cb; 596 devcb_write8 m_address_w_cb; 597 devcb_read8 m_nand_data_r_cb; 598 devcb_write8 m_nand_data_w_cb; 599 int m_flags; 600 601 sdi_t m_sdi; 602 }; 603 604 DECLARE_DEVICE_TYPE(S3C2410, s3c2410_device) 605 606 #endif // MAME_MACHINE_S3C2410_H 607