1 // license:BSD-3-Clause 2 // copyright-holders:Ryan Holtz 3 /************************************************************* 4 5 Texas Instruments TSB12LV01A/TSB12LV01AI IEEE 1394-1995 6 High-Speed Serial-Bus Link-Layer Controller 7 8 Skeleton device 9 10 **************************************************************/ 11 12 #ifndef MAME_MACHINE_TSB12LV01A_H 13 #define MAME_MACHINE_TSB12LV01A_H 14 15 #pragma once 16 17 class tsb12lv01a_device : public device_t 18 { 19 public: 20 tsb12lv01a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 21 22 uint32_t read(offs_t offset); 23 void write(offs_t offset, uint32_t data, uint32_t mem_mask); 24 int_cb()25 auto int_cb() { return m_int_cb.bind(); } phy_read()26 auto phy_read() { return m_phy_read_cb.bind(); } phy_write()27 auto phy_write() { return m_phy_write_cb.bind(); } 28 29 DECLARE_WRITE_LINE_MEMBER(phy_reset_w); 30 31 private: 32 // device-level overrides 33 virtual void device_start() override; 34 virtual void device_reset() override; 35 36 void set_interrupt(uint32_t bit); 37 void check_interrupts(); 38 39 void reset_tx(); 40 void reset_rx(); 41 42 void clear_atf(); 43 void clear_itf(); 44 void clear_grf(); 45 46 enum 47 { 48 NODE_ADDR_BUSNUM_SHIFT = 22, 49 NODE_ADDR_BUSNUM_MASK = 0xffc00000, 50 NODE_ADDR_NODENUM_SHIFT = 16, 51 NODE_ADDR_NODENUM_MASK = 0x003f0000, 52 NODE_ADDR_ROOT = 0x8000, 53 NODE_ADDR_ATACK_SHIFT = 4, 54 NODE_ADDR_ATACK_MASK = 0x000001f0, 55 NODE_ADDR_ACKV = 0x00000001, 56 57 CTRL_IDVAL = 0x80000000, 58 CTRL_RXSID = 0x40000000, 59 CTRL_BSYCTRL = 0x20000000, 60 CTRL_RAI = 0x10000000, 61 CTRL_RCVCYST = 0x08000000, 62 CTRL_TXAEN = 0x04000000, 63 CTRL_RXAEN = 0x02000000, 64 CTRL_TXIEN = 0x01000000, 65 CTRL_RXIEN = 0x00800000, 66 CTRL_ACKCEN = 0x00400000, 67 CTRL_RSTTX = 0x00200000, 68 CTRL_RSTRX = 0x00100000, 69 CTRL_CYMAS = 0x00000800, 70 CTRL_CYSRC = 0x00000400, 71 CTRL_CYTEN = 0x00000200, 72 CTRL_TRGEN = 0x00000100, 73 CTRL_IRP1EN = 0x00000080, 74 CTRL_IRP2EN = 0x00000040, 75 CTRL_FHBAD = 0x00000001, 76 CTRL_RW_BITS = CTRL_IDVAL | CTRL_RXSID | CTRL_BSYCTRL | CTRL_RAI | CTRL_RCVCYST | 77 CTRL_TXAEN | CTRL_RXAEN | CTRL_TXIEN | CTRL_RXIEN | CTRL_ACKCEN | 78 CTRL_CYMAS | CTRL_CYSRC | CTRL_CYTEN | CTRL_TRGEN | CTRL_IRP1EN | 79 CTRL_IRP2EN | CTRL_FHBAD, 80 81 INT_INT = 0x80000000, 82 INT_PHINT = 0x40000000, 83 INT_PHYRRX = 0x20000000, 84 INT_PHRST = 0x10000000, 85 INT_SIDCOMP = 0x08000000, 86 INT_TXRDY = 0x04000000, 87 INT_RXDTA = 0x02000000, 88 INT_CMDRST = 0x01000000, 89 INT_ACKRCV = 0x00800000, 90 INT_ITBADF = 0x00100000, 91 INT_ATBADF = 0x00080000, 92 INT_SNTRJ = 0x00020000, 93 INT_HDRDR = 0x00010000, 94 INT_TCERR = 0x00008000, 95 INT_CYTMOUT = 0x00001000, 96 INT_CYSEC = 0x00000800, 97 INT_CYST = 0x00000400, 98 INT_CYDNE = 0x00000200, 99 INT_CYPND = 0x00000100, 100 INT_CYLST = 0x00000080, 101 INT_CARBFL = 0x00000040, 102 INT_ARBGP = 0x00000004, 103 INT_FRGP = 0x00000002, 104 INT_IARBFL = 0x00000001, 105 106 CYTMR_SEC_COUNT_SHIFT = 25, 107 CYTMR_SEC_COUNT_MASK = 0xfe000000, 108 CYTMR_CYC_COUNT_SHIFT = 12, 109 CYTMR_CYC_COUNT_MASK = 0x01fff000, 110 CYTMR_CYC_OFFSET_SHIFT = 0, 111 CYTMR_CYC_OFFSET_MASK = 0x00000fff, 112 113 ISOCH_PORT_TAG_SHIFT = 30, 114 ISOCH_PORT_TAG_MASK = 0xc0000000, 115 ISOCH_PORT_IRPORT1_SHIFT = 24, 116 ISOCH_PORT_IRPORT1_MASK = 0x3f000000, 117 ISOCH_PORT_TAG2_SHIFT = 22, 118 ISOCH_PORT_TAG2_MASK = 0x00c00000, 119 ISOCH_PORT_IRPORT2_SHIFT = 16, 120 ISOCH_PORT_IRPORT2_MASK = 0x003f0000, 121 ISOCH_PORT_MON_TAG = 0x00000001, 122 123 FIFO_CTRL_CLRATF = 0x80000000, 124 FIFO_CTRL_CLRITF = 0x40000000, 125 FIFO_CTRL_CLRGRF = 0x20000000, 126 FIFO_CTRL_TRIG_SIZE_SHIFT = 18, 127 FIFO_CTRL_TRIG_SIZE_MASK = 0x07fc0000, 128 FIFO_CTRL_ATF_SIZE_SHIFT = 9, 129 FIFO_CTRL_ATF_SIZE_MASK = 0x0003fe00, 130 FIFO_CTRL_ITF_SIZE_SHIFT = 0, 131 FIFO_CTRL_ITF_SIZE_MASK = 0x000001ff, 132 FIFO_CTRL_RW_BITS = (FIFO_CTRL_TRIG_SIZE_MASK | FIFO_CTRL_ATF_SIZE_MASK | FIFO_CTRL_ITF_SIZE_MASK), 133 134 PHY_RDPHY = 0x80000000, 135 PHY_WRPHY = 0x40000000, 136 PHY_PHYRGAD_SHIFT = 24, 137 PHY_PHYRGAD_MASK = 0x0f000000, 138 PHY_PHYRGDATA_SHIFT = 16, 139 PHY_PHYRGDATA_MASK = 0x00ff0000, 140 PHY_PHYRXAD_SHIFT = 8, 141 PHY_PHYRXAD_MASK = 0x00000f00, 142 PHY_PHYRXDATA_SHIFT = 0, 143 PHY_PHYRXDATA_MASK = 0x000000ff, 144 PHY_RW_BITS = 0x0fff0fff, 145 146 ATF_STATUS_FULL = 0x80000000, 147 ATF_STATUS_EMPTY = 0x40000000, 148 ATF_STATUS_CONERR = 0x20000000, 149 ATF_STATUS_ADRCLR = 0x10000000, 150 ATF_STATUS_CONTROL = 0x08000000, 151 ATF_STATUS_RAMTEST = 0x04000000, 152 ATF_STATUS_ADRCOUNTER_SHIFT = 17, 153 ATF_STATUS_ADRCOUNTER_MASK = 0x03fe0000, 154 ATF_STATUS_ATFSPACE_SHIFT = 0, 155 ATF_STATUS_ATFSPACE_MASK = 0x000001ff, 156 157 ITF_STATUS_FULL = 0x80000000, 158 ITF_STATUS_EMPTY = 0x40000000, 159 ITF_STATUS_ITFSPACE_SHIFT = 0, 160 ITF_STATUS_ITFSPACE_MASK = 0x000001ff, 161 162 GRF_STATUS_EMPTY = 0x80000000, 163 GRF_STATUS_CD = 0x40000000, 164 GRF_STATUS_PACCOM = 0x20000000, 165 GRF_STATUS_GRFTOTAL_SHIFT = 19, 166 GRF_STATUS_GRFTOTAL_MASK = 0x1ff80000, 167 GRF_STATUS_GRFSIZE_SHIFT = 9, 168 GRF_STATUS_GRFSIZE_MASK = 0x0007fe00, 169 GRF_STATUS_WRITECOUNT_SHIFT = 0, 170 GRF_STATUS_WRITECOUNT_MASK = 0x000001ff 171 }; 172 173 uint32_t m_version; 174 uint32_t m_node_address; 175 uint32_t m_ctrl; 176 uint32_t m_int_status; 177 uint32_t m_int_mask; 178 uint32_t m_cycle_timer; 179 uint32_t m_isoch_port_num; 180 uint32_t m_fifo_ctrl; 181 uint32_t m_diag_ctrl; 182 uint32_t m_phy_access; 183 uint32_t m_atf_status; 184 uint32_t m_itf_status; 185 uint32_t m_grf_status; 186 187 devcb_write_line m_int_cb; 188 devcb_read8 m_phy_read_cb; 189 devcb_write8 m_phy_write_cb; 190 }; 191 192 //device type definition 193 DECLARE_DEVICE_TYPE(TSB12LV01A, tsb12lv01a_device) 194 195 #endif // MAME_MACHINE_TSB12LV01A_H 196