1 // license:GPL-2.0+
2 // copyright-holders:Jarek Burczynski,Tatsuyuki Satoh
3 /*
4 **
5 ** File: fmopl.c - software implementation of FM sound generator
6 ** types OPL and OPL2
7 **
8 ** Copyright Jarek Burczynski (bujar at mame dot net)
9 ** Copyright Tatsuyuki Satoh , MultiArcadeMachineEmulator development
10 **
11 ** Version 0.72
12 **
13
14 Revision History:
15
16 04-08-2003 Jarek Burczynski:
17 - removed BFRDY hack. BFRDY is busy flag, and it should be 0 only when the chip
18 handles memory read/write or during the adpcm synthesis when the chip
19 requests another byte of ADPCM data.
20
21 24-07-2003 Jarek Burczynski:
22 - added a small hack for Y8950 status BFRDY flag (bit 3 should be set after
23 some (unknown) delay). Right now it's always set.
24
25 14-06-2003 Jarek Burczynski:
26 - implemented all of the status register flags in Y8950 emulation
27 - renamed y8950_set_delta_t_memory() parameters from _rom_ to _mem_ since
28 they can be either RAM or ROM
29
30 08-10-2002 Jarek Burczynski (thanks to Dox for the YM3526 chip)
31 - corrected ym3526_read() to always set bit 2 and bit 1
32 to HIGH state - identical to ym3812_read (verified on real YM3526)
33
34 04-28-2002 Jarek Burczynski:
35 - binary exact Envelope Generator (verified on real YM3812);
36 compared to YM2151: the EG clock is equal to internal_clock,
37 rates are 2 times slower and volume resolution is one bit less
38 - modified interface functions (they no longer return pointer -
39 that's internal to the emulator now):
40 - new wrapper functions for OPLCreate: ym3526_init(), ym3812_init() and y8950_init()
41 - corrected 'off by one' error in feedback calculations (when feedback is off)
42 - enabled waveform usage (credit goes to Vlad Romascanu and zazzal22)
43 - speeded up noise generator calculations (Nicola Salmoria)
44
45 03-24-2002 Jarek Burczynski (thanks to Dox for the YM3812 chip)
46 Complete rewrite (all verified on real YM3812):
47 - corrected sin_tab and tl_tab data
48 - corrected operator output calculations
49 - corrected waveform_select_enable register;
50 simply: ignore all writes to waveform_select register when
51 waveform_select_enable == 0 and do not change the waveform previously selected.
52 - corrected KSR handling
53 - corrected Envelope Generator: attack shape, Sustain mode and
54 Percussive/Non-percussive modes handling
55 - Envelope Generator rates are two times slower now
56 - LFO amplitude (tremolo) and phase modulation (vibrato)
57 - rhythm sounds phase generation
58 - white noise generator (big thanks to Olivier Galibert for mentioning Berlekamp-Massey algorithm)
59 - corrected key on/off handling (the 'key' signal is ORed from three sources: FM, rhythm and CSM)
60 - funky details (like ignoring output of operator 1 in BD rhythm sound when connect == 1)
61
62 12-28-2001 Acho A. Tang
63 - reflected Delta-T EOS status on Y8950 status port.
64 - fixed subscription range of attack/decay tables
65
66
67 To do:
68 add delay before key off in CSM mode (see CSMKeyControll)
69 verify volume of the FM part on the Y8950
70 */
71
72 #include "emu.h"
73 #include "fmopl.h"
74 #include "ymdeltat.h"
75
76
77
78 /* output final shift */
79 #if (OPL_SAMPLE_BITS==16)
80 #define FINAL_SH (0)
81 #define MAXOUT (+32767)
82 #define MINOUT (-32768)
83 #else
84 #define FINAL_SH (8)
85 #define MAXOUT (+127)
86 #define MINOUT (-128)
87 #endif
88
89
90 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
91 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
92 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
93 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
94
95 #define FREQ_MASK ((1<<FREQ_SH)-1)
96
97 /* envelope output entries */
98 #define ENV_BITS 10
99 #define ENV_LEN (1<<ENV_BITS)
100 #define ENV_STEP (128.0/ENV_LEN)
101
102 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
103 #define MIN_ATT_INDEX (0)
104
105 /* sinwave entries */
106 #define SIN_BITS 10
107 #define SIN_LEN (1<<SIN_BITS)
108 #define SIN_MASK (SIN_LEN-1)
109
110 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
111
112
113
114 /* register number to channel number , slot offset */
115 #define SLOT1 0
116 #define SLOT2 1
117
118 /* Envelope Generator phases */
119
120 #define EG_ATT 4
121 #define EG_DEC 3
122 #define EG_SUS 2
123 #define EG_REL 1
124 #define EG_OFF 0
125
126
127 /* save output as raw 16-bit sample */
128
129 /*#define SAVE_SAMPLE*/
130
131 #ifdef SAVE_SAMPLE
acc_calc(signed int value)132 static inline signed int acc_calc(signed int value)
133 {
134 if (value>=0)
135 {
136 if (value < 0x0200)
137 return (value & ~0);
138 if (value < 0x0400)
139 return (value & ~1);
140 if (value < 0x0800)
141 return (value & ~3);
142 if (value < 0x1000)
143 return (value & ~7);
144 if (value < 0x2000)
145 return (value & ~15);
146 if (value < 0x4000)
147 return (value & ~31);
148 return (value & ~63);
149 }
150 /*else value < 0*/
151 if (value > -0x0200)
152 return (~abs(value) & ~0);
153 if (value > -0x0400)
154 return (~abs(value) & ~1);
155 if (value > -0x0800)
156 return (~abs(value) & ~3);
157 if (value > -0x1000)
158 return (~abs(value) & ~7);
159 if (value > -0x2000)
160 return (~abs(value) & ~15);
161 if (value > -0x4000)
162 return (~abs(value) & ~31);
163 return (~abs(value) & ~63);
164 }
165
166
167 static FILE *sample[1];
168 #if 1 /*save to MONO file */
169 #define SAVE_ALL_CHANNELS \
170 { signed int pom = acc_calc(lt); \
171 fputc((unsigned short)pom&0xff,sample[0]); \
172 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
173 }
174 #else /*save to STEREO file */
175 #define SAVE_ALL_CHANNELS \
176 { signed int pom = lt; \
177 fputc((unsigned short)pom&0xff,sample[0]); \
178 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
179 pom = rt; \
180 fputc((unsigned short)pom&0xff,sample[0]); \
181 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
182 }
183 #endif
184 #endif
185
186 #define OPL_TYPE_WAVESEL 0x01 /* waveform select */
187 #define OPL_TYPE_ADPCM 0x02 /* DELTA-T ADPCM unit */
188 #define OPL_TYPE_KEYBOARD 0x04 /* keyboard interface */
189 #define OPL_TYPE_IO 0x08 /* I/O port */
190
191 /* ---------- Generic interface section ---------- */
192 #define OPL_TYPE_YM3526 (0)
193 #define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL)
194 #define OPL_TYPE_Y8950 (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO)
195
196
197 namespace {
198
199 // TODO: make these static members
200
201 #define RATE_STEPS (8)
202 extern const unsigned char eg_rate_shift[16+64+16];
203 extern const unsigned char eg_rate_select[16+64+16];
204
205
206 struct OPL_SLOT
207 {
208 uint32_t ar; /* attack rate: AR<<2 */
209 uint32_t dr; /* decay rate: DR<<2 */
210 uint32_t rr; /* release rate:RR<<2 */
211 uint8_t KSR; /* key scale rate */
212 uint8_t ksl; /* keyscale level */
213 uint8_t ksr; /* key scale rate: kcode>>KSR */
214 uint8_t mul; /* multiple: mul_tab[ML] */
215
216 /* Phase Generator */
217 uint32_t Cnt; /* frequency counter */
218 uint32_t Incr; /* frequency counter step */
219 uint8_t FB; /* feedback shift value */
220 int32_t *connect1; /* slot1 output pointer */
221 int32_t op1_out[2]; /* slot1 output for feedback */
222 uint8_t CON; /* connection (algorithm) type */
223
224 /* Envelope Generator */
225 uint8_t eg_type; /* percussive/non-percussive mode */
226 uint8_t state; /* phase type */
227 uint32_t TL; /* total level: TL << 2 */
228 int32_t TLL; /* adjusted now TL */
229 int32_t volume; /* envelope counter */
230 uint32_t sl; /* sustain level: sl_tab[SL] */
231 uint8_t eg_sh_ar; /* (attack state) */
232 uint8_t eg_sel_ar; /* (attack state) */
233 uint8_t eg_sh_dr; /* (decay state) */
234 uint8_t eg_sel_dr; /* (decay state) */
235 uint8_t eg_sh_rr; /* (release state) */
236 uint8_t eg_sel_rr; /* (release state) */
237 uint32_t key; /* 0 = KEY OFF, >0 = KEY ON */
238
239 /* LFO */
240 uint32_t AMmask; /* LFO Amplitude Modulation enable mask */
241 uint8_t vib; /* LFO Phase Modulation enable flag (active high)*/
242
243 /* waveform select */
244 uint16_t wavetable;
245
KEYON__anon012e80b20111::OPL_SLOT246 void KEYON(uint32_t key_set)
247 {
248 if( !key )
249 {
250 /* restart Phase Generator */
251 Cnt = 0;
252 /* phase -> Attack */
253 state = EG_ATT;
254 }
255 key |= key_set;
256 }
257
KEYOFF__anon012e80b20111::OPL_SLOT258 void KEYOFF(uint32_t key_clr)
259 {
260 if( key )
261 {
262 key &= key_clr;
263
264 if( !key )
265 {
266 /* phase -> Release */
267 if (state>EG_REL)
268 state = EG_REL;
269 }
270 }
271 }
272 };
273
274 struct OPL_CH
275 {
276 OPL_SLOT SLOT[2];
277 /* phase generator state */
278 uint32_t block_fnum; /* block+fnum */
279 uint32_t fc; /* Freq. Increment base */
280 uint32_t ksl_base; /* KeyScaleLevel Base step */
281 uint8_t kcode; /* key code (for key scaling) */
282
283
284 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT__anon012e80b20111::OPL_CH285 void CALC_FCSLOT(OPL_SLOT &SLOT)
286 {
287 /* (frequency) phase increment counter */
288 SLOT.Incr = fc * SLOT.mul;
289 int const ksr = kcode >> SLOT.KSR;
290
291 if( SLOT.ksr != ksr )
292 {
293 SLOT.ksr = ksr;
294
295 /* calculate envelope generator rates */
296 if ((SLOT.ar + SLOT.ksr) < 16+62)
297 {
298 SLOT.eg_sh_ar = eg_rate_shift [SLOT.ar + SLOT.ksr ];
299 SLOT.eg_sel_ar = eg_rate_select[SLOT.ar + SLOT.ksr ];
300 }
301 else
302 {
303 SLOT.eg_sh_ar = 0;
304 SLOT.eg_sel_ar = 13*RATE_STEPS;
305 }
306 SLOT.eg_sh_dr = eg_rate_shift [SLOT.dr + SLOT.ksr ];
307 SLOT.eg_sel_dr = eg_rate_select[SLOT.dr + SLOT.ksr ];
308 SLOT.eg_sh_rr = eg_rate_shift [SLOT.rr + SLOT.ksr ];
309 SLOT.eg_sel_rr = eg_rate_select[SLOT.rr + SLOT.ksr ];
310 }
311 }
312
313 /* CSM Key Control */
CSMKeyControll__anon012e80b20111::OPL_CH314 void CSMKeyControll()
315 {
316 SLOT[SLOT1].KEYON(4);
317 SLOT[SLOT2].KEYON(4);
318
319 /* The key off should happen exactly one sample later - not implemented correctly yet */
320
321 SLOT[SLOT1].KEYOFF(~4);
322 SLOT[SLOT2].KEYOFF(~4);
323 }
324 };
325
326 /* OPL state */
327 class FM_OPL
328 {
329 protected:
FM_OPL()330 FM_OPL()
331 #if BUILD_Y8950
332 : deltat(nullptr, [] (YM_DELTAT *p) { p->~YM_DELTAT(); })
333 #endif
334 {
335 }
336
337 public:
~FM_OPL()338 ~FM_OPL()
339 {
340 UnLockTable();
341 }
342
343 /* FM channel slots */
344 OPL_CH P_CH[9]; /* OPL/OPL2 chips have 9 channels*/
345
346 uint32_t eg_cnt; /* global envelope generator counter */
347 uint32_t eg_timer; /* global envelope generator counter works at frequency = chipclock/72 */
348 uint32_t eg_timer_add; /* step of eg_timer */
349 uint32_t eg_timer_overflow; /* envelope generator timer overflows every 1 sample (on real chip) */
350
351 uint8_t rhythm; /* Rhythm mode */
352
353 uint32_t fn_tab[1024]; /* fnumber->increment counter */
354
355 /* LFO */
356 uint32_t LFO_AM;
357 int32_t LFO_PM;
358
359 uint8_t lfo_am_depth;
360 uint8_t lfo_pm_depth_range;
361 uint32_t lfo_am_cnt;
362 uint32_t lfo_am_inc;
363 uint32_t lfo_pm_cnt;
364 uint32_t lfo_pm_inc;
365
366 uint32_t noise_rng; /* 23 bit noise shift register */
367 uint32_t noise_p; /* current noise 'phase' */
368 uint32_t noise_f; /* current noise period */
369
370 uint8_t wavesel; /* waveform select enable flag */
371
372 uint32_t T[2]; /* timer counters */
373 uint8_t st[2]; /* timer enable */
374
375 #if BUILD_Y8950
376 /* Delta-T ADPCM unit (Y8950) */
377
378 std::unique_ptr<YM_DELTAT, void (*)(YM_DELTAT *)> deltat;
379
380 /* Keyboard and I/O ports interface */
381 uint8_t portDirection;
382 uint8_t portLatch;
383 OPL_PORTHANDLER_R porthandler_r;
384 OPL_PORTHANDLER_W porthandler_w;
385 device_t * port_param;
386 OPL_PORTHANDLER_R keyboardhandler_r;
387 OPL_PORTHANDLER_W keyboardhandler_w;
388 device_t * keyboard_param;
389 #endif
390
391 /* external event callback handlers */
392 OPL_TIMERHANDLER timer_handler; /* TIMER handler */
393 device_t *TimerParam; /* TIMER parameter */
394 OPL_IRQHANDLER IRQHandler; /* IRQ handler */
395 device_t *IRQParam; /* IRQ parameter */
396 OPL_UPDATEHANDLER UpdateHandler;/* stream update handler */
397 device_t *UpdateParam; /* stream update parameter */
398
399 uint8_t type; /* chip type */
400 uint8_t address; /* address register */
401 uint8_t status; /* status flag */
402 uint8_t statusmask; /* status mask */
403 uint8_t mode; /* Reg.08 : CSM,notesel,etc. */
404
405 uint32_t clock; /* master clock (Hz) */
406 uint32_t rate; /* sampling rate (Hz) */
407 double freqbase; /* frequency base */
408 attotime TimerBase; /* Timer base time (==sampling time)*/
409 device_t *device;
410
411 signed int phase_modulation; /* phase modulation input (SLOT 2) */
412 signed int output[1];
413 #if BUILD_Y8950
414 int32_t output_deltat[4]; /* for Y8950 DELTA-T, chip is mono, that 4 here is just for safety */
415 #endif
416
417
418 /* status set and IRQ handling */
STATUS_SET(int flag)419 void STATUS_SET(int flag)
420 {
421 /* set status flag */
422 status |= flag;
423 if(!(status & 0x80))
424 {
425 if(status & statusmask)
426 { /* IRQ on */
427 status |= 0x80;
428 /* callback user interrupt handler (IRQ is OFF to ON) */
429 if(IRQHandler) (IRQHandler)(IRQParam,1);
430 }
431 }
432 }
433
434 /* status reset and IRQ handling */
STATUS_RESET(int flag)435 void STATUS_RESET(int flag)
436 {
437 /* reset status flag */
438 status &=~flag;
439 if(status & 0x80)
440 {
441 if (!(status & statusmask) )
442 {
443 status &= 0x7f;
444 /* callback user interrupt handler (IRQ is ON to OFF) */
445 if(IRQHandler) (IRQHandler)(IRQParam,0);
446 }
447 }
448 }
449
450 /* IRQ mask set */
STATUSMASK_SET(int flag)451 void STATUSMASK_SET(int flag)
452 {
453 statusmask = flag;
454 /* IRQ handling check */
455 STATUS_SET(0);
456 STATUS_RESET(0);
457 }
458
459
460 /* advance LFO to next sample */
advance_lfo()461 void advance_lfo()
462 {
463 /* LFO */
464 lfo_am_cnt += lfo_am_inc;
465 if (lfo_am_cnt >= (uint32_t(LFO_AM_TAB_ELEMENTS) << LFO_SH)) /* lfo_am_table is 210 elements long */
466 lfo_am_cnt -= (uint32_t(LFO_AM_TAB_ELEMENTS) << LFO_SH);
467
468 uint8_t const tmp = lfo_am_table[ lfo_am_cnt >> LFO_SH ];
469
470 LFO_AM = lfo_am_depth ? tmp : tmp >> 2;
471
472 lfo_pm_cnt += lfo_pm_inc;
473 LFO_PM = (lfo_pm_cnt>>LFO_SH & 7) | lfo_pm_depth_range;
474 }
475
476 /* advance to next sample */
advance()477 void advance()
478 {
479 eg_timer += eg_timer_add;
480
481 while (eg_timer >= eg_timer_overflow)
482 {
483 eg_timer -= eg_timer_overflow;
484
485 eg_cnt++;
486
487 for (int i=0; i<9*2; i++)
488 {
489 OPL_CH &CH = P_CH[i/2];
490 OPL_SLOT &op = CH.SLOT[i&1];
491
492 /* Envelope Generator */
493 switch(op.state)
494 {
495 case EG_ATT: /* attack phase */
496 if ( !(eg_cnt & ((1<<op.eg_sh_ar)-1) ) )
497 {
498 op.volume += (~op.volume *
499 (eg_inc[op.eg_sel_ar + ((eg_cnt>>op.eg_sh_ar)&7)])
500 ) >>3;
501
502 if (op.volume <= MIN_ATT_INDEX)
503 {
504 op.volume = MIN_ATT_INDEX;
505 op.state = EG_DEC;
506 }
507
508 }
509 break;
510
511 case EG_DEC: /* decay phase */
512 if ( !(eg_cnt & ((1<<op.eg_sh_dr)-1) ) )
513 {
514 op.volume += eg_inc[op.eg_sel_dr + ((eg_cnt>>op.eg_sh_dr)&7)];
515
516 if ( op.volume >= op.sl )
517 op.state = EG_SUS;
518
519 }
520 break;
521
522 case EG_SUS: /* sustain phase */
523
524 /* this is important behaviour:
525 one can change percusive/non-percussive modes on the fly and
526 the chip will remain in sustain phase - verified on real YM3812 */
527
528 if(op.eg_type) /* non-percussive mode */
529 {
530 /* do nothing */
531 }
532 else /* percussive mode */
533 {
534 /* during sustain phase chip adds Release Rate (in percussive mode) */
535 if ( !(eg_cnt & ((1<<op.eg_sh_rr)-1) ) )
536 {
537 op.volume += eg_inc[op.eg_sel_rr + ((eg_cnt>>op.eg_sh_rr)&7)];
538
539 if ( op.volume >= MAX_ATT_INDEX )
540 op.volume = MAX_ATT_INDEX;
541 }
542 /* else do nothing in sustain phase */
543 }
544 break;
545
546 case EG_REL: /* release phase */
547 if ( !(eg_cnt & ((1<<op.eg_sh_rr)-1) ) )
548 {
549 op.volume += eg_inc[op.eg_sel_rr + ((eg_cnt>>op.eg_sh_rr)&7)];
550
551 if ( op.volume >= MAX_ATT_INDEX )
552 {
553 op.volume = MAX_ATT_INDEX;
554 op.state = EG_OFF;
555 }
556
557 }
558 break;
559
560 default:
561 break;
562 }
563 }
564 }
565
566 for (int i=0; i<9*2; i++)
567 {
568 OPL_CH &CH = P_CH[i/2];
569 OPL_SLOT &op = CH.SLOT[i&1];
570
571 /* Phase Generator */
572 if(op.vib)
573 {
574 unsigned int block_fnum = CH.block_fnum;
575 unsigned int const fnum_lfo = (block_fnum&0x0380) >> 7;
576
577 signed int const lfo_fn_table_index_offset = lfo_pm_table[LFO_PM + 16*fnum_lfo ];
578
579 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
580 {
581 block_fnum += lfo_fn_table_index_offset;
582 uint8_t const block = (block_fnum&0x1c00) >> 10;
583 op.Cnt += (fn_tab[block_fnum&0x03ff] >> (7-block)) * op.mul;
584 }
585 else /* LFO phase modulation = zero */
586 {
587 op.Cnt += op.Incr;
588 }
589 }
590 else /* LFO phase modulation disabled for this operator */
591 {
592 op.Cnt += op.Incr;
593 }
594 }
595
596 /* The Noise Generator of the YM3812 is 23-bit shift register.
597 * Period is equal to 2^23-2 samples.
598 * Register works at sampling frequency of the chip, so output
599 * can change on every sample.
600 *
601 * Output of the register and input to the bit 22 is:
602 * bit0 XOR bit14 XOR bit15 XOR bit22
603 *
604 * Simply use bit 22 as the noise output.
605 */
606
607 noise_p += noise_f;
608 int i = noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
609 noise_p &= FREQ_MASK;
610 while (i)
611 {
612 /*
613 uint32_t j;
614 j = ( (noise_rng) ^ (noise_rng>>14) ^ (noise_rng>>15) ^ (noise_rng>>22) ) & 1;
615 noise_rng = (j<<22) | (noise_rng>>1);
616 */
617
618 /*
619 Instead of doing all the logic operations above, we
620 use a trick here (and use bit 0 as the noise output).
621 The difference is only that the noise bit changes one
622 step ahead. This doesn't matter since we don't know
623 what is real state of the noise_rng after the reset.
624 */
625
626 if (noise_rng & 1) noise_rng ^= 0x800302;
627 noise_rng >>= 1;
628
629 i--;
630 }
631 }
632
633 /* calculate output */
CALC_CH(OPL_CH & CH)634 void CALC_CH(OPL_CH &CH)
635 {
636 OPL_SLOT *SLOT;
637 unsigned int env;
638 signed int out;
639
640 phase_modulation = 0;
641
642 /* SLOT 1 */
643 SLOT = &CH.SLOT[SLOT1];
644 env = volume_calc(*SLOT);
645 out = SLOT->op1_out[0] + SLOT->op1_out[1];
646 SLOT->op1_out[0] = SLOT->op1_out[1];
647 *SLOT->connect1 += SLOT->op1_out[0];
648 SLOT->op1_out[1] = 0;
649 if( env < ENV_QUIET )
650 {
651 if (!SLOT->FB)
652 out = 0;
653 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
654 }
655
656 /* SLOT 2 */
657 SLOT++;
658 env = volume_calc(*SLOT);
659 if( env < ENV_QUIET )
660 output[0] += op_calc(SLOT->Cnt, env, phase_modulation, SLOT->wavetable);
661 }
662
663 /*
664 operators used in the rhythm sounds generation process:
665
666 Envelope Generator:
667
668 channel operator register number Bass High Snare Tom Top
669 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
670 6 / 0 12 50 70 90 f0 +
671 6 / 1 15 53 73 93 f3 +
672 7 / 0 13 51 71 91 f1 +
673 7 / 1 16 54 74 94 f4 +
674 8 / 0 14 52 72 92 f2 +
675 8 / 1 17 55 75 95 f5 +
676
677 Phase Generator:
678
679 channel operator register number Bass High Snare Tom Top
680 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
681 6 / 0 12 30 +
682 6 / 1 15 33 +
683 7 / 0 13 31 + + +
684 7 / 1 16 34 ----- n o t u s e d -----
685 8 / 0 14 32 +
686 8 / 1 17 35 + +
687
688 channel operator register number Bass High Snare Tom Top
689 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
690 6 12,15 B6 A6 +
691
692 7 13,16 B7 A7 + + +
693
694 8 14,17 B8 A8 + + +
695
696 */
697
698 /* calculate rhythm */
699
CALC_RH()700 void CALC_RH()
701 {
702 unsigned int const noise = BIT(noise_rng, 0);
703
704 OPL_SLOT *SLOT;
705 signed int out;
706 unsigned int env;
707
708
709 /* Bass Drum (verified on real YM3812):
710 - depends on the channel 6 'connect' register:
711 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
712 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
713 - output sample always is multiplied by 2
714 */
715
716 phase_modulation = 0;
717 /* SLOT 1 */
718 SLOT = &P_CH[6].SLOT[SLOT1];
719 env = volume_calc(*SLOT);
720
721 out = SLOT->op1_out[0] + SLOT->op1_out[1];
722 SLOT->op1_out[0] = SLOT->op1_out[1];
723
724 if (!SLOT->CON)
725 phase_modulation = SLOT->op1_out[0];
726 /* else ignore output of operator 1 */
727
728 SLOT->op1_out[1] = 0;
729 if( env < ENV_QUIET )
730 {
731 if (!SLOT->FB)
732 out = 0;
733 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
734 }
735
736 /* SLOT 2 */
737 SLOT++;
738 env = volume_calc(*SLOT);
739 if( env < ENV_QUIET )
740 output[0] += op_calc(SLOT->Cnt, env, phase_modulation, SLOT->wavetable) * 2;
741
742
743 /* Phase generation is based on: */
744 /* HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases) */
745 /* SD (16) channel 7->slot 1 */
746 /* TOM (14) channel 8->slot 1 */
747 /* TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases) */
748
749 /* Envelope generation based on: */
750 /* HH channel 7->slot1 */
751 /* SD channel 7->slot2 */
752 /* TOM channel 8->slot1 */
753 /* TOP channel 8->slot2 */
754
755
756 /* The following formulas can be well optimized.
757 I leave them in direct form for now (in case I've missed something).
758 */
759
760 /* High Hat (verified on real YM3812) */
761 OPL_SLOT const &SLOT7_1 = P_CH[7].SLOT[SLOT1];
762 OPL_SLOT const &SLOT8_2 = P_CH[8].SLOT[SLOT2];
763 env = volume_calc(SLOT7_1);
764 if( env < ENV_QUIET )
765 {
766 /* high hat phase generation:
767 phase = d0 or 234 (based on frequency only)
768 phase = 34 or 2d0 (based on noise)
769 */
770
771 /* base frequency derived from operator 1 in channel 7 */
772 unsigned char const bit7 = BIT(SLOT7_1.Cnt >> FREQ_SH, 7);
773 unsigned char const bit3 = BIT(SLOT7_1.Cnt >> FREQ_SH, 3);
774 unsigned char const bit2 = BIT(SLOT7_1.Cnt >> FREQ_SH, 2);
775
776 unsigned char const res1 = (bit2 ^ bit7) | bit3;
777
778 /* when res1 = 0 phase = 0x000 | 0xd0; */
779 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
780 uint32_t phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
781
782 /* enable gate based on frequency of operator 2 in channel 8 */
783 unsigned char const bit5e= BIT(SLOT8_2.Cnt >> FREQ_SH, 5);
784 unsigned char const bit3e= BIT(SLOT8_2.Cnt >> FREQ_SH, 3);
785
786 unsigned char const res2 = bit3e ^ bit5e;
787
788 /* when res2 = 0 pass the phase from calculation above (res1); */
789 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
790 if (res2)
791 phase = (0x200|(0xd0>>2));
792
793
794 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
795 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
796 if (phase&0x200)
797 {
798 if (noise)
799 phase = 0x200|0xd0;
800 }
801 else
802 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
803 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
804 {
805 if (noise)
806 phase = 0xd0>>2;
807 }
808
809 output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1.wavetable) * 2;
810 }
811
812 /* Snare Drum (verified on real YM3812) */
813 OPL_SLOT const &SLOT7_2 = P_CH[7].SLOT[SLOT2];
814 env = volume_calc(SLOT7_2);
815 if( env < ENV_QUIET )
816 {
817 /* base frequency derived from operator 1 in channel 7 */
818 unsigned char const bit8 = BIT(SLOT7_1.Cnt >> FREQ_SH, 8);
819
820 /* when bit8 = 0 phase = 0x100; */
821 /* when bit8 = 1 phase = 0x200; */
822 uint32_t phase = bit8 ? 0x200 : 0x100;
823
824 /* Noise bit XOR'es phase by 0x100 */
825 /* when noisebit = 0 pass the phase from calculation above */
826 /* when noisebit = 1 phase ^= 0x100; */
827 /* in other words: phase ^= (noisebit<<8); */
828 if (noise)
829 phase ^= 0x100;
830
831 output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2.wavetable) * 2;
832 }
833
834 /* Tom Tom (verified on real YM3812) */
835 OPL_SLOT const &SLOT8_1 = P_CH[8].SLOT[SLOT1];
836 env = volume_calc(SLOT8_1);
837 if( env < ENV_QUIET )
838 output[0] += op_calc(SLOT8_1.Cnt, env, 0, SLOT8_1.wavetable) * 2;
839
840 /* Top Cymbal (verified on real YM3812) */
841 env = volume_calc(SLOT8_2);
842 if( env < ENV_QUIET )
843 {
844 /* base frequency derived from operator 1 in channel 7 */
845 unsigned char const bit7 = BIT(SLOT7_1.Cnt >> FREQ_SH, 7);
846 unsigned char const bit3 = BIT(SLOT7_1.Cnt >> FREQ_SH, 3);
847 unsigned char const bit2 = BIT(SLOT7_1.Cnt >> FREQ_SH, 2);
848
849 unsigned char const res1 = (bit2 ^ bit7) | bit3;
850
851 /* when res1 = 0 phase = 0x000 | 0x100; */
852 /* when res1 = 1 phase = 0x200 | 0x100; */
853 uint32_t phase = res1 ? 0x300 : 0x100;
854
855 /* enable gate based on frequency of operator 2 in channel 8 */
856 unsigned char const bit5e= BIT(SLOT8_2.Cnt >> FREQ_SH, 5);
857 unsigned char const bit3e= BIT(SLOT8_2.Cnt >> FREQ_SH, 3);
858
859 unsigned char const res2 = bit3e ^ bit5e;
860 /* when res2 = 0 pass the phase from calculation above (res1); */
861 /* when res2 = 1 phase = 0x200 | 0x100; */
862 if (res2)
863 phase = 0x300;
864
865 output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2.wavetable) * 2;
866 }
867 }
868
869
870 void initialize();
871
872
873 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(int slot,int v)874 void set_mul(int slot, int v)
875 {
876 OPL_CH &CH = P_CH[slot/2];
877 OPL_SLOT &SLOT = CH.SLOT[slot&1];
878
879 SLOT.mul = mul_tab[v&0x0f];
880 SLOT.KSR = (v & 0x10) ? 0 : 2;
881 SLOT.eg_type = (v & 0x20);
882 SLOT.vib = (v & 0x40);
883 SLOT.AMmask = (v & 0x80) ? ~0 : 0;
884 CH.CALC_FCSLOT(SLOT);
885 }
886
887 /* set ksl & tl */
set_ksl_tl(int slot,int v)888 void set_ksl_tl(int slot, int v)
889 {
890 OPL_CH &CH = P_CH[slot/2];
891 OPL_SLOT &SLOT = CH.SLOT[slot&1];
892
893 SLOT.ksl = ksl_shift[v >> 6];
894 SLOT.TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
895
896 SLOT.TLL = SLOT.TL + (CH.ksl_base >> SLOT.ksl);
897 }
898
899 /* set attack rate & decay rate */
set_ar_dr(int slot,int v)900 void set_ar_dr(int slot, int v)
901 {
902 OPL_CH &CH = P_CH[slot/2];
903 OPL_SLOT &SLOT = CH.SLOT[slot&1];
904
905 SLOT.ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
906
907 if ((SLOT.ar + SLOT.ksr) < 16+62)
908 {
909 SLOT.eg_sh_ar = eg_rate_shift [SLOT.ar + SLOT.ksr ];
910 SLOT.eg_sel_ar = eg_rate_select[SLOT.ar + SLOT.ksr ];
911 }
912 else
913 {
914 SLOT.eg_sh_ar = 0;
915 SLOT.eg_sel_ar = 13*RATE_STEPS;
916 }
917
918 SLOT.dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
919 SLOT.eg_sh_dr = eg_rate_shift [SLOT.dr + SLOT.ksr ];
920 SLOT.eg_sel_dr = eg_rate_select[SLOT.dr + SLOT.ksr ];
921 }
922
923 /* set sustain level & release rate */
set_sl_rr(int slot,int v)924 void set_sl_rr(int slot, int v)
925 {
926 OPL_CH &CH = P_CH[slot/2];
927 OPL_SLOT &SLOT = CH.SLOT[slot&1];
928
929 SLOT.sl = sl_tab[ v>>4 ];
930
931 SLOT.rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
932 SLOT.eg_sh_rr = eg_rate_shift [SLOT.rr + SLOT.ksr ];
933 SLOT.eg_sel_rr = eg_rate_select[SLOT.rr + SLOT.ksr ];
934 }
935
936
937 void ResetChip();
938 void postload();
939
clock_changed(uint32_t c,uint32_t r)940 void clock_changed(uint32_t c, uint32_t r)
941 {
942 clock = c;
943 rate = r;
944
945 /* init global tables */
946 initialize();
947 }
948
Write(int a,int v)949 int Write(int a, int v)
950 {
951 if( !(a&1) )
952 { /* address port */
953 address = v & 0xff;
954 }
955 else
956 { /* data port */
957 if (UpdateHandler) UpdateHandler(UpdateParam, 0);
958 WriteReg(address, v);
959 }
960 return status>>7;
961 }
962
Read(int a)963 unsigned char Read(int a)
964 {
965 if( !(a&1) )
966 {
967 /* status port */
968
969 #if BUILD_Y8950
970
971 if(type&OPL_TYPE_ADPCM) /* Y8950 */
972 {
973 return (status & (statusmask|0x80)) | (deltat->PCM_BSY&1);
974 }
975
976 #endif
977
978 /* OPL and OPL2 */
979 return status & (statusmask|0x80);
980 }
981
982 #if BUILD_Y8950
983 /* data port */
984 switch(address)
985 {
986 case 0x05: /* KeyBoard IN */
987 if(type&OPL_TYPE_KEYBOARD)
988 {
989 if(keyboardhandler_r)
990 return keyboardhandler_r(keyboard_param);
991 else
992 device->logerror("Y8950: read unmapped KEYBOARD port\n");
993 }
994 return 0;
995
996 case 0x0f: /* ADPCM-DATA */
997 if(type&OPL_TYPE_ADPCM)
998 {
999 uint8_t val;
1000
1001 val = deltat->ADPCM_Read();
1002 /*logerror("Y8950: read ADPCM value read=%02x\n",val);*/
1003 return val;
1004 }
1005 return 0;
1006
1007 case 0x19: /* I/O DATA */
1008 if(type&OPL_TYPE_IO)
1009 {
1010 if(porthandler_r)
1011 return porthandler_r(port_param);
1012 else
1013 device->logerror("Y8950:read unmapped I/O port\n");
1014 }
1015 return 0;
1016 case 0x1a: /* PCM-DATA */
1017 if(type&OPL_TYPE_ADPCM)
1018 {
1019 device->logerror("Y8950 A/D conversion is accessed but not implemented !\n");
1020 return 0x80; /* 2's complement PCM data - result from A/D conversion */
1021 }
1022 return 0;
1023 }
1024 #endif
1025
1026 return 0xff;
1027 }
1028
1029
TimerOver(int c)1030 int TimerOver(int c)
1031 {
1032 if( c )
1033 { /* Timer B */
1034 STATUS_SET(0x20);
1035 }
1036 else
1037 { /* Timer A */
1038 STATUS_SET(0x40);
1039 /* CSM mode key,TL controll */
1040 if( mode & 0x80 )
1041 { /* CSM mode total level latch and auto key on */
1042 int ch;
1043 if(UpdateHandler) UpdateHandler(UpdateParam,0);
1044 for(ch=0; ch<9; ch++)
1045 P_CH[ch].CSMKeyControll();
1046 }
1047 }
1048 /* reload timer */
1049 if (timer_handler) (timer_handler)(TimerParam,c,TimerBase * T[c]);
1050 return status>>7;
1051 }
1052
1053
1054 /* Create one of virtual YM3812/YM3526/Y8950 */
1055 /* 'clock' is chip clock in Hz */
1056 /* 'rate' is sampling rate */
Create(device_t * device,uint32_t clock,uint32_t rate,int type)1057 static FM_OPL *Create(device_t *device, uint32_t clock, uint32_t rate, int type)
1058 {
1059 if (LockTable(device) == -1)
1060 return nullptr;
1061
1062 /* calculate OPL state size */
1063 size_t state_size = sizeof(FM_OPL);
1064 #if BUILD_Y8950
1065 if (type & OPL_TYPE_ADPCM)
1066 state_size+= sizeof(YM_DELTAT);
1067 #endif
1068
1069 /* allocate memory block */
1070 char *ptr = reinterpret_cast<char *>(::operator new(state_size));
1071 std::fill_n(ptr, state_size, 0);
1072
1073 FM_OPL *const OPL = new(ptr) FM_OPL;
1074
1075 ptr += sizeof(FM_OPL);
1076
1077 #if BUILD_Y8950
1078 if (type & OPL_TYPE_ADPCM)
1079 {
1080 OPL->deltat.reset(reinterpret_cast<YM_DELTAT *>(ptr));
1081 ptr += sizeof(YM_DELTAT);
1082 }
1083 #endif
1084
1085 OPL->device = device;
1086 OPL->type = type;
1087 OPL->clock_changed(clock, rate);
1088
1089 return OPL;
1090 }
1091
1092
1093 /* Optional handlers */
1094
SetTimerHandler(OPL_TIMERHANDLER handler,device_t * device)1095 void SetTimerHandler(OPL_TIMERHANDLER handler, device_t *device)
1096 {
1097 timer_handler = handler;
1098 TimerParam = device;
1099 }
SetIRQHandler(OPL_IRQHANDLER handler,device_t * device)1100 void SetIRQHandler(OPL_IRQHANDLER handler, device_t *device)
1101 {
1102 IRQHandler = handler;
1103 IRQParam = device;
1104 }
SetUpdateHandler(OPL_UPDATEHANDLER handler,device_t * device)1105 void SetUpdateHandler(OPL_UPDATEHANDLER handler, device_t *device)
1106 {
1107 UpdateHandler = handler;
1108 UpdateParam = device;
1109 }
1110
1111 private:
1112 void WriteReg(int r, int v);
1113
volume_calc(OPL_SLOT const & OP) const1114 uint32_t volume_calc(OPL_SLOT const &OP) const
1115 {
1116 return OP.TLL + uint32_t(OP.volume) + (LFO_AM & OP.AMmask);
1117 }
1118
op_calc(uint32_t phase,unsigned int env,signed int pm,unsigned int wave_tab)1119 static inline signed int op_calc(uint32_t phase, unsigned int env, signed int pm, unsigned int wave_tab)
1120 {
1121 uint32_t const p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
1122
1123 return (p >= TL_TAB_LEN) ? 0 : tl_tab[p];
1124 }
1125
op_calc1(uint32_t phase,unsigned int env,signed int pm,unsigned int wave_tab)1126 static inline signed int op_calc1(uint32_t phase, unsigned int env, signed int pm, unsigned int wave_tab)
1127 {
1128 uint32_t const p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm )) >> FREQ_SH ) & SIN_MASK) ];
1129
1130 return (p >= TL_TAB_LEN) ? 0 : tl_tab[p];
1131 }
1132
1133
1134 /* lock/unlock for common table */
LockTable(device_t * device)1135 static int LockTable(device_t *device)
1136 {
1137 num_lock++;
1138 if(num_lock>1) return 0;
1139
1140 /* first time */
1141
1142 /* allocate total level table (128kb space) */
1143 if( !init_tables() )
1144 {
1145 num_lock--;
1146 return -1;
1147 }
1148
1149 return 0;
1150 }
1151
UnLockTable()1152 static void UnLockTable()
1153 {
1154 if(num_lock) num_lock--;
1155 if(num_lock) return;
1156
1157 /* last time */
1158 CloseTable();
1159 }
1160
1161 static int init_tables();
1162
CloseTable()1163 static void CloseTable()
1164 {
1165 #ifdef SAVE_SAMPLE
1166 fclose(sample[0]);
1167 #endif
1168 }
1169
1170
SC(uint32_t db)1171 static constexpr uint32_t SC(uint32_t db) { return uint32_t(db * (2.0 / ENV_STEP)); }
1172
1173
1174 static constexpr double DV = 0.1875 / 2.0;
1175
1176
1177 /* TL_TAB_LEN is calculated as:
1178 * 12 - sinus amplitude bits (Y axis)
1179 * 2 - sinus sign bit (Y axis)
1180 * TL_RES_LEN - sinus resolution (X axis)
1181 */
1182 static constexpr unsigned TL_TAB_LEN = 12 * 2 * TL_RES_LEN;
1183 static constexpr unsigned ENV_QUIET = TL_TAB_LEN >> 4;
1184
1185 static constexpr unsigned LFO_AM_TAB_ELEMENTS = 210;
1186
1187 static const double ksl_tab[8*16];
1188 static const uint32_t ksl_shift[4];
1189 static const uint32_t sl_tab[16];
1190 static const unsigned char eg_inc[15 * RATE_STEPS];
1191
1192 static const uint8_t mul_tab[16];
1193 static signed int tl_tab[TL_TAB_LEN];
1194 static unsigned int sin_tab[SIN_LEN * 4];
1195
1196 static const uint8_t lfo_am_table[LFO_AM_TAB_ELEMENTS];
1197 static const int8_t lfo_pm_table[8 * 8 * 2];
1198
1199 static int num_lock;
1200 };
1201
1202
1203
1204 /* mapping of register number (offset) to slot number used by the emulator */
1205 static const int slot_array[32]=
1206 {
1207 0, 2, 4, 1, 3, 5,-1,-1,
1208 6, 8,10, 7, 9,11,-1,-1,
1209 12,14,16,13,15,17,-1,-1,
1210 -1,-1,-1,-1,-1,-1,-1,-1
1211 };
1212
1213 /* key scale level */
1214 /* table is 3dB/octave , DV converts this into 6dB/octave */
1215 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
1216 const double FM_OPL::ksl_tab[8*16]=
1217 {
1218 /* OCT 0 */
1219 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1220 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1221 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1222 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1223 /* OCT 1 */
1224 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1225 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1226 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
1227 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
1228 /* OCT 2 */
1229 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
1230 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
1231 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
1232 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
1233 /* OCT 3 */
1234 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
1235 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
1236 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
1237 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
1238 /* OCT 4 */
1239 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
1240 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
1241 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
1242 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
1243 /* OCT 5 */
1244 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
1245 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
1246 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
1247 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
1248 /* OCT 6 */
1249 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
1250 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
1251 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
1252 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
1253 /* OCT 7 */
1254 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
1255 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
1256 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
1257 19.875/DV,20.250/DV,20.625/DV,21.000/DV
1258 };
1259
1260 /* 0 / 3.0 / 1.5 / 6.0 dB/OCT */
1261 const uint32_t FM_OPL::ksl_shift[4] = { 31, 1, 2, 0 };
1262
1263
1264 /* sustain level table (3dB per step) */
1265 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
1266 const uint32_t FM_OPL::sl_tab[16]={
1267 SC( 0),SC( 1),SC( 2),SC( 3),SC( 4),SC( 5),SC( 6),SC( 7),
1268 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
1269 };
1270
1271
1272 const unsigned char FM_OPL::eg_inc[15*RATE_STEPS]={
1273 /*cycle:0 1 2 3 4 5 6 7*/
1274
1275 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
1276 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
1277 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
1278 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
1279
1280 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
1281 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
1282 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
1283 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
1284
1285 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
1286 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
1287 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
1288 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
1289
1290 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 4) */
1291 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 2, 15 3 for attack */
1292 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
1293 };
1294
1295
1296 #define O(a) (a*RATE_STEPS)
1297
1298 /*note that there is no O(13) in this table - it's directly in the code */
1299 const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
1300 /* 16 infinite time rates */
1301 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
1302 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
1303
1304 /* rates 00-12 */
1305 O( 0),O( 1),O( 2),O( 3),
1306 O( 0),O( 1),O( 2),O( 3),
1307 O( 0),O( 1),O( 2),O( 3),
1308 O( 0),O( 1),O( 2),O( 3),
1309 O( 0),O( 1),O( 2),O( 3),
1310 O( 0),O( 1),O( 2),O( 3),
1311 O( 0),O( 1),O( 2),O( 3),
1312 O( 0),O( 1),O( 2),O( 3),
1313 O( 0),O( 1),O( 2),O( 3),
1314 O( 0),O( 1),O( 2),O( 3),
1315 O( 0),O( 1),O( 2),O( 3),
1316 O( 0),O( 1),O( 2),O( 3),
1317 O( 0),O( 1),O( 2),O( 3),
1318
1319 /* rate 13 */
1320 O( 4),O( 5),O( 6),O( 7),
1321
1322 /* rate 14 */
1323 O( 8),O( 9),O(10),O(11),
1324
1325 /* rate 15 */
1326 O(12),O(12),O(12),O(12),
1327
1328 /* 16 dummy rates (same as 15 3) */
1329 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
1330 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
1331
1332 };
1333 #undef O
1334
1335 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
1336 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
1337 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
1338
1339 #define O(a) (a*1)
1340 const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
1341 /* 16 infinite time rates */
1342 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
1343 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
1344
1345 /* rates 00-12 */
1346 O(12),O(12),O(12),O(12),
1347 O(11),O(11),O(11),O(11),
1348 O(10),O(10),O(10),O(10),
1349 O( 9),O( 9),O( 9),O( 9),
1350 O( 8),O( 8),O( 8),O( 8),
1351 O( 7),O( 7),O( 7),O( 7),
1352 O( 6),O( 6),O( 6),O( 6),
1353 O( 5),O( 5),O( 5),O( 5),
1354 O( 4),O( 4),O( 4),O( 4),
1355 O( 3),O( 3),O( 3),O( 3),
1356 O( 2),O( 2),O( 2),O( 2),
1357 O( 1),O( 1),O( 1),O( 1),
1358 O( 0),O( 0),O( 0),O( 0),
1359
1360 /* rate 13 */
1361 O( 0),O( 0),O( 0),O( 0),
1362
1363 /* rate 14 */
1364 O( 0),O( 0),O( 0),O( 0),
1365
1366 /* rate 15 */
1367 O( 0),O( 0),O( 0),O( 0),
1368
1369 /* 16 dummy rates (same as 15 3) */
1370 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
1371 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
1372
1373 };
1374 #undef O
1375
1376
1377 /* multiple table */
1378 #define ML 2
1379 const uint8_t FM_OPL::mul_tab[16]= {
1380 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
1381 ML/2, 1*ML, 2*ML, 3*ML, 4*ML, 5*ML, 6*ML, 7*ML,
1382 8*ML, 9*ML,10*ML,10*ML,12*ML,12*ML,15*ML,15*ML
1383 };
1384 #undef ML
1385
1386 signed int FM_OPL::tl_tab[TL_TAB_LEN];
1387
1388 /* sin waveform table in 'decibel' scale */
1389 /* four waveforms on OPL2 type chips */
1390 unsigned int FM_OPL::sin_tab[SIN_LEN * 4];
1391
1392
1393 /* LFO Amplitude Modulation table (verified on real YM3812)
1394 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
1395
1396 Length: 210 elements.
1397
1398 Each of the elements has to be repeated
1399 exactly 64 times (on 64 consecutive samples).
1400 The whole table takes: 64 * 210 = 13440 samples.
1401
1402 When AM = 1 data is used directly
1403 When AM = 0 data is divided by 4 before being used (losing precision is important)
1404 */
1405
1406 const uint8_t FM_OPL::lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
1407 0,0,0,0,0,0,0,
1408 1,1,1,1,
1409 2,2,2,2,
1410 3,3,3,3,
1411 4,4,4,4,
1412 5,5,5,5,
1413 6,6,6,6,
1414 7,7,7,7,
1415 8,8,8,8,
1416 9,9,9,9,
1417 10,10,10,10,
1418 11,11,11,11,
1419 12,12,12,12,
1420 13,13,13,13,
1421 14,14,14,14,
1422 15,15,15,15,
1423 16,16,16,16,
1424 17,17,17,17,
1425 18,18,18,18,
1426 19,19,19,19,
1427 20,20,20,20,
1428 21,21,21,21,
1429 22,22,22,22,
1430 23,23,23,23,
1431 24,24,24,24,
1432 25,25,25,25,
1433 26,26,26,
1434 25,25,25,25,
1435 24,24,24,24,
1436 23,23,23,23,
1437 22,22,22,22,
1438 21,21,21,21,
1439 20,20,20,20,
1440 19,19,19,19,
1441 18,18,18,18,
1442 17,17,17,17,
1443 16,16,16,16,
1444 15,15,15,15,
1445 14,14,14,14,
1446 13,13,13,13,
1447 12,12,12,12,
1448 11,11,11,11,
1449 10,10,10,10,
1450 9,9,9,9,
1451 8,8,8,8,
1452 7,7,7,7,
1453 6,6,6,6,
1454 5,5,5,5,
1455 4,4,4,4,
1456 3,3,3,3,
1457 2,2,2,2,
1458 1,1,1,1
1459 };
1460
1461 /* LFO Phase Modulation table (verified on real YM3812) */
1462 const int8_t FM_OPL::lfo_pm_table[8*8*2] = {
1463 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
1464 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
1465 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
1466
1467 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
1468 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
1469 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
1470
1471 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
1472 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
1473 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
1474
1475 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
1476 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
1477 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
1478
1479 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
1480 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
1481 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
1482
1483 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
1484 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
1485 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
1486
1487 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
1488 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
1489 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
1490
1491 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
1492 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
1493 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
1494 };
1495
1496
1497 /* lock level of common table */
1498 int FM_OPL::num_lock = 0;
1499
1500
1501 #if 0
1502 static inline int limit( int val, int max, int min ) {
1503 if ( val > max )
1504 val = max;
1505 else if ( val < min )
1506 val = min;
1507
1508 return val;
1509 }
1510 #endif
1511
1512 /* generic table initialize */
init_tables()1513 int FM_OPL::init_tables()
1514 {
1515 signed int i,x;
1516 signed int n;
1517 double o,m;
1518
1519
1520 for (x=0; x<TL_RES_LEN; x++)
1521 {
1522 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1523 m = floor(m);
1524
1525 /* we never reach (1<<16) here due to the (x+1) */
1526 /* result fits within 16 bits at maximum */
1527
1528 n = (int)m; /* 16 bits here */
1529 n >>= 4; /* 12 bits here */
1530 if (n&1) /* round to nearest */
1531 n = (n>>1)+1;
1532 else
1533 n = n>>1;
1534 /* 11 bits here (rounded) */
1535 n <<= 1; /* 12 bits here (as in real chip) */
1536 tl_tab[ x*2 + 0 ] = n;
1537 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
1538
1539 for (i=1; i<12; i++)
1540 {
1541 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1542 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
1543 }
1544 #if 0
1545 logerror("tl %04i", x*2);
1546 for (i=0; i<12; i++)
1547 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 /*+1*/ + i*2*TL_RES_LEN ] );
1548 logerror("\n");
1549 #endif
1550 }
1551 /*logerror("FMOPL.C: TL_TAB_LEN = %i elements (%i bytes)\n",TL_TAB_LEN, (int)sizeof(tl_tab));*/
1552
1553
1554 for (i=0; i<SIN_LEN; i++)
1555 {
1556 /* non-standard sinus */
1557 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1558
1559 /* we never reach zero here due to ((i*2)+1) */
1560
1561 if (m>0.0)
1562 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
1563 else
1564 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
1565
1566 o = o / (ENV_STEP/4);
1567
1568 n = (int)(2.0*o);
1569 if (n&1) /* round to nearest */
1570 n = (n>>1)+1;
1571 else
1572 n = n>>1;
1573
1574 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1575
1576 /*logerror("FMOPL.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1577 }
1578
1579 for (i=0; i<SIN_LEN; i++)
1580 {
1581 /* waveform 1: __ __ */
1582 /* / \____/ \____*/
1583 /* output only first half of the sinus waveform (positive one) */
1584
1585 if (i & (1<<(SIN_BITS-1)) )
1586 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1587 else
1588 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1589
1590 /* waveform 2: __ __ __ __ */
1591 /* / \/ \/ \/ \*/
1592 /* abs(sin) */
1593
1594 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1595
1596 /* waveform 3: _ _ _ _ */
1597 /* / |_/ |_/ |_/ |_*/
1598 /* abs(output only first quarter of the sinus waveform) */
1599
1600 if (i & (1<<(SIN_BITS-2)) )
1601 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1602 else
1603 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1604
1605 /*logerror("FMOPL.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
1606 logerror("FMOPL.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
1607 logerror("FMOPL.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );*/
1608 }
1609 /*logerror("FMOPL.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1610
1611
1612 #ifdef SAVE_SAMPLE
1613 sample[0]=fopen("sampsum.pcm","wb");
1614 #endif
1615
1616 return 1;
1617 }
1618
1619
initialize()1620 void FM_OPL::initialize()
1621 {
1622 int i;
1623
1624 /* frequency base */
1625 freqbase = (rate) ? ((double)clock / 72.0) / rate : 0;
1626 #if 0
1627 rate = (double)clock / 72.0;
1628 freqbase = 1.0;
1629 #endif
1630
1631 /*logerror("freqbase=%f\n", freqbase);*/
1632
1633 /* Timer base time */
1634 TimerBase = clock ? attotime::from_hz(clock) * 72 : attotime::zero;
1635
1636 /* make fnumber -> increment counter table */
1637 for( i=0 ; i < 1024 ; i++ )
1638 {
1639 /* opn phase increment counter = 20bit */
1640 fn_tab[i] = (uint32_t)( (double)i * 64 * freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1641 #if 0
1642 logerror("FMOPL.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1643 i, fn_tab[i]>>6, fn_tab[i]>>6 );
1644 #endif
1645 }
1646
1647 #if 0
1648 for( i=0 ; i < 16 ; i++ )
1649 {
1650 logerror("FMOPL.C: sl_tab[%i] = %08x\n",
1651 i, sl_tab[i] );
1652 }
1653 for( i=0 ; i < 8 ; i++ )
1654 {
1655 int j;
1656 logerror("FMOPL.C: ksl_tab[oct=%2i] =",i);
1657 for (j=0; j<16; j++)
1658 {
1659 logerror("%08x ", static_cast<uint32_t>(ksl_tab[i*16+j]) );
1660 }
1661 logerror("\n");
1662 }
1663 #endif
1664
1665
1666 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1667 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1668 lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * freqbase;
1669
1670 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1671 lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * freqbase;
1672
1673 /*logerror ("lfo_am_inc = %8x ; lfo_pm_inc = %8x\n", lfo_am_inc, lfo_pm_inc);*/
1674
1675 /* Noise generator: a step takes 1 sample */
1676 noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * freqbase;
1677
1678 eg_timer_add = (1<<EG_SH) * freqbase;
1679 eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1680 /*logerror("OPLinit eg_timer_add=%8x eg_timer_overflow=%8x\n", eg_timer_add, eg_timer_overflow);*/
1681 }
1682
1683
1684 /* write a value v to register r on OPL chip */
WriteReg(int r,int v)1685 void FM_OPL::WriteReg(int r, int v)
1686 {
1687 OPL_CH *CH;
1688 int slot;
1689 int block_fnum;
1690
1691
1692 /* adjust bus to 8 bits */
1693 r &= 0xff;
1694 v &= 0xff;
1695
1696 switch(r&0xe0)
1697 {
1698 case 0x00: /* 00-1f:control */
1699 switch(r&0x1f)
1700 {
1701 case 0x01: /* waveform select enable */
1702 if(type&OPL_TYPE_WAVESEL)
1703 {
1704 wavesel = v&0x20;
1705 /* do not change the waveform previously selected */
1706 }
1707 break;
1708 case 0x02: /* Timer 1 */
1709 T[0] = (256-v)*4;
1710 break;
1711 case 0x03: /* Timer 2 */
1712 T[1] = (256-v)*16;
1713 break;
1714 case 0x04: /* IRQ clear / mask and Timer enable */
1715 if(v&0x80)
1716 { /* IRQ flag clear */
1717 STATUS_RESET(0x7f-0x08); /* don't reset BFRDY flag or we will have to call deltat module to set the flag */
1718 }
1719 else
1720 { /* set IRQ mask ,timer enable*/
1721 uint8_t st1 = v&1;
1722 uint8_t st2 = (v>>1)&1;
1723
1724 /* IRQRST,T1MSK,t2MSK,EOSMSK,BRMSK,x,ST2,ST1 */
1725 STATUS_RESET(v & (0x78-0x08));
1726 STATUSMASK_SET((~v) & 0x78);
1727
1728 /* timer 2 */
1729 if(st[1] != st2)
1730 {
1731 attotime period = st2 ? (TimerBase * T[1]) : attotime::zero;
1732 st[1] = st2;
1733 if (timer_handler) (timer_handler)(TimerParam,1,period);
1734 }
1735 /* timer 1 */
1736 if(st[0] != st1)
1737 {
1738 attotime period = st1 ? (TimerBase * T[0]) : attotime::zero;
1739 st[0] = st1;
1740 if (timer_handler) (timer_handler)(TimerParam,0,period);
1741 }
1742 }
1743 break;
1744 #if BUILD_Y8950
1745 case 0x06: /* Key Board OUT */
1746 if(type&OPL_TYPE_KEYBOARD)
1747 {
1748 if(keyboardhandler_w)
1749 keyboardhandler_w(keyboard_param,v);
1750 else
1751 device->logerror("Y8950: write unmapped KEYBOARD port\n");
1752 }
1753 break;
1754 case 0x07: /* DELTA-T control 1 : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */
1755 if(type&OPL_TYPE_ADPCM)
1756 deltat->ADPCM_Write(r-0x07,v);
1757 break;
1758 #endif
1759 case 0x08: /* MODE,DELTA-T control 2 : CSM,NOTESEL,x,x,smpl,da/ad,64k,rom */
1760 mode = v;
1761 #if BUILD_Y8950
1762 if(type&OPL_TYPE_ADPCM)
1763 deltat->ADPCM_Write(r-0x07,v&0x0f); /* mask 4 LSBs in register 08 for DELTA-T unit */
1764 #endif
1765 break;
1766
1767 #if BUILD_Y8950
1768 case 0x09: /* START ADD */
1769 case 0x0a:
1770 case 0x0b: /* STOP ADD */
1771 case 0x0c:
1772 case 0x0d: /* PRESCALE */
1773 case 0x0e:
1774 case 0x0f: /* ADPCM data write */
1775 case 0x10: /* DELTA-N */
1776 case 0x11: /* DELTA-N */
1777 case 0x12: /* ADPCM volume */
1778 if(type&OPL_TYPE_ADPCM)
1779 deltat->ADPCM_Write(r-0x07,v);
1780 break;
1781
1782 case 0x15: /* DAC data high 8 bits (F7,F6...F2) */
1783 case 0x16: /* DAC data low 2 bits (F1, F0 in bits 7,6) */
1784 case 0x17: /* DAC data shift (S2,S1,S0 in bits 2,1,0) */
1785 device->logerror("FMOPL.C: DAC data register written, but not implemented reg=%02x val=%02x\n",r,v);
1786 break;
1787
1788 case 0x18: /* I/O CTRL (Direction) */
1789 if(type&OPL_TYPE_IO)
1790 portDirection = v&0x0f;
1791 break;
1792 case 0x19: /* I/O DATA */
1793 if(type&OPL_TYPE_IO)
1794 {
1795 portLatch = v;
1796 if(porthandler_w)
1797 porthandler_w(port_param,v&portDirection);
1798 }
1799 break;
1800 #endif
1801 default:
1802 device->logerror("FMOPL.C: write to unknown register: %02x\n",r);
1803 break;
1804 }
1805 break;
1806 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1807 slot = slot_array[r&0x1f];
1808 if(slot < 0) return;
1809 set_mul(slot,v);
1810 break;
1811 case 0x40:
1812 slot = slot_array[r&0x1f];
1813 if(slot < 0) return;
1814 set_ksl_tl(slot,v);
1815 break;
1816 case 0x60:
1817 slot = slot_array[r&0x1f];
1818 if(slot < 0) return;
1819 set_ar_dr(slot,v);
1820 break;
1821 case 0x80:
1822 slot = slot_array[r&0x1f];
1823 if(slot < 0) return;
1824 set_sl_rr(slot,v);
1825 break;
1826 case 0xa0:
1827 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1828 {
1829 lfo_am_depth = v & 0x80;
1830 lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1831
1832 rhythm = v&0x3f;
1833
1834 if(rhythm&0x20)
1835 {
1836 /* BD key on/off */
1837 if(v&0x10)
1838 {
1839 P_CH[6].SLOT[SLOT1].KEYON(2);
1840 P_CH[6].SLOT[SLOT2].KEYON(2);
1841 }
1842 else
1843 {
1844 P_CH[6].SLOT[SLOT1].KEYOFF(~2);
1845 P_CH[6].SLOT[SLOT2].KEYOFF(~2);
1846 }
1847 /* HH key on/off */
1848 if(v&0x01) P_CH[7].SLOT[SLOT1].KEYON ( 2);
1849 else P_CH[7].SLOT[SLOT1].KEYOFF(~2);
1850 /* SD key on/off */
1851 if(v&0x08) P_CH[7].SLOT[SLOT2].KEYON ( 2);
1852 else P_CH[7].SLOT[SLOT2].KEYOFF(~2);
1853 /* TOM key on/off */
1854 if(v&0x04) P_CH[8].SLOT[SLOT1].KEYON ( 2);
1855 else P_CH[8].SLOT[SLOT1].KEYOFF(~2);
1856 /* TOP-CY key on/off */
1857 if(v&0x02) P_CH[8].SLOT[SLOT2].KEYON ( 2);
1858 else P_CH[8].SLOT[SLOT2].KEYOFF(~2);
1859 }
1860 else
1861 {
1862 /* BD key off */
1863 P_CH[6].SLOT[SLOT1].KEYOFF(~2);
1864 P_CH[6].SLOT[SLOT2].KEYOFF(~2);
1865 /* HH key off */
1866 P_CH[7].SLOT[SLOT1].KEYOFF(~2);
1867 /* SD key off */
1868 P_CH[7].SLOT[SLOT2].KEYOFF(~2);
1869 /* TOM key off */
1870 P_CH[8].SLOT[SLOT1].KEYOFF(~2);
1871 /* TOP-CY off */
1872 P_CH[8].SLOT[SLOT2].KEYOFF(~2);
1873 }
1874 return;
1875 }
1876 /* keyon,block,fnum */
1877 if( (r&0x0f) > 8) return;
1878 CH = &P_CH[r&0x0f];
1879 if(!(r&0x10))
1880 { /* a0-a8 */
1881 block_fnum = (CH->block_fnum&0x1f00) | v;
1882 }
1883 else
1884 { /* b0-b8 */
1885 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1886
1887 if(v&0x20)
1888 {
1889 CH->SLOT[SLOT1].KEYON ( 1);
1890 CH->SLOT[SLOT2].KEYON ( 1);
1891 }
1892 else
1893 {
1894 CH->SLOT[SLOT1].KEYOFF(~1);
1895 CH->SLOT[SLOT2].KEYOFF(~1);
1896 }
1897 }
1898 /* update */
1899 if(CH->block_fnum != block_fnum)
1900 {
1901 uint8_t block = block_fnum >> 10;
1902
1903 CH->block_fnum = block_fnum;
1904
1905 CH->ksl_base = static_cast<uint32_t>(ksl_tab[block_fnum>>6]);
1906 CH->fc = fn_tab[block_fnum&0x03ff] >> (7-block);
1907
1908 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1909 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1910
1911 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YM3812) */
1912 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1913 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1914 if (mode&0x40)
1915 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1916 else
1917 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1918
1919 /* refresh Total Level in both SLOTs of this channel */
1920 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
1921 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
1922
1923 /* refresh frequency counter in both SLOTs of this channel */
1924 CH->CALC_FCSLOT(CH->SLOT[SLOT1]);
1925 CH->CALC_FCSLOT(CH->SLOT[SLOT2]);
1926 }
1927 break;
1928 case 0xc0:
1929 /* FB,C */
1930 if( (r&0x0f) > 8) return;
1931 CH = &P_CH[r&0x0f];
1932 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
1933 CH->SLOT[SLOT1].CON = v&1;
1934 CH->SLOT[SLOT1].connect1 = CH->SLOT[SLOT1].CON ? &output[0] : &phase_modulation;
1935 break;
1936 case 0xe0: /* waveform select */
1937 /* simply ignore write to the waveform select register if selecting not enabled in test register */
1938 if(wavesel)
1939 {
1940 slot = slot_array[r&0x1f];
1941 if(slot < 0) return;
1942 CH = &P_CH[slot/2];
1943
1944 CH->SLOT[slot&1].wavetable = (v&0x03)*SIN_LEN;
1945 }
1946 break;
1947 }
1948 }
1949
1950
ResetChip()1951 void FM_OPL::ResetChip()
1952 {
1953 eg_timer = 0;
1954 eg_cnt = 0;
1955
1956 noise_rng = 1; /* noise shift register */
1957 mode = 0; /* normal mode */
1958 STATUS_RESET(0x7f);
1959
1960 /* reset with register write */
1961 WriteReg(0x01,0); /* wavesel disable */
1962 WriteReg(0x02,0); /* Timer1 */
1963 WriteReg(0x03,0); /* Timer2 */
1964 WriteReg(0x04,0); /* IRQ mask clear */
1965 for(int i = 0xff ; i >= 0x20 ; i-- ) WriteReg(i,0);
1966
1967 /* reset operator parameters */
1968 for(OPL_CH &CH : P_CH)
1969 {
1970 for(OPL_SLOT &SLOT : CH.SLOT)
1971 {
1972 /* wave table */
1973 SLOT.wavetable = 0;
1974 SLOT.state = EG_OFF;
1975 SLOT.volume = MAX_ATT_INDEX;
1976 }
1977 }
1978 #if BUILD_Y8950
1979 if(type&OPL_TYPE_ADPCM)
1980 {
1981 deltat->freqbase = freqbase;
1982 deltat->output_pointer = &output_deltat[0];
1983 deltat->portshift = 5;
1984 deltat->output_range = 1<<23;
1985 deltat->ADPCM_Reset(0,YM_DELTAT::EMULATION_MODE_NORMAL,device);
1986 }
1987 #endif
1988 }
1989
1990
postload()1991 void FM_OPL::postload()
1992 {
1993 for(OPL_CH &CH : P_CH)
1994 {
1995 /* Look up key scale level */
1996 uint32_t const block_fnum = CH.block_fnum;
1997 CH.ksl_base = static_cast<uint32_t>(ksl_tab[block_fnum >> 6]);
1998 CH.fc = fn_tab[block_fnum & 0x03ff] >> (7 - (block_fnum >> 10));
1999
2000 for(OPL_SLOT &SLOT : CH.SLOT)
2001 {
2002 /* Calculate key scale rate */
2003 SLOT.ksr = CH.kcode >> SLOT.KSR;
2004
2005 /* Calculate attack, decay and release rates */
2006 if ((SLOT.ar + SLOT.ksr) < 16+62)
2007 {
2008 SLOT.eg_sh_ar = eg_rate_shift [SLOT.ar + SLOT.ksr ];
2009 SLOT.eg_sel_ar = eg_rate_select[SLOT.ar + SLOT.ksr ];
2010 }
2011 else
2012 {
2013 SLOT.eg_sh_ar = 0;
2014 SLOT.eg_sel_ar = 13*RATE_STEPS;
2015 }
2016 SLOT.eg_sh_dr = eg_rate_shift [SLOT.dr + SLOT.ksr ];
2017 SLOT.eg_sel_dr = eg_rate_select[SLOT.dr + SLOT.ksr ];
2018 SLOT.eg_sh_rr = eg_rate_shift [SLOT.rr + SLOT.ksr ];
2019 SLOT.eg_sel_rr = eg_rate_select[SLOT.rr + SLOT.ksr ];
2020
2021 /* Calculate phase increment */
2022 SLOT.Incr = CH.fc * SLOT.mul;
2023
2024 /* Total level */
2025 SLOT.TLL = SLOT.TL + (CH.ksl_base >> SLOT.ksl);
2026
2027 /* Connect output */
2028 SLOT.connect1 = SLOT.CON ? &output[0] : &phase_modulation;
2029 }
2030 }
2031 #if BUILD_Y8950
2032 if ( (type & OPL_TYPE_ADPCM) && (deltat) )
2033 {
2034 // We really should call the postlod function for the YM_DELTAT, but it's hard without registers
2035 // (see the way the YM2610 does it)
2036 //deltat->postload(REGS);
2037 }
2038 #endif
2039 }
2040
2041 } // anonymous namespace
2042
2043
OPLsave_state_channel(device_t * device,OPL_CH * CH)2044 static void OPLsave_state_channel(device_t *device, OPL_CH *CH)
2045 {
2046 int slot, ch;
2047
2048 for( ch=0 ; ch < 9 ; ch++, CH++ )
2049 {
2050 /* channel */
2051 device->save_item(NAME(CH->block_fnum), ch);
2052 device->save_item(NAME(CH->kcode), ch);
2053 /* slots */
2054 for( slot=0 ; slot < 2 ; slot++ )
2055 {
2056 OPL_SLOT *SLOT = &CH->SLOT[slot];
2057
2058 device->save_item(NAME(SLOT->ar), ch * 2 + slot);
2059 device->save_item(NAME(SLOT->dr), ch * 2 + slot);
2060 device->save_item(NAME(SLOT->rr), ch * 2 + slot);
2061 device->save_item(NAME(SLOT->KSR), ch * 2 + slot);
2062 device->save_item(NAME(SLOT->ksl), ch * 2 + slot);
2063 device->save_item(NAME(SLOT->mul), ch * 2 + slot);
2064
2065 device->save_item(NAME(SLOT->Cnt), ch * 2 + slot);
2066 device->save_item(NAME(SLOT->FB), ch * 2 + slot);
2067 device->save_item(NAME(SLOT->op1_out), ch * 2 + slot);
2068 device->save_item(NAME(SLOT->CON), ch * 2 + slot);
2069
2070 device->save_item(NAME(SLOT->eg_type), ch * 2 + slot);
2071 device->save_item(NAME(SLOT->state), ch * 2 + slot);
2072 device->save_item(NAME(SLOT->TL), ch * 2 + slot);
2073 device->save_item(NAME(SLOT->volume), ch * 2 + slot);
2074 device->save_item(NAME(SLOT->sl), ch * 2 + slot);
2075 device->save_item(NAME(SLOT->key), ch * 2 + slot);
2076
2077 device->save_item(NAME(SLOT->AMmask), ch * 2 + slot);
2078 device->save_item(NAME(SLOT->vib), ch * 2 + slot);
2079
2080 device->save_item(NAME(SLOT->wavetable), ch * 2 + slot);
2081 }
2082 }
2083 }
2084
2085
2086 /* Register savestate for a virtual YM3812/YM3526Y8950 */
2087
OPL_save_state(FM_OPL * OPL,device_t * device)2088 static void OPL_save_state(FM_OPL *OPL, device_t *device)
2089 {
2090 OPLsave_state_channel(device, OPL->P_CH);
2091
2092 device->save_item(NAME(OPL->eg_cnt));
2093 device->save_item(NAME(OPL->eg_timer));
2094
2095 device->save_item(NAME(OPL->rhythm));
2096
2097 device->save_item(NAME(OPL->lfo_am_depth));
2098 device->save_item(NAME(OPL->lfo_pm_depth_range));
2099 device->save_item(NAME(OPL->lfo_am_cnt));
2100 device->save_item(NAME(OPL->lfo_pm_cnt));
2101
2102 device->save_item(NAME(OPL->noise_rng));
2103 device->save_item(NAME(OPL->noise_p));
2104
2105 if( OPL->type & OPL_TYPE_WAVESEL )
2106 {
2107 device->save_item(NAME(OPL->wavesel));
2108 }
2109
2110 device->save_item(NAME(OPL->T));
2111 device->save_item(NAME(OPL->st));
2112
2113 #if BUILD_Y8950
2114 if ( (OPL->type & OPL_TYPE_ADPCM) && (OPL->deltat) )
2115 {
2116 OPL->deltat->savestate(device);
2117 }
2118
2119 if ( OPL->type & OPL_TYPE_IO )
2120 {
2121 device->save_item(NAME(OPL->portDirection));
2122 device->save_item(NAME(OPL->portLatch));
2123 }
2124 #endif
2125
2126 device->save_item(NAME(OPL->address));
2127 device->save_item(NAME(OPL->status));
2128 device->save_item(NAME(OPL->statusmask));
2129 device->save_item(NAME(OPL->mode));
2130
2131 device->machine().save().register_postload(save_prepost_delegate(FUNC(FM_OPL::postload), OPL));
2132 }
2133
2134
2135 #define MAX_OPL_CHIPS 2
2136
2137
2138 #if (BUILD_YM3812)
2139
ym3812_clock_changed(void * chip,uint32_t clock,uint32_t rate)2140 void ym3812_clock_changed(void *chip, uint32_t clock, uint32_t rate)
2141 {
2142 reinterpret_cast<FM_OPL *>(chip)->clock_changed(clock, rate);
2143 }
2144
ym3812_init(device_t * device,uint32_t clock,uint32_t rate)2145 void * ym3812_init(device_t *device, uint32_t clock, uint32_t rate)
2146 {
2147 /* emulator create */
2148 FM_OPL *YM3812 = FM_OPL::Create(device,clock,rate,OPL_TYPE_YM3812);
2149 if (YM3812)
2150 {
2151 OPL_save_state(YM3812, device);
2152 ym3812_reset_chip(YM3812);
2153 }
2154 return YM3812;
2155 }
2156
ym3812_shutdown(void * chip)2157 void ym3812_shutdown(void *chip)
2158 {
2159 FM_OPL *YM3812 = (FM_OPL *)chip;
2160
2161 /* emulator shutdown */
2162 delete YM3812;
2163 }
ym3812_reset_chip(void * chip)2164 void ym3812_reset_chip(void *chip)
2165 {
2166 FM_OPL *YM3812 = (FM_OPL *)chip;
2167 YM3812->ResetChip();
2168 }
2169
ym3812_write(void * chip,int a,int v)2170 int ym3812_write(void *chip, int a, int v)
2171 {
2172 FM_OPL *YM3812 = (FM_OPL *)chip;
2173 return YM3812->Write(a, v);
2174 }
2175
ym3812_read(void * chip,int a)2176 unsigned char ym3812_read(void *chip, int a)
2177 {
2178 FM_OPL *YM3812 = (FM_OPL *)chip;
2179 /* YM3812 always returns bit2 and bit1 in HIGH state */
2180 return YM3812->Read(a) | 0x06 ;
2181 }
ym3812_timer_over(void * chip,int c)2182 int ym3812_timer_over(void *chip, int c)
2183 {
2184 FM_OPL *YM3812 = (FM_OPL *)chip;
2185 return YM3812->TimerOver(c);
2186 }
2187
ym3812_set_timer_handler(void * chip,OPL_TIMERHANDLER timer_handler,device_t * device)2188 void ym3812_set_timer_handler(void *chip, OPL_TIMERHANDLER timer_handler, device_t *device)
2189 {
2190 reinterpret_cast<FM_OPL *>(chip)->SetTimerHandler(timer_handler, device);
2191 }
ym3812_set_irq_handler(void * chip,OPL_IRQHANDLER IRQHandler,device_t * device)2192 void ym3812_set_irq_handler(void *chip,OPL_IRQHANDLER IRQHandler,device_t *device)
2193 {
2194 reinterpret_cast<FM_OPL *>(chip)->SetIRQHandler(IRQHandler, device);
2195 }
ym3812_set_update_handler(void * chip,OPL_UPDATEHANDLER UpdateHandler,device_t * device)2196 void ym3812_set_update_handler(void *chip,OPL_UPDATEHANDLER UpdateHandler,device_t *device)
2197 {
2198 reinterpret_cast<FM_OPL *>(chip)->SetUpdateHandler(UpdateHandler, device);
2199 }
2200
2201
2202 /*
2203 ** Generate samples for one of the YM3812's
2204 **
2205 ** 'which' is the virtual YM3812 number
2206 ** '*buffer' is the output buffer pointer
2207 ** 'length' is the number of samples that should be generated
2208 */
ym3812_update_one(void * chip,write_stream_view & buf)2209 void ym3812_update_one(void *chip, write_stream_view &buf)
2210 {
2211 FM_OPL *OPL = (FM_OPL *)chip;
2212 uint8_t rhythm = OPL->rhythm&0x20;
2213 int i;
2214
2215 for( i=0; i < buf.samples(); i++ )
2216 {
2217 int lt;
2218
2219 OPL->output[0] = 0;
2220
2221 OPL->advance_lfo();
2222
2223 /* FM part */
2224 OPL->CALC_CH(OPL->P_CH[0]);
2225 OPL->CALC_CH(OPL->P_CH[1]);
2226 OPL->CALC_CH(OPL->P_CH[2]);
2227 OPL->CALC_CH(OPL->P_CH[3]);
2228 OPL->CALC_CH(OPL->P_CH[4]);
2229 OPL->CALC_CH(OPL->P_CH[5]);
2230
2231 if(!rhythm)
2232 {
2233 OPL->CALC_CH(OPL->P_CH[6]);
2234 OPL->CALC_CH(OPL->P_CH[7]);
2235 OPL->CALC_CH(OPL->P_CH[8]);
2236 }
2237 else /* Rhythm part */
2238 {
2239 OPL->CALC_RH();
2240 }
2241
2242 lt = OPL->output[0];
2243
2244 #ifdef SAVE_SAMPLE
2245 if (which==0)
2246 {
2247 SAVE_ALL_CHANNELS
2248 }
2249 #endif
2250
2251 /* store to sound buffer */
2252 buf.put_int_clamp(i, lt, 32768 << FINAL_SH);
2253
2254 OPL->advance();
2255 }
2256
2257 }
2258 #endif /* BUILD_YM3812 */
2259
2260
2261
2262 #if (BUILD_YM3526)
2263
ym3526_clock_changed(void * chip,uint32_t clock,uint32_t rate)2264 void ym3526_clock_changed(void *chip, uint32_t clock, uint32_t rate)
2265 {
2266 reinterpret_cast<FM_OPL *>(chip)->clock_changed(clock, rate);
2267 }
2268
ym3526_init(device_t * device,uint32_t clock,uint32_t rate)2269 void *ym3526_init(device_t *device, uint32_t clock, uint32_t rate)
2270 {
2271 /* emulator create */
2272 FM_OPL *YM3526 = FM_OPL::Create(device,clock,rate,OPL_TYPE_YM3526);
2273 if (YM3526)
2274 {
2275 OPL_save_state(YM3526, device);
2276 ym3526_reset_chip(YM3526);
2277 }
2278 return YM3526;
2279 }
2280
ym3526_shutdown(void * chip)2281 void ym3526_shutdown(void *chip)
2282 {
2283 FM_OPL *YM3526 = (FM_OPL *)chip;
2284 /* emulator shutdown */
2285 delete YM3526;
2286 }
ym3526_reset_chip(void * chip)2287 void ym3526_reset_chip(void *chip)
2288 {
2289 FM_OPL *YM3526 = (FM_OPL *)chip;
2290 YM3526->ResetChip();
2291 }
2292
ym3526_write(void * chip,int a,int v)2293 int ym3526_write(void *chip, int a, int v)
2294 {
2295 FM_OPL *YM3526 = (FM_OPL *)chip;
2296 return YM3526->Write(a, v);
2297 }
2298
ym3526_read(void * chip,int a)2299 unsigned char ym3526_read(void *chip, int a)
2300 {
2301 FM_OPL *YM3526 = (FM_OPL *)chip;
2302 /* YM3526 always returns bit2 and bit1 in HIGH state */
2303 return YM3526->Read(a) | 0x06 ;
2304 }
ym3526_timer_over(void * chip,int c)2305 int ym3526_timer_over(void *chip, int c)
2306 {
2307 FM_OPL *YM3526 = (FM_OPL *)chip;
2308 return YM3526->TimerOver(c);
2309 }
2310
ym3526_set_timer_handler(void * chip,OPL_TIMERHANDLER timer_handler,device_t * device)2311 void ym3526_set_timer_handler(void *chip, OPL_TIMERHANDLER timer_handler, device_t *device)
2312 {
2313 reinterpret_cast<FM_OPL *>(chip)->SetTimerHandler(timer_handler, device);
2314 }
ym3526_set_irq_handler(void * chip,OPL_IRQHANDLER IRQHandler,device_t * device)2315 void ym3526_set_irq_handler(void *chip,OPL_IRQHANDLER IRQHandler,device_t *device)
2316 {
2317 reinterpret_cast<FM_OPL *>(chip)->SetIRQHandler(IRQHandler, device);
2318 }
ym3526_set_update_handler(void * chip,OPL_UPDATEHANDLER UpdateHandler,device_t * device)2319 void ym3526_set_update_handler(void *chip,OPL_UPDATEHANDLER UpdateHandler,device_t *device)
2320 {
2321 reinterpret_cast<FM_OPL *>(chip)->SetUpdateHandler(UpdateHandler, device);
2322 }
2323
2324
2325 /*
2326 ** Generate samples for one of the YM3526's
2327 **
2328 ** 'which' is the virtual YM3526 number
2329 ** '*buffer' is the output buffer pointer
2330 ** 'length' is the number of samples that should be generated
2331 */
ym3526_update_one(void * chip,write_stream_view & buf)2332 void ym3526_update_one(void *chip, write_stream_view &buf)
2333 {
2334 FM_OPL *OPL = (FM_OPL *)chip;
2335 uint8_t rhythm = OPL->rhythm&0x20;
2336 int i;
2337
2338 for( i=0; i < buf.samples() ; i++ )
2339 {
2340 int lt;
2341
2342 OPL->output[0] = 0;
2343
2344 OPL->advance_lfo();
2345
2346 /* FM part */
2347 OPL->CALC_CH(OPL->P_CH[0]);
2348 OPL->CALC_CH(OPL->P_CH[1]);
2349 OPL->CALC_CH(OPL->P_CH[2]);
2350 OPL->CALC_CH(OPL->P_CH[3]);
2351 OPL->CALC_CH(OPL->P_CH[4]);
2352 OPL->CALC_CH(OPL->P_CH[5]);
2353
2354 if(!rhythm)
2355 {
2356 OPL->CALC_CH(OPL->P_CH[6]);
2357 OPL->CALC_CH(OPL->P_CH[7]);
2358 OPL->CALC_CH(OPL->P_CH[8]);
2359 }
2360 else /* Rhythm part */
2361 {
2362 OPL->CALC_RH();
2363 }
2364
2365 lt = OPL->output[0];
2366
2367 #ifdef SAVE_SAMPLE
2368 if (which==0)
2369 {
2370 SAVE_ALL_CHANNELS
2371 }
2372 #endif
2373
2374 /* store to sound buffer */
2375 buf.put_int_clamp(i, lt, 32768 << FINAL_SH);
2376
2377 OPL->advance();
2378 }
2379
2380 }
2381 #endif /* BUILD_YM3526 */
2382
2383
2384
2385
2386 #if BUILD_Y8950
2387
Y8950_deltat_status_set(void * chip,uint8_t changebits)2388 static void Y8950_deltat_status_set(void *chip, uint8_t changebits)
2389 {
2390 FM_OPL *Y8950 = (FM_OPL *)chip;
2391 Y8950->STATUS_SET(changebits);
2392 }
Y8950_deltat_status_reset(void * chip,uint8_t changebits)2393 static void Y8950_deltat_status_reset(void *chip, uint8_t changebits)
2394 {
2395 FM_OPL *Y8950 = (FM_OPL *)chip;
2396 Y8950->STATUS_RESET(changebits);
2397 }
2398
y8950_clock_changed(void * chip,uint32_t clock,uint32_t rate)2399 void y8950_clock_changed(void *chip, uint32_t clock, uint32_t rate)
2400 {
2401 reinterpret_cast<FM_OPL *>(chip)->clock_changed(clock, rate);
2402 }
2403
y8950_init(device_t * device,uint32_t clock,uint32_t rate)2404 void *y8950_init(device_t *device, uint32_t clock, uint32_t rate)
2405 {
2406 /* emulator create */
2407 FM_OPL *Y8950 = FM_OPL::Create(device,clock,rate,OPL_TYPE_Y8950);
2408 if (Y8950)
2409 {
2410 Y8950->deltat->status_set_handler = Y8950_deltat_status_set;
2411 Y8950->deltat->status_reset_handler = Y8950_deltat_status_reset;
2412 Y8950->deltat->status_change_which_chip = Y8950;
2413 Y8950->deltat->status_change_EOS_bit = 0x10; /* status flag: set bit4 on End Of Sample */
2414 Y8950->deltat->status_change_BRDY_bit = 0x08; /* status flag: set bit3 on BRDY (End Of: ADPCM analysis/synthesis, memory reading/writing) */
2415
2416 /*Y8950->deltat->write_time = 10.0 / clock;*/ /* a single byte write takes 10 cycles of main clock */
2417 /*Y8950->deltat->read_time = 8.0 / clock;*/ /* a single byte read takes 8 cycles of main clock */
2418 /* reset */
2419 OPL_save_state(Y8950, device);
2420 y8950_reset_chip(Y8950);
2421 }
2422
2423 return Y8950;
2424 }
2425
y8950_shutdown(void * chip)2426 void y8950_shutdown(void *chip)
2427 {
2428 FM_OPL *Y8950 = (FM_OPL *)chip;
2429 /* emulator shutdown */
2430 delete Y8950;
2431 }
y8950_reset_chip(void * chip)2432 void y8950_reset_chip(void *chip)
2433 {
2434 FM_OPL *Y8950 = (FM_OPL *)chip;
2435 Y8950->ResetChip();
2436 }
2437
y8950_write(void * chip,int a,int v)2438 int y8950_write(void *chip, int a, int v)
2439 {
2440 FM_OPL *Y8950 = (FM_OPL *)chip;
2441 return Y8950->Write(a, v);
2442 }
2443
y8950_read(void * chip,int a)2444 unsigned char y8950_read(void *chip, int a)
2445 {
2446 FM_OPL *Y8950 = (FM_OPL *)chip;
2447 return Y8950->Read(a);
2448 }
y8950_timer_over(void * chip,int c)2449 int y8950_timer_over(void *chip, int c)
2450 {
2451 FM_OPL *Y8950 = (FM_OPL *)chip;
2452 return Y8950->TimerOver(c);
2453 }
2454
y8950_set_timer_handler(void * chip,OPL_TIMERHANDLER timer_handler,device_t * device)2455 void y8950_set_timer_handler(void *chip, OPL_TIMERHANDLER timer_handler, device_t *device)
2456 {
2457 reinterpret_cast<FM_OPL *>(chip)->SetTimerHandler(timer_handler, device);
2458 }
y8950_set_irq_handler(void * chip,OPL_IRQHANDLER IRQHandler,device_t * device)2459 void y8950_set_irq_handler(void *chip,OPL_IRQHANDLER IRQHandler,device_t *device)
2460 {
2461 reinterpret_cast<FM_OPL *>(chip)->SetIRQHandler(IRQHandler, device);
2462 }
y8950_set_update_handler(void * chip,OPL_UPDATEHANDLER UpdateHandler,device_t * device)2463 void y8950_set_update_handler(void *chip,OPL_UPDATEHANDLER UpdateHandler,device_t *device)
2464 {
2465 reinterpret_cast<FM_OPL *>(chip)->SetUpdateHandler(UpdateHandler, device);
2466 }
2467
y8950_set_delta_t_memory(void * chip,FM_READBYTE read_byte,FM_WRITEBYTE write_byte)2468 void y8950_set_delta_t_memory(void *chip, FM_READBYTE read_byte, FM_WRITEBYTE write_byte)
2469 {
2470 FM_OPL *OPL = (FM_OPL *)chip;
2471 OPL->deltat->read_byte = read_byte;
2472 OPL->deltat->write_byte = write_byte;
2473 }
2474
2475 /*
2476 ** Generate samples for one of the Y8950's
2477 **
2478 ** 'which' is the virtual Y8950 number
2479 ** '*buffer' is the output buffer pointer
2480 ** 'length' is the number of samples that should be generated
2481 */
y8950_update_one(void * chip,write_stream_view & buf)2482 void y8950_update_one(void *chip, write_stream_view &buf)
2483 {
2484 int i;
2485 FM_OPL *OPL = (FM_OPL *)chip;
2486 uint8_t rhythm = OPL->rhythm&0x20;
2487 YM_DELTAT &DELTAT = *OPL->deltat;
2488
2489 for( i=0; i < buf.samples() ; i++ )
2490 {
2491 int lt;
2492
2493 OPL->output[0] = 0;
2494 OPL->output_deltat[0] = 0;
2495
2496 OPL->advance_lfo();
2497
2498 /* deltaT ADPCM */
2499 if( DELTAT.portstate&0x80 )
2500 DELTAT.ADPCM_CALC();
2501
2502 /* FM part */
2503 OPL->CALC_CH(OPL->P_CH[0]);
2504 OPL->CALC_CH(OPL->P_CH[1]);
2505 OPL->CALC_CH(OPL->P_CH[2]);
2506 OPL->CALC_CH(OPL->P_CH[3]);
2507 OPL->CALC_CH(OPL->P_CH[4]);
2508 OPL->CALC_CH(OPL->P_CH[5]);
2509
2510 if(!rhythm)
2511 {
2512 OPL->CALC_CH(OPL->P_CH[6]);
2513 OPL->CALC_CH(OPL->P_CH[7]);
2514 OPL->CALC_CH(OPL->P_CH[8]);
2515 }
2516 else /* Rhythm part */
2517 {
2518 OPL->CALC_RH();
2519 }
2520
2521 lt = OPL->output[0] + (OPL->output_deltat[0]>>11);
2522
2523 #ifdef SAVE_SAMPLE
2524 if (which==0)
2525 {
2526 SAVE_ALL_CHANNELS
2527 }
2528 #endif
2529
2530 /* store to sound buffer */
2531 buf.put_int_clamp(i, lt, 32768 << FINAL_SH);
2532
2533 OPL->advance();
2534 }
2535
2536 }
2537
y8950_set_port_handler(void * chip,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,device_t * device)2538 void y8950_set_port_handler(void *chip,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,device_t *device)
2539 {
2540 FM_OPL *OPL = (FM_OPL *)chip;
2541 OPL->porthandler_w = PortHandler_w;
2542 OPL->porthandler_r = PortHandler_r;
2543 OPL->port_param = device;
2544 }
2545
y8950_set_keyboard_handler(void * chip,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,device_t * device)2546 void y8950_set_keyboard_handler(void *chip,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,device_t *device)
2547 {
2548 FM_OPL *OPL = (FM_OPL *)chip;
2549 OPL->keyboardhandler_w = KeyboardHandler_w;
2550 OPL->keyboardhandler_r = KeyboardHandler_r;
2551 OPL->keyboard_param = device;
2552 }
2553
2554 #endif
2555