1 // license:BSD-3-Clause
2 // copyright-holders:Patrick Mackinlay
3
4 /*
5 * An emulation of the Intergraph InterPro/InterServe family of CLIPPER based
6 * UNIX workstations.
7 *
8 * The first systems were built using the original C100 CLIPPER CPU, and used
9 * an additional Intel 80186 as an I/O processor, later upgraded to a C300 and
10 * 80386 IOP. Around 1990, the CLIPPER became fast enough to obviate the need
11 * for the separate I/O processor, and systems from that point used the main
12 * CPU for both compute and I/O, along with some custom ASICs.
13 *
14 * Over the lifespan of the InterPro, there were five distinct families of
15 * systems, varying mainly in terms of the primary CPU, as follows:
16 *
17 * Year Family Models CPU
18 * 1986 amethyst 32C/100/200 C100 (80186 IOP)
19 * 300 C100 (80386 IOP)
20 * 1988 topaz 3000/4000/5000 C300/C300Plus (80386 IOP)
21 * 1990 emerald 6000/6100/6200/6500 C300/C300Plus
22 * 1990 turquoise 2000 C300
23 * 1991 emerald 6600 C4?
24 * 1992 sapphire 2400/6400 C4T
25 * 1993 sapphire 2500/2700/6700/6800 C4I
26 * 1994 sapphire 2800 C4I
27 *
28 * Individual models and some of their specific attributes include:
29 *
30 * Model Year CPU Performance Clock Family Bus
31 * 6000 1990 C300 10 MIPS 40MHz emerald SRX
32 * 1991 12 MIPS
33 * 6100 1990 C300+? 14 MIPS emerald IOI, 12-slot
34 1991 15.5 MIPS
35 * 6500 1990 C300+ 20 MIPS emerald IOI, QWIC bus?, 12-slot
36 * 6200 1990 C300+ 14 MIPS 60MHz emerald
37 * 1991 18 MIPS
38 * 2000 1990 C300 12.5 MIPS 50MHz? turquoise CBUS
39 * 1991 16 MIPS
40 * 6600 1991 C400 40 MIPS emerald IOI, SRX bus?
41 * 2400 1992 C4T 36 MIPS/33 SPECmarks 40MHz? sapphire CBUS
42 * 6400 1992 C4T 36 MIPS/33 SPECmarks 40MHz sapphire SRX
43 * 2700 1993 C400I 61 MIPS?/40.1 SPECmark89 sapphire 2 CBUS
44 * 6700 1993 C400I 61 MIPS?/40.1 SPECmark89 sapphire 2 SRX
45 * 6800 1993 C400I 85 MIPS/67.2 SPECmark89 sapphire 3 SRX
46 * 2500 1993 C400I 19.9 SPECint92 sapphire
47 * 2800 1994 C400I sapphire 3 CBUS?
48 *
49 * IOI == I/O Interface (another type of bus?)
50 * Sapphire 2 w/CBUS supports RETRY (maybe bus retry?)
51 *
52 * With some exceptions, system models are numbered ABCD, where:
53 *
54 * A: case type (2=desktop, 6=minicase)
55 * B: CPU type (0=C300, 4=C4T, 6=C400?, 7/8/5 = C400I)
56 * C: graphics type (0=none, 2=GT, 3=GT+, 5=GTII, 4=EDGE-1, 8=EDGE-2/2+)
57 * D: usually 0, 6xxx systems have 5, 7 and 9 options (backplane type?)
58 *
59 * Both the desktop and minicase units supported expansion slots with a variety
60 * of cards, although with different profiles and connectors between 2xxx and
61 * 6xxx systems. The 2xxx bus is referred to as CBUS, with the 6xxx bus known
62 * as SRX bus; SR (shared resource) bus is used to refer to either type. The
63 * bus supported a range of add-in cards, ranging from expanded SCSI and serial
64 * controllers, to specialised scanning and plotting controllers, a VME bridge,
65 * and most importantly various single and dual-headed graphics boards.
66 *
67 * The InterPro graphics options included the GT range, generally fitted to the
68 * desktops, and EDGE graphics for the 6xxx systems. Systems with no graphics
69 * were operated through a serial terminal on serial port 2, and were branded
70 * InterServe rather than InterPro.
71 *
72 * Model Year Performance
73 * GT 1990? 360k 2D vec/s (in a 2020)
74 * EDGE-1 8 planes + 1 highlight plane, double buffered (6040)
75 * EDGE-2 24 bit, 400k 2D vec/s, 350k 3D vec/s (6280)
76 * GT+ 500k 2D vec/s, 300k 2D vec/s (in a 2430)
77 * 760k 2D vec/s, 530k 3D vec/s (in a 2730)
78 * GTII 800k 2D vec/s, 500k 3D vec/s (in a 6450)
79 * 830k 2D vec/s, 640k 3D vec/s (in a 6750)
80 * 900k 2D vec/s, 700k 3D vec/s (in a 6850)
81 * EDGE II+ 600k 2D vec/s, 500k 3D vec/s, 50k shaded poly/s (in a 6480)
82 *
83 * GT graphics are also referred to in various places as Memory Mapped Graphics
84 * or MMG. EDGE stands for Extensible Display Geometry Engine.
85 *
86 * This driver currently supports the Emerald, Turquoise and Sapphire systems
87 * (i.e. 2x00 and 6x00 models), but not all of the variants of the Emerald at
88 * this point. GT/GTDB or EDGE graphics can be used depending on model, or
89 * graphics and keyboard uninstalled and a serial terminal used instead.
90 *
91 * Key parts lists for the supported models are as follows.
92 *
93 * 2000 Turquoise (PCB962 rev A, PCB824 rev J)
94 *
95 * Ref Part Function
96 * U37 Intel 82072 Floppy drive controller
97 * U39 Intel 82586 Ethernet controller
98 * U40 Zilog 8530 SCC Keyboard and console serial controller
99 * U41 Zilog 8530 SCC Serial controller for serial port 0 and 1
100 * U42 Xilinx XC3020-50 Plotter control FPGA?
101 * U43 (MPRGM610C) Bitstream for XC3020?
102 * U54 4.9152 MHz crystal Clock source for 8530s?
103 * U55 20.0 MHz crystal
104 * U57 24.0 MHz crystal Clock source for 53C90A?
105 * U61 NCR 53C90A SCSI controller
106 * U63 CIDC84607 TC110G75CY-0011 Intergraph I/O gate array?
107 * U116 Dallas DS1287 RTC and NVRAM
108 * U137? diagnostic 7-segment LED?
109 * U171 128 kB EPROM (MPRGM530E) Boot ROM MSB
110 * U172 128 kB EPROM (MPRGM540E) Boot ROM LSB
111 *
112 * 2400 Sapphire (SMT047 rev 0, SMT038?)
113 *
114 * Ref Part Function
115 * U31 Zilog Z85C30 SCC Keyboard and console serial controller
116 * U32 Zilog Z85230 ESCC Serial controller for serial port 0 and 1
117 * U34 Xilinx XC3020-50 Plotter control FPGA?
118 * U35 128 kB EPROM (MPRGW510B) Boot ROM
119 * U43? (MPRGM610P) Bitstream for XC3020?
120 * U44 Intel 82596SX-20 Ethernet controller
121 * U67 Intel N28F010-200 128Kx8 flash memory (Y226 0B03 0592)
122 * U68 CYID21603 TC150G89AF
123 * U71 LSI L1A6104 CICD 95801 Intergraph I/O gate array
124 * U76 Intel N28F010-200 128Kx8 flash memory (Y225 0B?? 27??)
125 * U81 NCR 53C94 SCSI controller
126 * U86 24.0 MHz crystal Clock source for 53C94?
127 * U87 4.9152 MHz crystal Clock source for 8530s?
128 * U88 20.0 MHz crystal Clock source for 82596?
129 * U91 Intel N82077AA-1 Floppy drive controller
130 * U96 32.0 MHz crystal
131 * U97 40.0 MHz crystal
132 * U112? (MPRG4230A) node ID prom?
133 * U113? Dallas DS1287 RTC and NVRAM
134 * U117? diagnostic 7-segment LED?
135 * U118? (MPRG X510R)
136 * U155 CYID21704 TC140G54AF
137 *
138 * 2700 Sapphire (SMT128 rev 0, SMT104 rev A)
139 *
140 * Ref Part Function
141 * U31 Zilog Z85C30 SCC Keyboard and console serial controller
142 * U32 Zilog Z85230 ESCC Serial controller for serial port 0 and 1
143 * U34 Xilinx XC3020-70 Plotter control FPGA?
144 * U35 128 kB EPROM (MPRGZ530A) Boot ROM
145 * U43? (MPRGM610P) Bitstream for XC3020?
146 * U44 Intel 82596SX-20 Ethernet controller
147 * U68 CYID21603 TC150G89AF
148 * U67 Intel N28F010 128Kx8 flash memory (Y226 0C30 4291)
149 * U71 LSI L1A7374 CICD094A3 Intergraph I/O gate array
150 * U76 Intel N28F010 128Kx8 flash memory (Y225 0C30 4220)
151 * U81 NCR 53C94 SCSI controller
152 * U86 24.0 MHz crystal Clock source for 82077
153 * U87 4.9152 MHz crystal Clock source for 8530s?
154 * U88 20.0 MHz crystal Clock source for 82596?
155 * U91 Intel N82077SL-1 Floppy drive controller
156 * U96 29.0 MHz crystal
157 * U97 40.0 MHz crystal
158 * U112? (MPRGZ260E) node ID prom?
159 * U113 Dallas DS12887 RTC and NVRAM
160 * U117? diagnostic 7-segment LED?
161 * U118? ()
162 * U155 CYID212?4 TC140G54AF?
163 *
164 * 6000 (PCB765 rev B, PCB82409 rev D)
165 *
166 * Ref Part Function
167 * U264 Xilinx XC3020-50 Plotter control FPGA?
168 * U294 4.9152 MHz crystal
169 * U287 Z8530H-6JC Serial controller
170 * U288 Z8530H-6JC Serial controller
171 * U318 24.0 MHz crystal
172 * U323 20.0 MHz crystal
173 * U324 Intel 82586-10 Ethernet controller
174 * U303 CICD84607 TC110G75CY
175 * U311 NCR 53C90A SCSI controller
176 * U336 27C010 (MPRGG360F) 128Kx8 Boot EPROM MSB
177 * U341 Dallas DS1287 RTC and NVRAM
178 * U349 27C010 (MPRGG350F) 128Kx8 Boot EPROM LSB
179 * U347 Intel 82072 Floppy drive controller
180 *
181 * 6400 (SMT046 rev B, SMT082)
182 *
183 * 6800 Sapphire (SMT127 rev B, SMT104 rev C)
184 *
185 * Ref Part Function
186 * U53 LSI L1A7751 CICD094A3 Intergraph I/O gate array
187 * U55 Xilinx XC3020-70 Plotter control FPGA?
188 * U57 CYID21704 TC140G54AF
189 * U69 CYID21603 TC150G89AF
190 * U73 20.0 MHz crystal Clock source for 82596?
191 * U78 29.0 MHz crystal
192 * U88 4.9152 MHz crystal Clock source for 8530s?
193 * U94 40.0 MHz crystal
194 * U95 CICD 89703 TC110G11AT
195 * U108 24.0 MHz crystal Clock source for 82077
196 * U117 Intel N28F010 128Kx8 flash memory (Y225 0C40 6010)
197 * U118 Zilog Z85C30 SCC Keyboard and console serial controller
198 * U119 Zilog Z85230 ESCC Serial controller for serial port 0 and 1
199 * U130 Intel N28F010 128Kx8 flash memory (Y226 0C40 6280)
200 * U136 NCR 53C94 SCSI controller
201 * U144 27C1024 (MPRGZ530A) 64Kx16 Boot EPROM
202 * U145 Dallas DS12887 RTC and NVRAM
203 * U159 Intel 82596SX-20 Ethernet controller
204 * U164 Intel N82077SL-1? Floppy drive controller
205 *
206 * CPU daughter-boards
207 *
208 * PCB824 Rev J (MPCBA5507)
209 * CPCB82409 rev D (MPCB92108) - 6000 C311 + 2xC322 + 80MHz crystal
210 *
211 * SMT082 (MSMT0820B, 36MHz?) - 6400 (SMT046 "6400 36-MHz Series System Board")
212 * SMT03? 2400/6400 - (MSMT03804 -> rev 2 cammu, goes with "6400 36-MHz Series System Board", MSMT0380A eco 3+ use rev 3 cammu)
213 * SMT019 (MSMT019 C4E CPU Assembly)
214 * SMT104 Rev A - 2700/6700 (aka MSMT1040A "C4I CPU", C4 CPU REV 3 + C4 FPU REV 3 + C4I CAMMU)
215 *
216 * PCB962 2000 System Board MPCB824 C300
217 * PCB??? 6000 System Board w/?MB MPCB824 C300
218 * SMT046 6400 36-MHz Series System Board MSMT03804 rev 2 CAMMU/30MHz Kryptonite Rev 3 CAMMU/32MHz Kryptonite Rev 3 CAMMU/MSMT0820B(36MHz)
219 * SMT047 2400 Series System Board MSMT03804 rev 2 CAMMU/MSMT0380A eco 3+ Rev 3 CAMMU
220 * SMT098A 6400 32-MHz Sapphire System Board
221 * SMT098B 6400 32-MHz Sapphire System Board
222 * SMT127 6700 Series System Board MSMT1040A C4I: C4 CPU Rev 3 + C4 FPU Rev 3 + C4I CAMMU
223 * SMT128 2700 Series System Board MSMT1040A C4I: C4 CPU Rev 3 + C4 FPU Rev 3 + C4I CAMMU
224 * SMT144 6800 Series System Board integrated cpu?
225 * SMT145 2800 Series System Board
226 */
227
228 #include "emu.h"
229
230 #include "cpu/clipper/clipper.h"
231 #include "machine/cammu.h"
232
233 #include "machine/interpro_ioga.h"
234 #include "machine/interpro_mcga.h"
235 #include "machine/interpro_sga.h"
236 #include "machine/interpro_arbga.h"
237
238 #include "imagedev/floppy.h"
239 #include "machine/ram.h"
240 #include "machine/28fxxx.h"
241 #include "machine/mc146818.h"
242 #include "machine/z80scc.h"
243 #include "machine/upd765.h"
244 #include "machine/i82586.h"
245
246 #include "machine/ncr5390.h"
247 #include "machine/nscsi_bus.h"
248 #include "bus/nscsi/cd.h"
249 #include "bus/nscsi/hd.h"
250
251 #include "bus/rs232/rs232.h"
252
253 #include "bus/interpro/sr/sr.h"
254 #include "bus/interpro/sr/sr_cards.h"
255 #include "bus/interpro/keyboard/keyboard.h"
256 #include "bus/interpro/mouse/mouse.h"
257
258 #include "formats/pc_dsk.h"
259 #include "softlist.h"
260
261 #include "machine/input_merger.h"
262
263 #include "debugger.h"
264
265 #include "interpro.lh"
266
267 #define VERBOSE 0
268 #include "logmacro.h"
269
270 namespace {
271
272 class interpro_state : public driver_device
273 {
274 public:
interpro_state(const machine_config & mconfig,device_type type,const char * tag)275 interpro_state(const machine_config &mconfig, device_type type, const char *tag)
276 : driver_device(mconfig, type, tag)
277 , m_maincpu(*this, "cpu")
278 , m_ram(*this, "ram")
279 , m_mcga(*this, "mcga")
280 , m_sga(*this, "sga")
281 , m_fdc(*this, "fdc")
282 , m_scc1(*this, "scc1")
283 , m_scc2(*this, "scc2")
284 , m_rtc(*this, "rtc")
285 , m_scsibus(*this, "scsi")
286 , m_eth(*this, "eth")
287 , m_ioga(*this, "ioga")
288 , m_eprom(*this, "eprom")
289 , m_softlist(*this, "softlist")
290 , m_diag_led(*this, "digit0")
291 {
292 }
293
294 required_device<clipper_device> m_maincpu;
295 required_device<ram_device> m_ram;
296
297 required_device<interpro_mcga_device> m_mcga;
298 required_device<interpro_sga_device> m_sga;
299 required_device<upd765_family_device> m_fdc;
300 required_device<z80scc_device> m_scc1;
301 required_device<z80scc_device> m_scc2;
302 required_device<mc146818_device> m_rtc;
303 required_device<nscsi_bus_device> m_scsibus;
304 required_device<i82586_base_device> m_eth;
305 required_device<interpro_ioga_device> m_ioga;
306 required_region_ptr<u16> m_eprom;
307
308 required_device<software_list_device> m_softlist;
309
310 void init_common();
311
312 virtual u32 unmapped_r(address_space &space, offs_t offset);
313 virtual void unmapped_w(offs_t offset, u32 data);
314
315 enum error_mask : u16
316 {
317 ERROR_BPID4 = 0x0001,
318 ERROR_SRXMMBE = 0x0002,
319 ERROR_SRXHOG = 0x0004,
320 ERROR_SRXNEM = 0x0008,
321 ERROR_SRXVALID = 0x0010,
322 ERROR_CBUSNMI = 0x0020,
323 ERROR_CBUSBG = 0x00c0,
324 ERROR_BG = 0x0070,
325 ERROR_BUSHOG = 0x0080
326 };
327 u16 error_r();
328
329 void led_w(offs_t offset, u16 data, u16 mem_mask = ~0);
330
331 enum status_mask : u16
332 {
333 STATUS_YELLOW_ZONE = 0x0001,
334 STATUS_SRNMI = 0x0002,
335 STATUS_PWRLOSS = 0x0004,
336 STATUS_RED_ZONE = 0x0008,
337 STATUS_BP = 0x00f0
338 };
status_r()339 u16 status_r() { return m_status; }
340
341 virtual u16 ctrl1_r() = 0;
342 virtual void ctrl1_w(offs_t offset, u16 data, u16 mem_mask = ~0) = 0;
343 virtual u16 ctrl2_r() = 0;
344 virtual void ctrl2_w(offs_t offset, u16 data, u16 mem_mask = ~0) = 0;
345
346 u8 nodeid_r(address_space &space, offs_t offset);
347
348 DECLARE_FLOPPY_FORMATS(floppy_formats);
349
350 void ioga(machine_config &config);
351 void interpro_serial(machine_config &config);
352 void interpro(machine_config &config);
353 static void interpro_scsi_adapter(device_t *device);
354 static void interpro_cdrom(device_t *device);
355 void interpro_boot_map(address_map &map);
356 void interpro_common_map(address_map &map);
357
358 protected:
359 virtual void machine_start() override;
360 virtual void machine_reset() override;
361
362 output_finder<> m_diag_led;
363 emu_timer *m_reset_timer;
364
365 u16 m_error;
366 u16 m_status;
367 u16 m_led;
368 };
369
370 class emerald_state : public interpro_state
371 {
372 public:
emerald_state(const machine_config & mconfig,device_type type,const char * tag)373 emerald_state(const machine_config &mconfig, device_type type, const char *tag)
374 : interpro_state(mconfig, type, tag)
375 , m_d_cammu(*this, "cammu_d")
376 , m_i_cammu(*this, "cammu_i")
377 , m_scsi(*this, "scsi:7:host")
378 , m_bus(*this, "slot")
379 {
380 }
381
error_w(u8 data)382 void error_w(u8 data) { m_error = data; }
383
384 enum ctrl1_mask : u16
385 {
386 CTRL1_FLOPLOW = 0x0001, // 3.5" floppy select
387 CTRL1_FLOPRDY = 0x0002, // floppy ready enable?
388 CTRL1_LEDENA = 0x0004, // led display enable
389 CTRL1_LEDDP = 0x0008, // led right decimal point enable
390 CTRL1_ETHLOOP = 0x0010, // ethernet loopback enable?
391 CTRL1_ETHDTR = 0x0020, // modem dtr pin enable?
392 CTRL1_ETHRMOD = 0x0040, // remote modem configured (read)?
393 CTRL1_CLIPRESET = 0x0040, // hard reset (write)?
394 CTRL1_FIFOACTIVE = 0x0080 // plotter fifo active?
395 };
ctrl1_r()396 u16 ctrl1_r() override { return m_ctrl1; }
397 void ctrl1_w(offs_t offset, u16 data, u16 mem_mask = ~0) override;
398
399 enum ctrl2_mask : u16
400 {
401 CTRL2_PWRUP = 0x0001, // power supply voltage adjust?
402 CRTL2_PWRENA = 0x0002, // ?
403 CTRL2_HOLDOFF = 0x0004, // power supply shut down delay
404 CTRL2_EXTNMIENA = 0x0008, // power nmi enable
405 CTRL2_COLDSTART = 0x0010, // cold start flag
406 CTRL2_RESET = 0x0020, // soft reset
407 CTRL2_BUSENA = 0x0040, // clear bus grant error
408 CTRL2_FRCPARITY = 0x0080, // ?
409
410 CTRL2_WMASK = 0x000f
411 };
ctrl2_r()412 u16 ctrl2_r() override { return m_ctrl2; }
413 void ctrl2_w(offs_t offset, u16 data, u16 mem_mask = ~0) override;
414
415 required_device<cammu_c3_device> m_d_cammu;
416 required_device<cammu_c3_device> m_i_cammu;
417 required_device<ncr53c90a_device> m_scsi;
418 required_device<srx_bus_device> m_bus;
419
420 void emerald(machine_config &config);
421 void ip6000(machine_config &config);
422 void interpro_82586_map(address_map &map);
423 void emerald_base_map(address_map &map);
424 void emerald_main_map(address_map &map);
425 void emerald_io_map(address_map &map);
426
427 protected:
428 virtual void machine_start() override;
429 virtual void machine_reset() override;
430
431 private:
432 u16 m_ctrl1;
433 u16 m_ctrl2;
434 };
435
436 class turquoise_state : public interpro_state
437 {
438 public:
turquoise_state(const machine_config & mconfig,device_type type,const char * tag)439 turquoise_state(const machine_config &mconfig, device_type type, const char *tag)
440 : interpro_state(mconfig, type, tag)
441 , m_d_cammu(*this, "cammu_d")
442 , m_i_cammu(*this, "cammu_i")
443 , m_kbd_port(*this, "kbd")
444 , m_mse_port(*this, "mse")
445 , m_scsi(*this, "scsi:7:host")
446 , m_bus(*this, "slot")
447 {
448 }
449
error_w(u8 data)450 void error_w(u8 data) { m_error = data; }
451
452 enum ctrl1_mask : u16
453 {
454 CTRL1_FLOPLOW = 0x0001, // 3.5" floppy select
455 CTRL1_FLOPRDY = 0x0002, // floppy ready enable?
456 CTRL1_LEDENA = 0x0004, // led display enable
457 CTRL1_LEDDP = 0x0008, // led right decimal point enable
458 CTRL1_ETHLOOP = 0x0010, // ethernet loopback enable?
459 CTRL1_ETHDTR = 0x0020, // modem dtr pin enable?
460 CTRL1_ETHRMOD = 0x0040, // remote modem configured (read)?
461 CTRL1_CLIPRESET = 0x0040, // hard reset (write)?
462 CTRL1_FIFOACTIVE = 0x0080 // plotter fifo active?
463 };
ctrl1_r()464 u16 ctrl1_r() override { return m_ctrl1; }
465 void ctrl1_w(offs_t offset, u16 data, u16 mem_mask = ~0) override;
466
467 enum ctrl2_mask : u16
468 {
469 CTRL2_PWRUP = 0x0001, // power supply voltage adjust?
470 CRTL2_PWRENA = 0x0002, // ?
471 CTRL2_HOLDOFF = 0x0004, // power supply shut down delay
472 CTRL2_EXTNMIENA = 0x0008, // power nmi enable
473 CTRL2_COLDSTART = 0x0010, // cold start flag
474 CTRL2_RESET = 0x0020, // soft reset
475 CTRL2_BUSENA = 0x0040, // clear bus grant error
476 CTRL2_FRCPARITY = 0x0080, // ?
477
478 CTRL2_WMASK = 0x000f
479 };
ctrl2_r()480 u16 ctrl2_r() override { return m_ctrl2; }
481 void ctrl2_w(offs_t offset, u16 data, u16 mem_mask = ~0) override;
482
483 required_device<cammu_c3_device> m_d_cammu;
484 required_device<cammu_c3_device> m_i_cammu;
485 required_device<interpro_keyboard_port_device> m_kbd_port;
486 required_device<interpro_mouse_port_device> m_mse_port;
487 required_device<ncr53c90a_device> m_scsi;
488 required_device<cbus_bus_device> m_bus;
489
490 void turquoise(machine_config &config);
491 void ip2000(machine_config &config);
492 void interpro_82586_map(address_map &map);
493 void turquoise_base_map(address_map &map);
494 void turquoise_main_map(address_map &map);
495 void turquoise_io_map(address_map &map);
496
497 protected:
498 virtual void machine_start() override;
499 virtual void machine_reset() override;
500
501 private:
502 u16 m_ctrl1;
503 u16 m_ctrl2;
504 };
505
506 class sapphire_state : public interpro_state
507 {
508 public:
sapphire_state(const machine_config & mconfig,device_type type,const char * tag)509 sapphire_state(const machine_config &mconfig, device_type type, const char *tag)
510 : interpro_state(mconfig, type, tag)
511 , m_mmu(*this, "cammu")
512 , m_scsi(*this, "scsi:7:host")
513 , m_arbga(*this, "arbga")
514 , m_flash_lsb(*this, "flash_lsb")
515 , m_flash_msb(*this, "flash_msb")
516 {
517 }
518
519 virtual u32 unmapped_r(address_space &space, offs_t offset) override;
520 virtual void unmapped_w(offs_t offset, u32 data) override;
521
522 enum ctrl1_mask : u16
523 {
524 CTRL1_FLOPLOW = 0x0001, // 3.5" floppy select
525 // unused
526 CTRL1_LEDENA = 0x0004, // led display enable
527 CTRL1_LEDDP = 0x0008, // led right decimal point enable
528 CTRL1_MMBE = 0x0010, // mmbe enable
529 CTRL1_ETHDTR = 0x0020, // modem dtr pin enable
530 CTRL1_ETHRMOD = 0x0040, // 0 = sytem configured for remote modems
531 CTRL1_FIFOACTIVE = 0x0080 // 0 = plotter fifos reset
532 };
ctrl1_r()533 u16 ctrl1_r() override { return m_ctrl1; }
534 void ctrl1_w(offs_t offset, u16 data, u16 mem_mask = ~0) override;
535
536 enum ctrl2_mask : u16
537 {
538 CTRL2_PWRUP = 0x0003, // power supply voltage adjust
539 CTRL2_HOLDOFF = 0x0004, // power supply shut down delay
540 CTRL2_EXTNMIENA = 0x0008, // power nmi enable
541 CTRL2_COLDSTART = 0x0010, // cold start flag
542 CTRL2_RESET = 0x0020, // soft reset
543 CTRL2_BUSENA = 0x0040, // clear bus grant error
544 CTRL2_FLASHEN = 0x0080, // flash eprom write enable
545 };
ctrl2_r()546 u16 ctrl2_r() override { return m_ctrl2; }
547 void ctrl2_w(offs_t offset, u16 data, u16 mem_mask = ~0) override;
548
549 required_device<cammu_c4_device> m_mmu;
550 required_device<ncr53c94_device> m_scsi;
551 required_device<interpro_arbga_device> m_arbga;
552 required_device<intel_28f010_device> m_flash_lsb;
553 required_device<intel_28f010_device> m_flash_msb;
554
555 void sapphire(machine_config &config);
556
557 void interpro_82596_map(address_map &map);
558 void sapphire_base_map(address_map &map);
559 void sapphire_main_map(address_map &map);
560 void sapphire_io_map(address_map &map);
561
562 protected:
563 virtual void machine_start() override;
564 virtual void machine_reset() override;
565
566 private:
567 u16 m_ctrl1;
568 u16 m_ctrl2;
569 };
570
571 class cbus_sapphire_state : public sapphire_state
572 {
573 public:
cbus_sapphire_state(const machine_config & mconfig,device_type type,const char * tag)574 cbus_sapphire_state(const machine_config &mconfig, device_type type, const char *tag)
575 : sapphire_state(mconfig, type, tag)
576 , m_kbd_port(*this, "kbd")
577 , m_mse_port(*this, "mse")
578 , m_bus(*this, "slot")
579 {
580 }
581
582 void cbus_sapphire(machine_config &config);
583
584 void ip2500(machine_config &config);
585 void ip2400(machine_config &config);
586 void ip2700(machine_config &config);
587 void ip2800(machine_config &config);
588
589 protected:
590 required_device<interpro_keyboard_port_device> m_kbd_port;
591 required_device<interpro_mouse_port_device> m_mse_port;
592 required_device<cbus_bus_device> m_bus;
593 };
594
595 class srx_sapphire_state : public sapphire_state
596 {
597 public:
srx_sapphire_state(const machine_config & mconfig,device_type type,const char * tag)598 srx_sapphire_state(const machine_config &mconfig, device_type type, const char *tag)
599 : sapphire_state(mconfig, type, tag)
600 , m_bus(*this, "slot")
601 {
602 }
603
604 void srx_sapphire(machine_config &config);
605
606 void ip6400(machine_config &config);
607 void ip6700(machine_config &config);
608 void ip6800(machine_config &config);
609
610 protected:
611 required_device<srx_bus_device> m_bus;
612 };
613
machine_start()614 void interpro_state::machine_start()
615 {
616 m_diag_led.resolve();
617
618 save_item(NAME(m_error));
619 save_item(NAME(m_status));
620 save_item(NAME(m_led));
621 }
622
machine_reset()623 void interpro_state::machine_reset()
624 {
625 m_error = 0;
626 m_status = 0;
627 m_led = 0;
628 }
629
machine_start()630 void emerald_state::machine_start()
631 {
632 interpro_state::machine_start();
633
634 save_item(NAME(m_ctrl1));
635 save_item(NAME(m_ctrl2));
636
637 m_ctrl1 = 0;
638 // FIXME: disabled for now to avoid cold start diagnostic errors
639 m_ctrl2 = 0; // CTRL2_COLDSTART
640 }
641
machine_start()642 void turquoise_state::machine_start()
643 {
644 interpro_state::machine_start();
645
646 save_item(NAME(m_ctrl1));
647 save_item(NAME(m_ctrl2));
648
649 m_ctrl1 = 0;
650 // FIXME: disabled for now to avoid cold start diagnostic errors
651 m_ctrl2 = 0; // CTRL2_COLDSTART
652 }
653
machine_start()654 void sapphire_state::machine_start()
655 {
656 interpro_state::machine_start();
657
658 save_item(NAME(m_ctrl1));
659 save_item(NAME(m_ctrl2));
660
661 m_ctrl1 = 0;
662 // FIXME: disabled for now to avoid cold start diagnostic errors
663 m_ctrl2 = 0; // CTRL2_COLDSTART
664 }
665
machine_reset()666 void emerald_state::machine_reset()
667 {
668 interpro_state::machine_reset();
669
670 // deassert floppy ready
671 m_fdc->ready_w(true);
672 }
673
machine_reset()674 void turquoise_state::machine_reset()
675 {
676 interpro_state::machine_reset();
677
678 // deassert floppy ready
679 m_fdc->ready_w(true);
680 }
681
machine_reset()682 void sapphire_state::machine_reset()
683 {
684 interpro_state::machine_reset();
685
686 // flash rom requires the following
687 m_status = 0x400;
688 }
689
init_common()690 void interpro_state::init_common()
691 {
692 // FIXME: not all memory sizes are reported properly using fdm "5 inqhw" and
693 // "optimum_memory" commands
694
695 // 16 = reports 16M, banks empty?
696 // 32 = reports 16M, banks empty?
697 // 64 = reports 128M, 16x8
698 // 128 = reports 128M, 16x8
699 // 256 = reports 256M, 32x8
700
701 // map the configured ram
702 m_maincpu->space(0).install_ram(0, m_ram->mask(), m_ram->pointer());
703 }
704
led_w(offs_t offset,u16 data,u16 mem_mask)705 void interpro_state::led_w(offs_t offset, u16 data, u16 mem_mask)
706 {
707 // 7-segment decode patterns (hex digits) borrowed from wico.cpp (mc14495)
708 static const u8 patterns[16] = { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x6f, 0x77, 0x7c, 0x39, 0x5e, 0x79, 0x71 };
709
710 m_diag_led = patterns[data & 0xf];
711
712 COMBINE_DATA(&m_led);
713 }
714
ctrl1_w(offs_t offset,u16 data,u16 mem_mask)715 void emerald_state::ctrl1_w(offs_t offset, u16 data, u16 mem_mask)
716 {
717 LOG("control register 1 data 0x%04x mem_mask 0x%04x (%s)\n", data, mem_mask, machine().describe_context());
718
719 // check if led decimal point changes state
720 if ((data ^ m_ctrl1) & CTRL1_LEDDP)
721 m_led = (m_led + 0x80) & 0xff;
722
723 // FIXME: select 3.5" or 5.25" floppy drive?
724 //if ((data ^ m_sreg_ctrl1) & CTRL1_FLOPLOW)
725 // logerror("floplow %d\n", data & CTRL1_FLOPLOW ? 1 : 0);
726
727 // FIXME: floppy ready line handling - this is strange but working
728 if (data & CTRL1_FLOPRDY)
729 m_fdc->ready_w(!(data & CTRL1_FLOPRDY));
730
731 COMBINE_DATA(&m_ctrl1);
732 }
733
ctrl1_w(offs_t offset,u16 data,u16 mem_mask)734 void turquoise_state::ctrl1_w(offs_t offset, u16 data, u16 mem_mask)
735 {
736 LOG("control register 1 data 0x%04x mem_mask 0x%04x (%s)\n", data, mem_mask, machine().describe_context());
737
738 // check if led decimal point changes state
739 if ((data ^ m_ctrl1) & CTRL1_LEDDP)
740 m_led = (m_led + 0x80) & 0xff;
741
742 // FIXME: select 3.5" or 5.25" floppy drive?
743 //if ((data ^ m_sreg_ctrl1) & CTRL1_FLOPLOW)
744 // logerror("floplow %d\n", data & CTRL1_FLOPLOW ? 1 : 0);
745
746 // FIXME: floppy ready line handling - this is strange but working
747 if (data & CTRL1_FLOPRDY)
748 m_fdc->ready_w(!(data & CTRL1_FLOPRDY));
749
750 COMBINE_DATA(&m_ctrl1);
751 }
752
ctrl1_w(offs_t offset,u16 data,u16 mem_mask)753 void sapphire_state::ctrl1_w(offs_t offset, u16 data, u16 mem_mask)
754 {
755 LOG("control register 1 data 0x%04x mem_mask 0x%04x (%s)\n", data, mem_mask, machine().describe_context());
756
757 // check if led decimal point changes state
758 if ((data ^ m_ctrl1) & CTRL1_LEDDP)
759 m_led = (m_led + 0x80) & 0xff;
760
761 // FIXME: select 3.5" or 5.25" floppy drive?
762 //if ((data ^ m_ctrl1) & CTRL1_FLOPLOW)
763 // logerror("floplow %d\n", data & CTRL1_FLOPLOW ? 1 : 0);
764
765 COMBINE_DATA(&m_ctrl1);
766 }
767
ctrl2_w(offs_t offset,u16 data,u16 mem_mask)768 void emerald_state::ctrl2_w(offs_t offset, u16 data, u16 mem_mask)
769 {
770 LOG("control register 2 data 0x%04x mem_mask 0x%04x (%s)\n", data, mem_mask, machine().describe_context());
771 if (data & CTRL2_RESET)
772 {
773 m_ctrl2 &= ~CTRL2_COLDSTART;
774
775 machine().schedule_soft_reset();
776 }
777 else
778 m_ctrl2 = (m_ctrl2 & ~CTRL2_WMASK) | (data & CTRL2_WMASK);
779 }
780
ctrl2_w(offs_t offset,u16 data,u16 mem_mask)781 void turquoise_state::ctrl2_w(offs_t offset, u16 data, u16 mem_mask)
782 {
783 LOG("control register 2 data 0x%04x mem_mask 0x%04x (%s)\n", data, mem_mask, machine().describe_context());
784 if (data & CTRL2_RESET)
785 {
786 m_ctrl2 &= ~CTRL2_COLDSTART;
787
788 machine().schedule_soft_reset();
789 }
790 else
791 m_ctrl2 = (m_ctrl2 & ~CTRL2_WMASK) | (data & CTRL2_WMASK);
792 }
793
ctrl2_w(offs_t offset,u16 data,u16 mem_mask)794 void sapphire_state::ctrl2_w(offs_t offset, u16 data, u16 mem_mask)
795 {
796 LOG("control register 2 data 0x%04x mem_mask 0x%04x (%s)\n", data, mem_mask, machine().describe_context());
797 if (data & CTRL2_RESET)
798 {
799 m_ctrl2 &= ~CTRL2_COLDSTART;
800
801 machine().schedule_soft_reset();
802 }
803 else
804 m_ctrl2 = (m_ctrl2 & ~0x4d) | (data & 0x4d);
805
806 // enable/disable programming power on both flash devices
807 m_flash_lsb->vpp(data & CTRL2_FLASHEN ? ASSERT_LINE : CLEAR_LINE);
808 m_flash_msb->vpp(data & CTRL2_FLASHEN ? ASSERT_LINE : CLEAR_LINE);
809 }
810
error_r()811 u16 interpro_state::error_r()
812 {
813 const u16 result = m_error;
814
815 // clear error register on read
816 if (!machine().side_effects_disabled())
817 m_error = 0;
818
819 return result;
820 }
821
unmapped_r(address_space & space,offs_t offset)822 u32 interpro_state::unmapped_r(address_space &space, offs_t offset)
823 {
824 if (!machine().side_effects_disabled())
825 {
826 // flag non-existent memory error in system error register
827 m_error |= (ERROR_SRXNEM | ERROR_SRXVALID);
828
829 // tell ioga to raise a bus error
830 m_ioga->bus_error(interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2);
831 }
832
833 return space.unmap();
834 }
835
unmapped_w(offs_t offset,u32 data)836 void interpro_state::unmapped_w(offs_t offset, u32 data)
837 {
838 if (!machine().side_effects_disabled())
839 {
840 // flag non-existent memory error in system error register
841 m_error |= (ERROR_SRXNEM | ERROR_SRXVALID);
842
843 // tell ioga to raise a bus error
844 m_ioga->bus_error(interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2);
845 }
846 }
847
unmapped_r(address_space & space,offs_t offset)848 u32 sapphire_state::unmapped_r(address_space &space, offs_t offset)
849 {
850 // check if non-existent memory errors are enabled
851 if (!machine().side_effects_disabled())
852 if (m_arbga->tctrl_r() & interpro_arbga_device::TCTRL_ENNEM)
853 {
854 // flag non-existent memory error in system error register
855 m_error |= (ERROR_SRXNEM | ERROR_SRXVALID);
856
857 // tell ioga to raise a bus error
858 m_ioga->bus_error(interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2);
859 }
860
861 return space.unmap();
862 }
863
unmapped_w(offs_t offset,u32 data)864 void sapphire_state::unmapped_w(offs_t offset, u32 data)
865 {
866 // check if non-existent memory errors are enabled
867 if (m_arbga->tctrl_r() & interpro_arbga_device::TCTRL_ENNEM)
868 {
869 // flag non-existent memory error in system error register
870 m_error |= (ERROR_SRXNEM | ERROR_SRXVALID);
871
872 // tell ioga to raise a bus error
873 m_ioga->bus_error(interpro_ioga_device::BINFO_BERR | interpro_ioga_device::BINFO_SNAPOK, offset << 2);
874 }
875 }
876
nodeid_r(address_space & space,offs_t offset)877 u8 interpro_state::nodeid_r(address_space &space, offs_t offset)
878 {
879 // FIXME: hard coded node id for now
880 switch (offset)
881 {
882 // read system node id prom (contains last 3 bytes of mac address)
883 case 0: return 0x12;
884 case 1: return 0x34;
885 case 2: return 0x56;
886 case 3: return 0x9c; // checksum - sum of other bytes
887 }
888
889 return space.unmap();
890 }
891
interpro_common_map(address_map & map)892 void interpro_state::interpro_common_map(address_map &map)
893 {
894 //map(0x00000000, 0xffffffff).rw(FUNC(interpro_state::unmapped_r), FUNC(interpro_state::unmapped_w));
895
896 // FIXME: don't know what this range is for
897 map(0x08000000, 0x08000fff).noprw();
898
899 map(0x4f007e00, 0x4f007eff).m(m_sga, FUNC(interpro_sga_device::map));
900
901 map(0x7f000100, 0x7f00011f).m(m_fdc, FUNC(upd765_family_device::map)).umask32(0x000000ff);
902 map(0x7f000300, 0x7f000301).r(FUNC(interpro_state::error_r));
903 map(0x7f000304, 0x7f000305).rw(FUNC(interpro_state::status_r), FUNC(interpro_state::led_w));
904 map(0x7f000308, 0x7f000309).rw(FUNC(interpro_state::ctrl1_r), FUNC(interpro_state::ctrl1_w));
905 map(0x7f00030c, 0x7f00030d).rw(FUNC(interpro_state::ctrl2_r), FUNC(interpro_state::ctrl2_w));
906
907 map(0x7f000400, 0x7f00040f).rw(m_scc1, FUNC(z80scc_device::ab_dc_r), FUNC(z80scc_device::ab_dc_w)).umask32(0x000000ff);
908 map(0x7f000410, 0x7f00041f).rw(m_scc2, FUNC(z80scc_device::ab_dc_r), FUNC(z80scc_device::ab_dc_w)).umask32(0x000000ff);
909 map(0x7f000500, 0x7f000503).lrw8(
910 NAME([this] (offs_t offset) { return m_rtc->read(offset^1); }),
911 NAME([this] (offs_t offset, u8 data) { m_rtc->write(offset^1, data); })).umask32(0x000000ff);
912 map(0x7f000600, 0x7f000600).w(m_rtc, FUNC(mc146818_device::write));
913
914 // the system board id prom
915 map(0x7f000700, 0x7f00077f).rom().region("idprom", 0);
916
917 map(0x7f0fff00, 0x7f0fffff).m(m_ioga, FUNC(interpro_ioga_device::map));
918 }
919
emerald_base_map(address_map & map)920 void emerald_state::emerald_base_map(address_map &map)
921 {
922 interpro_common_map(map);
923
924 map(0x40000000, 0x4000003f).m(m_mcga, FUNC(interpro_mcga_device::map));
925
926 // scsi registers have unusual address mapping
927 map(0x7f000201, 0x7f000201).rw(m_scsi, FUNC(ncr53c90a_device::tcounter_lo_r), FUNC(ncr53c90a_device::tcount_lo_w));
928 map(0x7f000205, 0x7f000205).rw(m_scsi, FUNC(ncr53c90a_device::tcounter_hi_r), FUNC(ncr53c90a_device::tcount_hi_w));
929 map(0x7f000209, 0x7f000209).rw(m_scsi, FUNC(ncr53c90a_device::fifo_r), FUNC(ncr53c90a_device::fifo_w));
930 map(0x7f00020d, 0x7f00020d).rw(m_scsi, FUNC(ncr53c90a_device::command_r), FUNC(ncr53c90a_device::command_w));
931 map(0x7f000211, 0x7f000211).rw(m_scsi, FUNC(ncr53c90a_device::status_r), FUNC(ncr53c90a_device::bus_id_w));
932 map(0x7f000215, 0x7f000215).rw(m_scsi, FUNC(ncr53c90a_device::istatus_r), FUNC(ncr53c90a_device::timeout_w));
933 map(0x7f000219, 0x7f000219).rw(m_scsi, FUNC(ncr53c90a_device::seq_step_r), FUNC(ncr53c90a_device::sync_period_w));
934 map(0x7f00021d, 0x7f00021d).rw(m_scsi, FUNC(ncr53c90a_device::fifo_flags_r), FUNC(ncr53c90a_device::sync_offset_w));
935 map(0x7f000221, 0x7f000221).rw(m_scsi, FUNC(ncr53c90a_device::conf_r), FUNC(ncr53c90a_device::conf_w));
936 map(0x7f000225, 0x7f000225).w(m_scsi, FUNC(ncr53c90a_device::clock_w));
937 map(0x7f000229, 0x7f000229).w(m_scsi, FUNC(ncr53c90a_device::test_w));
938 map(0x7f00022d, 0x7f00022d).rw(m_scsi, FUNC(ncr53c90a_device::conf2_r), FUNC(ncr53c90a_device::conf2_w));
939
940 map(0x7f000300, 0x7f000300).w(FUNC(emerald_state::error_w));
941
942 map(0x7f000600, 0x7f00067f).rom().region("nodeid", 0);
943 }
944
emerald_main_map(address_map & map)945 void emerald_state::emerald_main_map(address_map &map)
946 {
947 //map(0x00000000, 0xffffffff).rw(FUNC(interpro_state::unmapped_r), FUNC(interpro_state::unmapped_w));
948
949 emerald_base_map(map);
950
951 map(0x00000000, 0x00ffffff).ram().share("ram");
952 map(0x7f100000, 0x7f13ffff).lr16([this] (offs_t offset) { return m_eprom[offset]; }, "eprom");
953 }
954
turquoise_base_map(address_map & map)955 void turquoise_state::turquoise_base_map(address_map &map)
956 {
957 interpro_common_map(map);
958
959 map(0x40000000, 0x4000003f).m(m_mcga, FUNC(interpro_mcga_device::map));
960
961 // scsi registers have unusual address mapping
962 map(0x7f000201, 0x7f000201).rw(m_scsi, FUNC(ncr53c90a_device::tcounter_lo_r), FUNC(ncr53c90a_device::tcount_lo_w));
963 map(0x7f000205, 0x7f000205).rw(m_scsi, FUNC(ncr53c90a_device::tcounter_hi_r), FUNC(ncr53c90a_device::tcount_hi_w));
964 map(0x7f000209, 0x7f000209).rw(m_scsi, FUNC(ncr53c90a_device::fifo_r), FUNC(ncr53c90a_device::fifo_w));
965 map(0x7f00020d, 0x7f00020d).rw(m_scsi, FUNC(ncr53c90a_device::command_r), FUNC(ncr53c90a_device::command_w));
966 map(0x7f000211, 0x7f000211).rw(m_scsi, FUNC(ncr53c90a_device::status_r), FUNC(ncr53c90a_device::bus_id_w));
967 map(0x7f000215, 0x7f000215).rw(m_scsi, FUNC(ncr53c90a_device::istatus_r), FUNC(ncr53c90a_device::timeout_w));
968 map(0x7f000219, 0x7f000219).rw(m_scsi, FUNC(ncr53c90a_device::seq_step_r), FUNC(ncr53c90a_device::sync_period_w));
969 map(0x7f00021d, 0x7f00021d).rw(m_scsi, FUNC(ncr53c90a_device::fifo_flags_r), FUNC(ncr53c90a_device::sync_offset_w));
970 map(0x7f000221, 0x7f000221).rw(m_scsi, FUNC(ncr53c90a_device::conf_r), FUNC(ncr53c90a_device::conf_w));
971 map(0x7f000225, 0x7f000225).w(m_scsi, FUNC(ncr53c90a_device::clock_w));
972 map(0x7f000229, 0x7f000229).w(m_scsi, FUNC(ncr53c90a_device::test_w));
973 map(0x7f00022d, 0x7f00022d).rw(m_scsi, FUNC(ncr53c90a_device::conf2_r), FUNC(ncr53c90a_device::conf2_w));
974
975 map(0x7f000300, 0x7f000300).w(FUNC(turquoise_state::error_w));
976
977 map(0x7f000600, 0x7f00067f).rom().region("nodeid", 0);
978 }
979
turquoise_main_map(address_map & map)980 void turquoise_state::turquoise_main_map(address_map &map)
981 {
982 //map(0x00000000, 0xffffffff).rw(FUNC(interpro_state::unmapped_r), FUNC(interpro_state::unmapped_w));
983
984 turquoise_base_map(map);
985
986 map(0x00000000, 0x00ffffff).ram().share("ram");
987 map(0x7f100000, 0x7f13ffff).lr16([this] (offs_t offset) { return m_eprom[offset]; }, "eprom");
988 }
989
sapphire_base_map(address_map & map)990 void sapphire_state::sapphire_base_map(address_map &map)
991 {
992 interpro_common_map(map);
993
994 map(0x40000000, 0x4000004f).m(m_mcga, FUNC(interpro_fmcc_device::map));
995 map(0x7f000200, 0x7f0002ff).m(m_arbga, FUNC(interpro_arbga_device::map));
996
997 map(0x7f000600, 0x7f00060f).r(FUNC(sapphire_state::nodeid_r)).umask32(0x000000ff);
998
999 // scsi registers have unusual address mapping
1000 map(0x7f001001, 0x7f001001).rw(m_scsi, FUNC(ncr53c94_device::tcounter_lo_r), FUNC(ncr53c94_device::tcount_lo_w));
1001 map(0x7f001101, 0x7f001101).rw(m_scsi, FUNC(ncr53c94_device::tcounter_hi_r), FUNC(ncr53c94_device::tcount_hi_w));
1002 map(0x7f001201, 0x7f001201).rw(m_scsi, FUNC(ncr53c94_device::fifo_r), FUNC(ncr53c94_device::fifo_w));
1003 map(0x7f001301, 0x7f001301).rw(m_scsi, FUNC(ncr53c94_device::command_r), FUNC(ncr53c94_device::command_w));
1004 map(0x7f001401, 0x7f001401).rw(m_scsi, FUNC(ncr53c94_device::status_r), FUNC(ncr53c94_device::bus_id_w));
1005 map(0x7f001501, 0x7f001501).rw(m_scsi, FUNC(ncr53c94_device::istatus_r), FUNC(ncr53c94_device::timeout_w));
1006 map(0x7f001601, 0x7f001601).rw(m_scsi, FUNC(ncr53c94_device::seq_step_r), FUNC(ncr53c94_device::sync_period_w));
1007 map(0x7f001701, 0x7f001701).rw(m_scsi, FUNC(ncr53c94_device::fifo_flags_r), FUNC(ncr53c94_device::sync_offset_w));
1008 map(0x7f001801, 0x7f001801).rw(m_scsi, FUNC(ncr53c94_device::conf_r), FUNC(ncr53c94_device::conf_w));
1009 map(0x7f001901, 0x7f001901).w(m_scsi, FUNC(ncr53c94_device::clock_w));
1010 map(0x7f001a01, 0x7f001a01).w(m_scsi, FUNC(ncr53c94_device::test_w));
1011 map(0x7f001b01, 0x7f001b01).rw(m_scsi, FUNC(ncr53c94_device::conf2_r), FUNC(ncr53c94_device::conf2_w));
1012 map(0x7f001c01, 0x7f001c01).w(m_scsi, FUNC(ncr53c94_device::conf3_w));
1013 map(0x7f001f01, 0x7f001f01).w(m_scsi, FUNC(ncr53c94_device::fifo_align_w));
1014 }
1015
sapphire_main_map(address_map & map)1016 void sapphire_state::sapphire_main_map(address_map &map)
1017 {
1018 //map(0x00000000, 0xffffffff).rw(FUNC(sapphire_state::unmapped_r), FUNC(sapphire_state::unmapped_w));
1019
1020 sapphire_base_map(map);
1021
1022 map(0x00000000, 0x00ffffff).ram().share("ram");
1023 map(0x7f100000, 0x7f11ffff).lr16([this] (offs_t offset) { return m_eprom[offset]; }, "eprom");
1024 map(0x7f180000, 0x7f1fffff).rw(m_flash_lsb, FUNC(intel_28f010_device::read), FUNC(intel_28f010_device::write)).umask32(0x00ff00ff).mask(0x3ffff);
1025 map(0x7f180000, 0x7f1fffff).rw(m_flash_msb, FUNC(intel_28f010_device::read), FUNC(intel_28f010_device::write)).umask32(0xff00ff00).mask(0x3ffff);
1026
1027 // HACK: for SRX bus Sapphire only
1028 //map(0x8f007f80, 0x8f007fff).rom().region("idprom", 0);
1029 }
1030
emerald_io_map(address_map & map)1031 void emerald_state::emerald_io_map(address_map &map)
1032 {
1033 emerald_base_map(map);
1034 }
1035
turquoise_io_map(address_map & map)1036 void turquoise_state::turquoise_io_map(address_map &map)
1037 {
1038 turquoise_base_map(map);
1039 }
1040
sapphire_io_map(address_map & map)1041 void sapphire_state::sapphire_io_map(address_map &map)
1042 {
1043 sapphire_base_map(map);
1044
1045 map(0x00000000, 0x00001fff).m(m_mmu, FUNC(cammu_c4_device::map));
1046 }
1047
interpro_boot_map(address_map & map)1048 void interpro_state::interpro_boot_map(address_map &map)
1049 {
1050 // FIXME: the real system may have some initial boot instructions in this boot
1051 // memory space which jump to the start of the boot eprom code, or there may
1052 // be some special address decoding logic for boot. For now, we fake it in the
1053 // CPU by hard-coding the start address to point at the eprom.
1054 map(0x00000000, 0x00001fff).ram();
1055 }
1056
interpro_82586_map(address_map & map)1057 void emerald_state::interpro_82586_map(address_map &map)
1058 {
1059 map(0x00000000, 0x00ffffff).rw(m_ioga, FUNC(emerald_ioga_device::eth_r), FUNC(emerald_ioga_device::eth_w));
1060 }
1061
interpro_82586_map(address_map & map)1062 void turquoise_state::interpro_82586_map(address_map &map)
1063 {
1064 map(0x00000000, 0x00ffffff).rw(m_ioga, FUNC(turquoise_ioga_device::eth_r), FUNC(turquoise_ioga_device::eth_w));
1065 }
1066
interpro_82596_map(address_map & map)1067 void sapphire_state::interpro_82596_map(address_map &map)
1068 {
1069 map(0x00000000, 0xffffffff).rw(m_ioga, FUNC(sapphire_ioga_device::eth_r), FUNC(sapphire_ioga_device::eth_w));
1070 }
1071
FLOPPY_FORMATS_MEMBER(interpro_state::floppy_formats)1072 FLOPPY_FORMATS_MEMBER(interpro_state::floppy_formats)
1073 FLOPPY_PC_FORMAT
1074 FLOPPY_FORMATS_END
1075
1076 void interpro_state::interpro_serial(machine_config &config)
1077 {
1078 input_merger_device &scc_int(INPUT_MERGER_ANY_HIGH(config, "scc_int"));
1079
1080 /*
1081 * Documentation states that all three serial ports have RxD, TxD, CTS and
1082 * RTS signals connected, and serial port 0 also has RI, DTR and DTS(?).
1083 * Serial diagnostics pass all tests (except internal loopback which is not
1084 * supported by z80scc_device) when a dec_loopback device is installed. The
1085 * diagnostic tests also indicate that DCD is connected on all three ports.
1086 *
1087 * The documentation consistently refers to a DTS signal on serial port 0,
1088 * but this appears to be an error or typo, as it doesn't match any known
1089 * RS-232 signal; possibly it should be DSR?
1090 */
1091 // scc1 channel A (serial port 1)
1092 rs232_port_device &port1(RS232_PORT(config, "serial1", default_rs232_devices, nullptr));
1093 port1.cts_handler().set(m_scc1, FUNC(z80scc_device::ctsa_w));
1094 port1.dcd_handler().set(m_scc1, FUNC(z80scc_device::dcda_w));
1095 port1.rxd_handler().set(m_scc1, FUNC(z80scc_device::rxa_w));
1096 m_scc1->out_rtsa_callback().set(port1, FUNC(rs232_port_device::write_rts));
1097 m_scc1->out_txda_callback().set(port1, FUNC(rs232_port_device::write_txd));
1098 m_scc1->out_wreqa_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_serial1)).invert();
1099
1100 // scc1 channel B (serial port 2)
1101 rs232_port_device &port2(RS232_PORT(config, "serial2", default_rs232_devices, nullptr));
1102 port2.cts_handler().set(m_scc1, FUNC(z80scc_device::ctsb_w));
1103 port2.dcd_handler().set(m_scc1, FUNC(z80scc_device::dcdb_w));
1104 port2.rxd_handler().set(m_scc1, FUNC(z80scc_device::rxb_w));
1105 m_scc1->out_rtsb_callback().set(port2, FUNC(rs232_port_device::write_rts));
1106 m_scc1->out_txdb_callback().set(port2, FUNC(rs232_port_device::write_txd));
1107 m_scc1->out_wreqb_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_serial2)).invert();
1108
1109 m_scc1->out_int_callback().set(scc_int, FUNC(input_merger_device::in_w<0>));
1110
1111 // scc2 channel B (serial port 0)
1112 rs232_port_device &port0(RS232_PORT(config, "serial0", default_rs232_devices, nullptr));
1113 port0.cts_handler().set(m_scc2, FUNC(z80scc_device::ctsb_w));
1114 port0.dcd_handler().set(m_scc2, FUNC(z80scc_device::dcdb_w));
1115 port0.ri_handler().set(m_scc2, FUNC(z80scc_device::syncb_w));
1116 port0.rxd_handler().set(m_scc2, FUNC(z80scc_device::rxb_w));
1117 m_scc2->out_dtrb_callback().set(port0, FUNC(rs232_port_device::write_dtr));
1118 m_scc2->out_rtsb_callback().set(port0, FUNC(rs232_port_device::write_rts));
1119 m_scc2->out_txdb_callback().set(port0, FUNC(rs232_port_device::write_txd));
1120 m_scc2->out_wreqb_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_serial0)).invert();
1121
1122 m_scc2->out_int_callback().set(scc_int, FUNC(input_merger_device::in_w<1>));
1123
1124 scc_int.output_handler().set(m_ioga, FUNC(interpro_ioga_device::ir11_w));
1125 }
1126
interpro_scsi_devices(device_slot_interface & device)1127 static void interpro_scsi_devices(device_slot_interface &device)
1128 {
1129 device.option_add("harddisk", NSCSI_HARDDISK);
1130 device.option_add("cdrom", NSCSI_CDROM);
1131 }
1132
interpro_scsi_adapter(device_t * device)1133 void interpro_state::interpro_scsi_adapter(device_t *device)
1134 {
1135 ncr5390_device &adapter = downcast<ncr5390_device &>(*device);
1136
1137 adapter.set_clock(24_MHz_XTAL);
1138
1139 adapter.irq_handler_cb().set(":ioga", FUNC(interpro_ioga_device::ir0_w));
1140 adapter.drq_handler_cb().set(":ioga", FUNC(interpro_ioga_device::drq_scsi));
1141 }
1142
interpro_cdrom(device_t * device)1143 void interpro_state::interpro_cdrom(device_t *device)
1144 {
1145 downcast<nscsi_cdrom_device &>(*device).set_block_size(512);
1146 }
1147
ioga(machine_config & config)1148 void interpro_state::ioga(machine_config &config)
1149 {
1150 m_ioga->out_nmi_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
1151 m_ioga->out_irq_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
1152 m_ioga->out_irq_vector_callback().set(m_maincpu, FUNC(clipper_device::set_ivec));
1153
1154 // ioga dma and serial dma channels
1155 //m_ioga->dma_r_callback<0>().set(unknown); // plotter
1156 m_ioga->dma_r_callback<1>().set("scsi:7:host", FUNC(ncr53c90a_device::dma_r));
1157 m_ioga->dma_w_callback<1>().set("scsi:7:host", FUNC(ncr53c90a_device::dma_w));
1158 m_ioga->dma_r_callback<2>().set(m_fdc, FUNC(upd765_family_device::dma_r));
1159 m_ioga->dma_w_callback<2>().set(m_fdc, FUNC(upd765_family_device::dma_w));
1160 m_ioga->serial_dma_r_callback<0>().set(m_scc2, FUNC(z80scc_device::db_r));
1161 m_ioga->serial_dma_w_callback<0>().set(m_scc2, FUNC(z80scc_device::db_w));
1162 m_ioga->serial_dma_r_callback<1>().set(m_scc1, FUNC(z80scc_device::da_r));
1163 m_ioga->serial_dma_w_callback<1>().set(m_scc1, FUNC(z80scc_device::da_w));
1164 m_ioga->serial_dma_r_callback<2>().set(m_scc1, FUNC(z80scc_device::db_r));
1165 m_ioga->serial_dma_w_callback<2>().set(m_scc1, FUNC(z80scc_device::db_w));
1166
1167 // ioga floppy terminal count, ethernet channel attention
1168 m_ioga->fdc_tc_callback().set(m_fdc, FUNC(upd765_family_device::tc_line_w));
1169 m_ioga->eth_ca_callback().set(m_eth, FUNC(i82586_base_device::ca));
1170 }
1171
interpro(machine_config & config)1172 void interpro_state::interpro(machine_config &config)
1173 {
1174 RAM(config, m_ram, 0);
1175 m_ram->set_default_size("16M");
1176 m_ram->set_extra_options("32M,64M,128M,256M");
1177
1178 // memory control gate array
1179
1180 // srx gate array
1181 INTERPRO_SGA(config, m_sga, 0);
1182 m_sga->berr_callback().set(m_ioga, FUNC(interpro_ioga_device::bus_error));
1183
1184 // floppy
1185
1186 // serial
1187
1188 // real-time clock/non-volatile memory
1189 MC146818(config, m_rtc, 32.768_kHz_XTAL);
1190 m_rtc->set_use_utc(true);
1191 m_rtc->irq().set(m_ioga, FUNC(interpro_ioga_device::ir9_w));
1192
1193 // scsi bus and devices
1194 NSCSI_BUS(config, m_scsibus, 0);
1195
1196 nscsi_connector &harddisk(NSCSI_CONNECTOR(config, "scsi:0", 0));
1197 interpro_scsi_devices(harddisk);
1198 harddisk.set_default_option("harddisk");
1199
1200 nscsi_connector &cdrom(NSCSI_CONNECTOR(config, "scsi:4", 0));
1201 interpro_scsi_devices(cdrom);
1202 cdrom.set_default_option("cdrom");
1203 cdrom.set_option_machine_config("cdrom", interpro_cdrom);
1204
1205 interpro_scsi_devices(NSCSI_CONNECTOR(config, "scsi:1", 0));
1206 interpro_scsi_devices(NSCSI_CONNECTOR(config, "scsi:2", 0));
1207 interpro_scsi_devices(NSCSI_CONNECTOR(config, "scsi:3", 0));
1208 interpro_scsi_devices(NSCSI_CONNECTOR(config, "scsi:5", 0));
1209 interpro_scsi_devices(NSCSI_CONNECTOR(config, "scsi:6", 0));
1210
1211 // ethernet
1212
1213 // i/o gate array
1214
1215 // system layout
1216 config.set_default_layout(layout_interpro);
1217
1218 // software lists
1219 SOFTWARE_LIST(config, m_softlist).set_original("interpro");
1220 }
1221
emerald(machine_config & config)1222 void emerald_state::emerald(machine_config &config)
1223 {
1224 interpro(config);
1225
1226 CLIPPER_C300(config, m_maincpu, 12.5_MHz_XTAL); // 40MHz?
1227 m_maincpu->set_addrmap(0, &emerald_state::emerald_main_map);
1228 m_maincpu->set_addrmap(1, &emerald_state::emerald_io_map);
1229 m_maincpu->set_addrmap(2, &emerald_state::interpro_boot_map);
1230 m_maincpu->set_irq_acknowledge_callback(m_ioga, FUNC(interpro_ioga_device::acknowledge_interrupt));
1231
1232 CAMMU_C3(config, m_i_cammu, 0);
1233 m_i_cammu->exception_callback().set(m_maincpu, FUNC(clipper_device::set_exception));
1234
1235 CAMMU_C3(config, m_d_cammu, 0);
1236 m_d_cammu->exception_callback().set(m_maincpu, FUNC(clipper_device::set_exception));
1237 m_d_cammu->add_linked(m_i_cammu);
1238
1239 // boot fails memory test without this
1240 m_ram->set_default_value(0);
1241
1242 // memory control gate array
1243 INTERPRO_MCGA(config, m_mcga, 0);
1244
1245 // floppy controller
1246 I82072(config, m_fdc, 24_MHz_XTAL);
1247 m_fdc->set_ready_line_connected(false);
1248 m_fdc->intrq_wr_callback().set(m_ioga, FUNC(interpro_ioga_device::ir1_w));
1249 m_fdc->drq_wr_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_floppy));
1250
1251 // connect a 3.5" drive at id 3
1252 //FLOPPY_CONNECTOR(config, "fdc:2", "525hd", FLOPPY_525_HD, true, interpro_state::floppy_formats).enable_sound(false);
1253 FLOPPY_CONNECTOR(config, "fdc:3", "35hd", FLOPPY_35_HD, true, interpro_state::floppy_formats).enable_sound(false);
1254
1255 // serial controllers and ports
1256 SCC85C30(config, m_scc1, 4.9152_MHz_XTAL);
1257 SCC85C30(config, m_scc2, 4.9152_MHz_XTAL);
1258 interpro_serial(config);
1259
1260 // scsi host adapter
1261 nscsi_connector &adapter(NSCSI_CONNECTOR(config, "scsi:7", 0));
1262 adapter.option_add_internal("host", NCR53C90A);
1263 adapter.set_default_option("host");
1264 adapter.set_fixed(true);
1265 adapter.set_option_machine_config("host", interpro_scsi_adapter);
1266
1267 // ethernet controller
1268 I82586(config, m_eth, 10_MHz_XTAL);
1269 m_eth->out_irq_cb().set(m_ioga, FUNC(interpro_ioga_device::ir12_w));
1270 m_eth->set_addrmap(0, &emerald_state::interpro_82586_map);
1271
1272 // i/o gate array
1273 EMERALD_IOGA(config, m_ioga, 0);
1274 m_ioga->set_memory(m_maincpu, 0);
1275 ioga(config);
1276
1277 // srx bus
1278 SRX_BUS(config, m_bus, 0);
1279 m_bus->set_main_space(m_maincpu, 0);
1280 m_bus->set_io_space(m_maincpu, 1);
1281
1282 m_bus->out_irq0_cb().set(m_ioga, FUNC(interpro_ioga_device::ir3_w));
1283 m_bus->out_irq1_cb().set(m_ioga, FUNC(interpro_ioga_device::ir4_w));
1284 m_bus->out_irq2_cb().set(m_ioga, FUNC(interpro_ioga_device::ir5_w));
1285 m_bus->out_irq3_cb().set(m_ioga, FUNC(interpro_ioga_device::ir6_w));
1286 }
1287
turquoise(machine_config & config)1288 void turquoise_state::turquoise(machine_config &config)
1289 {
1290 interpro(config);
1291
1292 CLIPPER_C300(config, m_maincpu, 12.5_MHz_XTAL); // 40Mhz?
1293 m_maincpu->set_addrmap(0, &turquoise_state::turquoise_main_map);
1294 m_maincpu->set_addrmap(1, &turquoise_state::turquoise_io_map);
1295 m_maincpu->set_addrmap(2, &turquoise_state::interpro_boot_map);
1296 m_maincpu->set_irq_acknowledge_callback(m_ioga, FUNC(interpro_ioga_device::acknowledge_interrupt));
1297
1298 CAMMU_C3(config, m_i_cammu, 0);
1299 m_i_cammu->exception_callback().set(m_maincpu, FUNC(clipper_device::set_exception));
1300
1301 CAMMU_C3(config, m_d_cammu, 0);
1302 m_d_cammu->exception_callback().set(m_maincpu, FUNC(clipper_device::set_exception));
1303 m_d_cammu->add_linked(m_i_cammu);
1304
1305 // boot fails memory test without this
1306 m_ram->set_default_value(0);
1307
1308 // memory control gate array
1309 INTERPRO_MCGA(config, m_mcga, 0);
1310
1311 // floppy controller
1312 I82072(config, m_fdc, 24_MHz_XTAL);
1313 m_fdc->set_ready_line_connected(false);
1314 m_fdc->intrq_wr_callback().set(m_ioga, FUNC(interpro_ioga_device::ir1_w));
1315 m_fdc->drq_wr_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_floppy));
1316
1317 // connect a 3.5" drive at id 3
1318 FLOPPY_CONNECTOR(config, "fdc:3", "35hd", FLOPPY_35_HD, true, interpro_state::floppy_formats).enable_sound(false);
1319
1320 // serial controllers and ports
1321 SCC85C30(config, m_scc1, 4.9152_MHz_XTAL);
1322 SCC85C30(config, m_scc2, 4.9152_MHz_XTAL);
1323 interpro_serial(config);
1324
1325 // keyboard port
1326 INTERPRO_KEYBOARD_PORT(config, m_kbd_port, interpro_keyboard_devices, nullptr);
1327 m_kbd_port->rxd_handler_cb().set(m_scc2, FUNC(z80scc_device::rxa_w));
1328 m_scc2->out_txda_callback().set(m_kbd_port, FUNC(interpro_keyboard_port_device::write_txd));
1329
1330 // mouse port
1331 INTERPRO_MOUSE_PORT(config, m_mse_port, interpro_mouse_devices, nullptr);
1332 m_mse_port->state_func().set(m_ioga, FUNC(interpro_ioga_device::mouse_status_w));
1333
1334 // scsi host adapter
1335 nscsi_connector &adapter(NSCSI_CONNECTOR(config, "scsi:7", 0));
1336 adapter.option_add_internal("host", NCR53C90A);
1337 adapter.set_default_option("host");
1338 adapter.set_fixed(true);
1339 adapter.set_option_machine_config("host", interpro_scsi_adapter);
1340
1341 // ethernet controller
1342 I82586(config, m_eth, 10_MHz_XTAL);
1343 m_eth->out_irq_cb().set(m_ioga, FUNC(interpro_ioga_device::ir12_w));
1344 m_eth->set_addrmap(0, &turquoise_state::interpro_82586_map);
1345
1346 // i/o gate array
1347 TURQUOISE_IOGA(config, m_ioga, 0);
1348 m_ioga->set_memory(m_maincpu, 0);
1349 ioga(config);
1350
1351 // cbus bus
1352 CBUS_BUS(config, m_bus, 0);
1353 m_bus->set_main_space(m_maincpu, 0);
1354 m_bus->set_io_space(m_maincpu, 1);
1355
1356 m_bus->out_irq0_cb().set(m_ioga, FUNC(interpro_ioga_device::ir3_w));
1357 m_bus->out_irq1_cb().set(m_ioga, FUNC(interpro_ioga_device::ir4_w));
1358 m_bus->out_irq2_cb().set(m_ioga, FUNC(interpro_ioga_device::ir5_w));
1359 m_bus->out_irq3_cb().set(m_ioga, FUNC(interpro_ioga_device::ir6_w));
1360 }
1361
sapphire(machine_config & config)1362 void sapphire_state::sapphire(machine_config &config)
1363 {
1364 interpro(config);
1365
1366 CLIPPER_C400(config, m_maincpu, 12.5_MHz_XTAL);
1367 m_maincpu->set_addrmap(0, &sapphire_state::sapphire_main_map);
1368 m_maincpu->set_addrmap(1, &sapphire_state::sapphire_io_map);
1369 m_maincpu->set_addrmap(2, &sapphire_state::interpro_boot_map);
1370 m_maincpu->set_irq_acknowledge_callback(m_ioga, FUNC(interpro_ioga_device::acknowledge_interrupt));
1371
1372 // FIXME: 2400/6400 should be C4T cammu?
1373 CAMMU_C4I(config, m_mmu, 0);
1374 m_mmu->exception_callback().set(m_maincpu, FUNC(clipper_device::set_exception));
1375
1376 // memory control gate array
1377 INTERPRO_FMCC(config, m_mcga, 0);
1378
1379 // floppy controller
1380 N82077AA(config, m_fdc, 24_MHz_XTAL, n82077aa_device::mode_t::PS2);
1381 m_fdc->intrq_wr_callback().set(m_ioga, FUNC(interpro_ioga_device::ir1_w));
1382 m_fdc->drq_wr_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_floppy));
1383
1384 // connect a 3.5" drive at id 1
1385 FLOPPY_CONNECTOR(config, "fdc:1", "35hd", FLOPPY_35_HD, true, interpro_state::floppy_formats).enable_sound(false);
1386
1387 // srx arbiter gate array
1388 INTERPRO_ARBGA(config, m_arbga, 0);
1389
1390 // serial controllers and ports
1391 SCC85230(config, m_scc1, 4.9152_MHz_XTAL);
1392 SCC85C30(config, m_scc2, 4.9152_MHz_XTAL);
1393 interpro_serial(config);
1394
1395 // scsi host adapter
1396 nscsi_connector &adapter(NSCSI_CONNECTOR(config, "scsi:7", 0));
1397 adapter.option_add_internal("host", NCR53C94);
1398 adapter.set_default_option("host");
1399 adapter.set_fixed(true);
1400 adapter.set_option_machine_config("host", interpro_scsi_adapter);
1401
1402 // ethernet controller
1403 I82596_LE16(config, m_eth, 20_MHz_XTAL);
1404 m_eth->out_irq_cb().set(m_ioga, FUNC(interpro_ioga_device::ir12_w));
1405 m_eth->set_addrmap(0, &sapphire_state::interpro_82596_map);
1406
1407 // i/o gate array
1408 SAPPHIRE_IOGA(config, m_ioga, 0);
1409 m_ioga->set_memory(m_maincpu, 0);
1410 ioga(config);
1411
1412 // flash memory
1413 INTEL_28F010(config, m_flash_lsb);
1414 INTEL_28F010(config, m_flash_msb);
1415 }
1416
ip2000(machine_config & config)1417 void turquoise_state::ip2000(machine_config &config)
1418 {
1419 turquoise(config);
1420
1421 // default is 2020 with GT graphics
1422 m_kbd_port->set_default_option("lle_en_us");
1423 m_mse_port->set_default_option("interpro_mouse");
1424
1425 CBUS_SLOT(config, "slot:0", 0, m_bus, cbus_cards, "mpcb963", false);
1426 CBUS_SLOT(config, "slot:1", 0, m_bus, cbus_cards, nullptr, false);
1427
1428 m_softlist->set_filter("2000");
1429 }
1430
cbus_sapphire(machine_config & config)1431 void cbus_sapphire_state::cbus_sapphire(machine_config &config)
1432 {
1433 sapphire(config);
1434
1435 // keyboard port
1436 INTERPRO_KEYBOARD_PORT(config, m_kbd_port, interpro_keyboard_devices, nullptr);
1437 m_kbd_port->rxd_handler_cb().set(m_scc2, FUNC(z80scc_device::rxa_w));
1438 m_scc2->out_txda_callback().set(m_kbd_port, FUNC(interpro_keyboard_port_device::write_txd));
1439
1440 // mouse port
1441 INTERPRO_MOUSE_PORT(config, m_mse_port, interpro_mouse_devices, nullptr);
1442 m_mse_port->state_func().set(m_ioga, FUNC(interpro_ioga_device::mouse_status_w));
1443
1444 // cbus bus
1445 CBUS_BUS(config, m_bus, 0);
1446 m_bus->set_main_space(m_maincpu, 0);
1447 m_bus->set_io_space(m_maincpu, 1);
1448
1449 m_bus->out_irq0_cb().set(m_ioga, FUNC(interpro_ioga_device::ir3_w));
1450 m_bus->out_irq1_cb().set(m_ioga, FUNC(interpro_ioga_device::ir4_w));
1451 m_bus->out_irq2_cb().set(m_ioga, FUNC(interpro_ioga_device::ir5_w));
1452 m_bus->out_irq3_cb().set(m_ioga, FUNC(interpro_ioga_device::ir6_w));
1453 }
1454
srx_sapphire(machine_config & config)1455 void srx_sapphire_state::srx_sapphire(machine_config &config)
1456 {
1457 sapphire(config);
1458
1459 // srx bus
1460 SRX_BUS(config, m_bus, 0);
1461 m_bus->set_main_space(m_maincpu, 0);
1462 m_bus->set_io_space(m_maincpu, 1);
1463
1464 m_bus->out_irq0_cb().set(m_ioga, FUNC(interpro_ioga_device::ir3_w));
1465 m_bus->out_irq1_cb().set(m_ioga, FUNC(interpro_ioga_device::ir4_w));
1466 m_bus->out_irq2_cb().set(m_ioga, FUNC(interpro_ioga_device::ir5_w));
1467 m_bus->out_irq3_cb().set(m_ioga, FUNC(interpro_ioga_device::ir6_w));
1468 }
1469
ip2400(machine_config & config)1470 void cbus_sapphire_state::ip2400(machine_config &config)
1471 {
1472 cbus_sapphire(config);
1473
1474 //m_maincpu->set_clock(50_MHz_XTAL);
1475 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR0);
1476
1477 // default is 2430 with GT+ graphics
1478 m_kbd_port->set_default_option("lle_en_us");
1479 m_mse_port->set_default_option("interpro_mouse");
1480
1481 CBUS_SLOT(config, "slot:0", 0, m_bus, cbus_cards, "msmt070", false);
1482 CBUS_SLOT(config, "slot:1", 0, m_bus, cbus_cards, nullptr, false);
1483
1484 m_softlist->set_filter("2400");
1485 }
1486
ip2500(machine_config & config)1487 void cbus_sapphire_state::ip2500(machine_config &config)
1488 {
1489 cbus_sapphire(config);
1490
1491 //m_maincpu->set_clock(?);
1492 // FIXME: don't know which cammu revision
1493 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR2);
1494
1495 // default is 2530 with GT+ graphics
1496 m_kbd_port->set_default_option("lle_en_us");
1497 m_mse_port->set_default_option("interpro_mouse");
1498
1499 CBUS_SLOT(config, "slot:0", 0, m_bus, cbus_cards, "msmt070", false);
1500 CBUS_SLOT(config, "slot:1", 0, m_bus, cbus_cards, nullptr, false);
1501
1502 m_softlist->set_filter("2500");
1503 }
1504
ip2700(machine_config & config)1505 void cbus_sapphire_state::ip2700(machine_config &config)
1506 {
1507 cbus_sapphire(config);
1508
1509 //m_maincpu->set_clock(?);
1510 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR2);
1511
1512 // default is 2730 with GT+ graphics
1513 m_kbd_port->set_default_option("lle_en_us");
1514 m_mse_port->set_default_option("interpro_mouse");
1515
1516 CBUS_SLOT(config, "slot:0", 0, m_bus, cbus_cards, "msmt070", false);
1517 CBUS_SLOT(config, "slot:1", 0, m_bus, cbus_cards, nullptr, false);
1518
1519 m_softlist->set_filter("2700");
1520 }
1521
ip2800(machine_config & config)1522 void cbus_sapphire_state::ip2800(machine_config &config)
1523 {
1524 cbus_sapphire(config);
1525
1526 //m_maincpu->set_clock(?);
1527 // FIXME: don't know which cammu revision
1528 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR2);
1529
1530 // default is 2830 with GT+ graphics
1531 m_kbd_port->set_default_option("lle_en_us");
1532 m_mse_port->set_default_option("interpro_mouse");
1533
1534 CBUS_SLOT(config, "slot:0", 0, m_bus, cbus_cards, "msmt070", false);
1535 CBUS_SLOT(config, "slot:1", 0, m_bus, cbus_cards, nullptr, false);
1536
1537 m_softlist->set_filter("2800");
1538 }
1539
ip6000(machine_config & config)1540 void emerald_state::ip6000(machine_config &config)
1541 {
1542 emerald(config);
1543
1544 // default is 6040 with EDGE-1 graphics
1545 SRX_SLOT(config, "slot:1", 0, m_bus, srx_cards, nullptr, false);
1546 SRX_SLOT(config, "slot:2", 0, m_bus, srx_cards, nullptr, false);
1547 SRX_SLOT(config, "slot:3", 0, m_bus, srx_cards, nullptr, false);
1548 SRX_SLOT(config, "slot:4", 0, m_bus, srx_cards, "mpcb828", false);
1549
1550 m_softlist->set_filter("6000");
1551 }
1552
ip6400(machine_config & config)1553 void srx_sapphire_state::ip6400(machine_config &config)
1554 {
1555 srx_sapphire(config);
1556
1557 //m_maincpu->set_clock(36_MHz_XTAL);
1558 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR0);
1559
1560 // default is 6450 with GT II graphics
1561 SRX_SLOT(config, "slot:1", 0, m_bus, srx_cards, nullptr, false);
1562 SRX_SLOT(config, "slot:2", 0, m_bus, srx_cards, nullptr, false);
1563 SRX_SLOT(config, "slot:3", 0, m_bus, srx_cards, nullptr, false);
1564 SRX_SLOT(config, "slot:4", 0, m_bus, srx_cards, "mpcbb68", false);
1565
1566 // EDGE-2 graphics (6480)
1567 //SRX_SLOT(config, "slot:3", 0, m_bus, srx_cards, "mpcb030", false);
1568 //SRX_SLOT(config, "slot:4", 0, m_bus, srx_cards, "mpcba63", false);
1569
1570 m_softlist->set_filter("6400");
1571 }
1572
ip6700(machine_config & config)1573 void srx_sapphire_state::ip6700(machine_config &config)
1574 {
1575 srx_sapphire(config);
1576
1577 //m_maincpu->set_clock(?);
1578 // FIXME: don't know which cammu revision
1579 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR2);
1580
1581 // default is 6780 with EDGE-2 Plus graphics
1582 SRX_SLOT(config, "slot:1", 0, m_bus, srx_cards, nullptr, false);
1583 SRX_SLOT(config, "slot:2", 0, m_bus, srx_cards, nullptr, false);
1584 SRX_SLOT(config, "slot:3", 0, m_bus, srx_cards, "msmt094", false);
1585 SRX_SLOT(config, "slot:4", 0, m_bus, srx_cards, "mpcb896", false);
1586
1587 m_softlist->set_filter("6700");
1588 }
1589
ip6800(machine_config & config)1590 void srx_sapphire_state::ip6800(machine_config &config)
1591 {
1592 srx_sapphire(config);
1593
1594 //m_maincpu->set_clock(?);
1595 // FIXME: don't know which cammu revision
1596 m_mmu->set_cammu_id(cammu_c4i_device::CID_C4IR2);
1597
1598 // default is 6880 with EDGE-2 Plus graphics
1599 SRX_SLOT(config, "slot:1", 0, m_bus, srx_cards, nullptr, false);
1600 SRX_SLOT(config, "slot:2", 0, m_bus, srx_cards, nullptr, false);
1601 SRX_SLOT(config, "slot:3", 0, m_bus, srx_cards, "msmt094", false);
1602 SRX_SLOT(config, "slot:4", 0, m_bus, srx_cards, "mpcb896", false);
1603
1604 m_softlist->set_filter("6800");
1605 }
1606
1607 ROM_START(ip2000)
1608 ROM_REGION32_LE(0x80, "nodeid", 0)
1609 ROM_LOAD32_BYTE("nodeid.bin", 0x0, 0x20, CRC(a38397a6) SHA1(9f45fb932bbe231c95b3d5470dcd1fa1c846486f))
1610
1611 ROM_REGION32_LE(0x80, "idprom", 0)
1612 ROM_LOAD32_BYTE("mpcb962a.bin", 0x0, 0x20, CRC(e391342c) SHA1(02e03aad760b6651b8599c3a41c7c457983ee97d))
1613
1614 ROM_REGION16_LE(0x40000, "eprom", 0)
1615 ROM_SYSTEM_BIOS(0, "ip2000", "InterPro/InterServe 20x0 EPROM")
1616 ROMX_LOAD("mprgm530e__26_apr_91k.u171", 0x00001, 0x20000, CRC(e4c470cb) SHA1(ff1917bfa963988d739a9dbf0b8f034fe49f2f8c), ROM_SKIP(1) | ROM_BIOS(0))
1617 ROMX_LOAD("mprgm540e__06_may_91k.u172", 0x00000, 0x20000, CRC(03225843) SHA1(03cfcd5b8ae0057240ef808a40108cb5d082eb63), ROM_SKIP(1) | ROM_BIOS(0))
1618 ROM_END
1619
1620 ROM_START(ip2400)
1621 // feature[0] & 0x02: C4I cammu if set
1622 ROM_REGION32_LE(0x80, "idprom", 0)
1623 ROM_LOAD32_BYTE("msmt0470.bin", 0x0, 0x20, CRC(498c80df) SHA1(18a49732ac9d04b20a77747c1b946c2e88abb087))
1624
1625 ROM_REGION16_LE(0x20000, "eprom", 0)
1626 ROM_SYSTEM_BIOS(0, "ip2400", "InterPro/InterServe 24x0 EPROM")
1627 ROMX_LOAD("mprgw510b__05_16_92.u35", 0x00000, 0x20000, CRC(3b2c4545) SHA1(4e4c98d1cd1035a04be8527223f44d0b687ec3ef), ROM_BIOS(0))
1628
1629 ROM_REGION(0x20000, "flash_lsb", 0)
1630 ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1631
1632 ROM_REGION(0x20000, "flash_msb", 0)
1633 ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1634 ROM_END
1635
1636 ROM_START(ip2500)
1637 ROM_REGION32_LE(0x80, "idprom", 0)
1638 ROM_LOAD32_BYTE("msmt1000.bin", 0x0, 0x20, CRC(548046c0) SHA1(ce7646e868f3aa35642d7f9348f6b9e91693918e))
1639
1640 ROM_REGION16_LE(0x20000, "eprom", 0)
1641 ROM_SYSTEM_BIOS(0, "ip2500", "InterPro/InterServe 25x0 EPROM")
1642 ROMX_LOAD("ip2500_eprom.bin", 0x00000, 0x20000, NO_DUMP, ROM_BIOS(0))
1643
1644 ROM_REGION(0x20000, "flash_lsb", 0)
1645 ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1646
1647 ROM_REGION(0x20000, "flash_msb", 0)
1648 ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1649 ROM_END
1650
1651 ROM_START(ip2700)
1652 // feature[0] & 0x04: supports RETRY if clear
1653 ROM_REGION32_LE(0x80, "idprom", 0)
1654 ROM_LOAD32_BYTE("msmt1280.bin", 0x0, 0x20, CRC(32d833af) SHA1(7225c5f5670fe49d86556a2cb453ae6fe09e3e19))
1655
1656 ROM_REGION16_LE(0x20000, "eprom", 0)
1657 ROM_SYSTEM_BIOS(0, "ip2700", "InterPro/InterServe 27x0 EPROM")
1658 ROMX_LOAD("mprgz530a__9405181.u35", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(0))
1659
1660 ROM_REGION(0x20000, "flash_lsb", 0)
1661 ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1662
1663 ROM_REGION(0x20000, "flash_msb", 0)
1664 ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1665 ROM_END
1666
1667 ROM_START(ip2800)
1668 ROM_REGION32_LE(0x80, "idprom", 0)
1669 ROM_LOAD32_BYTE("msmt1450.bin", 0x0, 0x20, CRC(61c7a305) SHA1(efcd045cbdfda8df44eaad761b0ba99367973cd7))
1670
1671 ROM_REGION16_LE(0x20000, "eprom", 0)
1672 ROM_SYSTEM_BIOS(0, "ip2800", "InterPro/InterServe 28x0 EPROM")
1673 ROMX_LOAD("ip2800_eprom.bin", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(0))
1674
1675 ROM_REGION(0x20000, "flash_lsb", 0)
1676 ROM_LOAD_OPTIONAL("y225.u76", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1677
1678 ROM_REGION(0x20000, "flash_msb", 0)
1679 ROM_LOAD_OPTIONAL("y226.u67", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1680 ROM_END
1681
1682 ROM_START(ip6000)
1683 ROM_REGION32_LE(0x80, "nodeid", 0)
1684 ROM_LOAD32_BYTE("nodeid.bin", 0x0, 0x20, CRC(a38397a6) SHA1(9f45fb932bbe231c95b3d5470dcd1fa1c846486f))
1685
1686 // feature[0] & 0x01: 1/4 bus clock if clear
1687 // feature[0] & 0x02: configurable console port if clear
1688 ROM_REGION32_LE(0x80, "idprom", 0)
1689 ROM_LOAD32_BYTE("mpcb765b.bin", 0x0, 0x20, CRC(6da05794) SHA1(fef8a9c17491f3d3ceb35c56a628f47d49166b57))
1690
1691 ROM_REGION16_LE(0x40000, "eprom", 0)
1692 ROM_SYSTEM_BIOS(0, "ip6000", "InterPro/InterServe 60x0 EPROM")
1693 ROMX_LOAD("mprgg360f__04_may_90v.u336", 0x00001, 0x20000, CRC(9e8b798b) SHA1(54412e26a468e038fb44ffa322ed3ddfae423c17), ROM_SKIP(1) | ROM_BIOS(0))
1694 ROMX_LOAD("mprgg350f__04_may_90v.u349", 0x00000, 0x20000, CRC(32ab99fd) SHA1(202a6082bade8a084b8cd25109daff8443f6a5c7), ROM_SKIP(1) | ROM_BIOS(0))
1695 ROM_END
1696
1697 ROM_START(ip6400)
1698 ROM_REGION32_LE(0x80, "idprom", 0)
1699 ROM_LOAD32_BYTE("msmt046b.bin", 0x0, 0x20, CRC(3e8ffc77) SHA1(719a3f8b01bb506c9cb876506d63d167550bcd0a))
1700
1701 // FIXME: use 2400 eprom until we have a 6400 dump
1702 ROM_REGION16_LE(0x20000, "eprom", 0)
1703 ROM_SYSTEM_BIOS(0, "ip6400", "InterPro/InterServe 64x0 EPROM")
1704 ROMX_LOAD("ip6400_eprom.bin", 0x00000, 0x20000, BAD_DUMP CRC(3b2c4545) SHA1(4e4c98d1cd1035a04be8527223f44d0b687ec3ef), ROM_BIOS(0))
1705
1706 ROM_REGION(0x20000, "flash_lsb", 0)
1707 ROM_LOAD_OPTIONAL("flash.lsb", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1708
1709 ROM_REGION(0x20000, "flash_msb", 0)
1710 ROM_LOAD_OPTIONAL("flash.msb", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1711 ROM_END
1712
1713 ROM_START(ip6700)
1714 ROM_REGION32_LE(0x80, "idprom", 0)
1715 ROM_LOAD32_BYTE("msmt127b.bin", 0x0, 0x20, CRC(cc112f65) SHA1(8533a31b4733fd91bb87effcd276fc93f2858629))
1716
1717 ROM_REGION16_LE(0x20000, "eprom", 0)
1718 ROM_SYSTEM_BIOS(0, "ip6700", "InterPro/InterServe 67x0 EPROM")
1719 ROMX_LOAD("mprgz530a.u144", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(0))
1720
1721 ROM_REGION(0x20000, "flash_lsb", 0)
1722 ROM_LOAD_OPTIONAL("y225.u117", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1723
1724 ROM_REGION(0x20000, "flash_msb", 0)
1725 ROM_LOAD_OPTIONAL("y226.u130", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1726 ROM_END
1727
1728 ROM_START(ip6800)
1729 ROM_REGION32_LE(0x80, "idprom", 0)
1730 ROM_LOAD32_BYTE("msmt127b.bin", 0x0, 0x20, CRC(cc112f65) SHA1(8533a31b4733fd91bb87effcd276fc93f2858629))
1731
1732 ROM_REGION16_LE(0x20000, "eprom", 0)
1733 ROM_SYSTEM_BIOS(0, "ip6800", "InterPro/InterServe 68x0 EPROM")
1734 ROMX_LOAD("mprgz530a__9406270.u144", 0x00000, 0x20000, CRC(467ce7bd) SHA1(53faee40d5df311f53b24c930e434cbf94a5c4aa), ROM_BIOS(0))
1735
1736 ROM_REGION(0x20000, "flash_lsb", 0)
1737 ROM_LOAD_OPTIONAL("y225.u117", 0x00000, 0x20000, CRC(46c0b105) SHA1(7c4a104e4fb3d0e5e8db7c911cdfb3f5c4fb0218))
1738
1739 ROM_REGION(0x20000, "flash_msb", 0)
1740 ROM_LOAD_OPTIONAL("y226.u130", 0x00000, 0x20000, CRC(54d95730) SHA1(a4e114dee1567d8aa31eed770f7cc366588f395c))
1741 ROM_END
1742
1743 }
1744
1745 /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
1746 COMP( 1990, ip2000, 0, 0, ip2000, 0, turquoise_state, init_common,"Intergraph", "InterPro/InterServe 20x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1747 COMP( 1992, ip2400, 0, 0, ip2400, 0, cbus_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 24x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1748 COMP( 1993, ip2500, 0, 0, ip2500, 0, cbus_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 25x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1749 COMP( 1993, ip2700, 0, 0, ip2700, 0, cbus_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 27x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1750 COMP( 1994, ip2800, 0, 0, ip2800, 0, cbus_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 28x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1751 COMP( 1990, ip6000, 0, 0, ip6000, 0, emerald_state, init_common,"Intergraph", "InterPro/InterServe 60x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1752 COMP( 1992, ip6400, 0, 0, ip6400, 0, srx_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 64x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1753 COMP( 1993, ip6700, 0, 0, ip6700, 0, srx_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 67x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1754 COMP( 1993, ip6800, 0, 0, ip6800, 0, srx_sapphire_state, init_common,"Intergraph", "InterPro/InterServe 68x0", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW)
1755