1 // license:GPL-2.0+
2 // copyright-holders:Dirk Best, R. Belmont
3 /***************************************************************************
4
5 Convergent Miniframe
6
7 Preliminary driver by R. Belmont based on unixpc.cpp by Dirk Best & R. Belmont
8
9 ***************************************************************************/
10
11
12 #include "emu.h"
13 #include "cpu/m68000/m68000.h"
14 #include "imagedev/floppy.h"
15 #include "machine/ram.h"
16 #include "machine/wd_fdc.h"
17 #include "machine/bankdev.h"
18 #include "machine/pit8253.h"
19 #include "machine/pic8259.h"
20 #include "screen.h"
21
22 /***************************************************************************
23 DRIVER STATE
24 ***************************************************************************/
25
26 class miniframe_state : public driver_device
27 {
28 public:
miniframe_state(const machine_config & mconfig,device_type type,const char * tag)29 miniframe_state(const machine_config &mconfig, device_type type, const char *tag)
30 : driver_device(mconfig, type, tag)
31 , m_maincpu(*this, "maincpu")
32 , m_ram(*this, RAM_TAG)
33 , m_wd2797(*this, "wd2797")
34 , m_floppy(*this, "wd2797:0:525dd")
35 , m_ramrombank(*this, "ramrombank")
36 , m_mapram(*this, "mapram")
37 { }
38
39 void miniframe(machine_config &config);
40
41 private:
42 required_device<m68010_device> m_maincpu;
43 required_device<ram_device> m_ram;
44 required_device<wd2797_device> m_wd2797;
45 required_device<floppy_image_device> m_floppy;
46 required_device<address_map_bank_device> m_ramrombank;
47
48 uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
49
50 virtual void machine_start() override;
51 virtual void machine_reset() override;
52
53 uint16_t ram_mmu_r(offs_t offset);
54 void ram_mmu_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
55
56 void general_ctrl_w(uint16_t data);
57
58 DECLARE_WRITE_LINE_MEMBER( wd2797_intrq_w );
59 DECLARE_WRITE_LINE_MEMBER( wd2797_drq_w );
60
61 required_shared_ptr<uint16_t> m_mapram;
62
63 void miniframe_mem(address_map &map);
64 void ramrombank_map(address_map &map);
65
66 uint16_t *m_ramptr;
67 uint32_t m_ramsize;
68 uint16_t m_diskdmasize;
69 uint32_t m_diskdmaptr;
70 bool m_fdc_intrq;
71 };
72
73
74 /***************************************************************************
75 MEMORY
76 ***************************************************************************/
77
78 static constexpr unsigned MMU_MAX_PAGES = 1024;
79 static constexpr uint16_t MMU_WRITE_ENABLE = 0x8000;
80 static constexpr uint16_t MMU_STATUS_MASK = 0x6000;
81 static constexpr uint16_t MMU_STATUS_NOT_PRESENT = 0x0000;
82 static constexpr uint16_t MMU_STATUS_PRESENT_NOT_ACCESSED = 0x2000;
83 static constexpr uint16_t MMU_STATUS_ACCESSED_NOT_WRITTEN = 0x4000;
84 static constexpr uint16_t MMU_STATUS_ACCESSED_WRITTEN = 0x6000;
85
ram_mmu_r(offs_t offset)86 uint16_t miniframe_state::ram_mmu_r(offs_t offset)
87 {
88 uint8_t fc = m_maincpu->get_fc();
89 uint16_t mapentry = m_mapram[(offset >> 11) & 0x7ff];
90
91 if ((offset < ((512*1024)>>1)) && (fc != M68K_FC_SUPERVISOR_DATA) && (fc != M68K_FC_SUPERVISOR_PROGRAM))
92 {
93 fatalerror("mmu: user mode access to lower 512K, need to generate a fault\n");
94 }
95
96 if ((mapentry & MMU_STATUS_MASK) != MMU_STATUS_NOT_PRESENT)
97 {
98 uint32_t addr = (offset & 0x7ff) | ((mapentry & 0xfff) << 11);
99 //printf("mmu_r: orig %x entry %04x xlate %x\n", offset, mapentry, addr);
100
101 // indicate page has been read
102 if ((mapentry & MMU_STATUS_MASK) == MMU_STATUS_PRESENT_NOT_ACCESSED)
103 {
104 m_mapram[(offset >> 11) & 0x7ff] &= ~MMU_STATUS_MASK;
105 m_mapram[(offset >> 11) & 0x7ff] |= MMU_STATUS_ACCESSED_NOT_WRITTEN;
106 }
107
108 return m_ramptr[addr];
109 }
110 else
111 {
112 fatalerror("miniframe: invalid MMU page accessed, need to throw a fault\n");
113 }
114 }
115
ram_mmu_w(offs_t offset,uint16_t data,uint16_t mem_mask)116 void miniframe_state::ram_mmu_w(offs_t offset, uint16_t data, uint16_t mem_mask)
117 {
118 uint8_t fc = m_maincpu->get_fc();
119 uint16_t mapentry = m_mapram[(offset >> 11) & 0x7ff];
120
121 if ((offset < ((512*1024)>>1)) && (fc != M68K_FC_SUPERVISOR_DATA) && (fc != M68K_FC_SUPERVISOR_PROGRAM))
122 {
123 fatalerror("mmu: user mode access to lower 512K, need to generate a fault\n");
124 }
125
126 if ((mapentry & MMU_STATUS_MASK) != MMU_STATUS_NOT_PRESENT)
127 {
128 uint32_t addr = (offset & 0x7ff) | ((mapentry & 0xfff) << 11);
129 //printf("mmu_w: orig %x entry %04x xlate %x\n", offset, mapentry, addr);
130
131 if (!(mapentry & MMU_WRITE_ENABLE) && (fc != M68K_FC_SUPERVISOR_PROGRAM) && (fc != M68K_FC_SUPERVISOR_DATA))
132 {
133 fatalerror("mmu: write protection violation, need to throw a fault\n");
134 }
135
136 // indicate page has been written
137 // we know it's OK to just OR this
138 m_mapram[(offset >> 11) & 0x7ff] |= MMU_STATUS_ACCESSED_WRITTEN;
139
140 COMBINE_DATA(&m_ramptr[addr]);
141 }
142 else
143 {
144 fatalerror("miniframe: invalid MMU page accessed, need to throw a fault\n");
145 }
146 }
147
general_ctrl_w(uint16_t data)148 void miniframe_state::general_ctrl_w(uint16_t data)
149 {
150 if (data & 0x1000) // ROM mirror at 0 if set
151 {
152 m_ramrombank->set_bank(1);
153 }
154 else
155 {
156 m_ramrombank->set_bank(0);
157 }
158
159 logerror("%x to general_ctrl_w\n", data);
160 }
161
machine_start()162 void miniframe_state::machine_start()
163 {
164 m_ramptr = (uint16_t *)m_ram->pointer();
165 m_ramsize = m_ram->size();
166 }
167
machine_reset()168 void miniframe_state::machine_reset()
169 {
170 // force ROM into lower mem on reset
171 m_ramrombank->set_bank(0);
172
173 // invalidate all pages by clearing all entries
174 memset(m_mapram, 0, MMU_MAX_PAGES * sizeof(uint16_t));
175 }
176
177 /***************************************************************************
178 VIDEO
179 ***************************************************************************/
180
screen_update(screen_device & screen,bitmap_ind16 & bitmap,const rectangle & cliprect)181 uint32_t miniframe_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
182 {
183 return 0;
184 }
185
186
187 /***************************************************************************
188 ADDRESS MAPS
189 ***************************************************************************/
190
miniframe_mem(address_map & map)191 void miniframe_state::miniframe_mem(address_map &map)
192 {
193 map(0x000000, 0x3fffff).m(m_ramrombank, FUNC(address_map_bank_device::amap16));
194 map(0x400000, 0x4007ff).ram().share("mapram");
195 map(0x450000, 0x450001).w(FUNC(miniframe_state::general_ctrl_w));
196 map(0x800000, 0x81ffff).rom().region("bootrom", 0);
197 map(0xc00000, 0xc00007).rw("pit8253", FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
198 map(0xc40000, 0xc40007).rw("baudgen", FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
199 map(0xc90000, 0xc90003).rw("pic8259", FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
200 }
201
ramrombank_map(address_map & map)202 void miniframe_state::ramrombank_map(address_map &map)
203 {
204 map(0x000000, 0x3fffff).rom().region("bootrom", 0);
205 map(0x400000, 0x7fffff).rw(FUNC(miniframe_state::ram_mmu_r), FUNC(miniframe_state::ram_mmu_w));
206 }
207
208 /***************************************************************************
209 INPUT PORTS
210 ***************************************************************************/
211
INPUT_PORTS_START(miniframe)212 static INPUT_PORTS_START( miniframe )
213 INPUT_PORTS_END
214
215
216 /***************************************************************************
217 MACHINE DRIVERS
218 ***************************************************************************/
219
220 static void miniframe_floppies(device_slot_interface &device)
221 {
222 device.option_add("525dd", FLOPPY_525_DD);
223 }
224
miniframe(machine_config & config)225 void miniframe_state::miniframe(machine_config &config)
226 {
227 // basic machine hardware
228 M68010(config, m_maincpu, XTAL(10'000'000));
229 m_maincpu->set_addrmap(AS_PROGRAM, &miniframe_state::miniframe_mem);
230
231 // internal ram
232 RAM(config, RAM_TAG).set_default_size("1M").set_extra_options("2M");
233
234 // RAM/ROM bank
235 ADDRESS_MAP_BANK(config, "ramrombank").set_map(&miniframe_state::ramrombank_map).set_options(ENDIANNESS_BIG, 16, 32, 0x400000);
236
237 // floppy
238 WD2797(config, m_wd2797, 1000000);
239 // m_wd2797->intrq_wr_callback().set(FUNC(miniframe_state::wd2797_intrq_w));
240 // m_wd2797->drq_wr_callback().set(FUNC(miniframe_state::wd2797_drq_w));
241 FLOPPY_CONNECTOR(config, "wd2797:0", miniframe_floppies, "525dd", floppy_image_device::default_floppy_formats);
242
243 // 8263s
244 pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
245 pit8253.set_clk<0>(76800);
246 pit8253.set_clk<1>(76800);
247 pit8253.out_handler<0>().set("pic8259", FUNC(pic8259_device::ir4_w)); // FIXME: fighting for IR4 - error, or needs input merger?
248 // chain clock 1 output into clock 2
249 pit8253.out_handler<1>().set("pit8253", FUNC(pit8253_device::write_clk2));
250 // and ir4 on the PIC
251 pit8253.out_handler<1>().append("pic8259", FUNC(pic8259_device::ir4_w));
252
253 pit8253_device &baudgen(PIT8253(config, "baudgen", 0));
254 baudgen.set_clk<0>(1228800);
255 baudgen.set_clk<1>(1228800);
256 baudgen.set_clk<2>(1228800);
257
258 // PIC8259s
259 pic8259_device &pic8259(PIC8259(config, "pic8259", 0));
260 pic8259.out_int_callback().set_inputline(m_maincpu, M68K_IRQ_4);
261 pic8259.in_sp_callback().set_constant(1);
262 }
263
264
265 /***************************************************************************
266 ROM DEFINITIONS
267 ***************************************************************************/
268
269 ROM_START( minifram )
270 ROM_REGION16_BE(0x400000, "bootrom", 0)
271 ROM_LOAD16_BYTE("72-00357.bin", 0x000001, 0x002000, CRC(17c2749c) SHA1(972b5300b4d6ec65536910eab2b8550b9df9bb4d))
272 ROM_LOAD16_BYTE("72-00356.bin", 0x000000, 0x002000, CRC(28b6c23a) SHA1(479e739a8154b6754e2e9b1fcfeb99d6ceaf9dbe))
273 ROM_END
274
275
276 /***************************************************************************
277 GAME DRIVERS
278 ***************************************************************************/
279
280 // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
281 COMP( 1985, minifram, 0, 0, miniframe, miniframe, miniframe_state, empty_init, "Convergent", "Miniframe", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
282