1 // license:BSD-3-Clause 2 // copyright-holders:Ernesto Corvi, Mariusz Wojcieszek 3 /*************************************************************************** 4 Amiga Computer / Arcadia Game System 5 6 Driver by: 7 8 Ernesto Corvi & Mariusz Wojcieszek 9 10 ***************************************************************************/ 11 12 #ifndef MAME_INCLUDES_AMIGA_H 13 #define MAME_INCLUDES_AMIGA_H 14 15 #pragma once 16 17 #include "cpu/m68000/m68000.h" 18 #include "machine/bankdev.h" 19 #include "bus/rs232/rs232.h" 20 #include "bus/centronics/ctronics.h" 21 #include "machine/mos6526.h" 22 #include "machine/amigafdc.h" 23 #include "machine/msm6242.h" 24 #include "machine/akiko.h" 25 #include "machine/i2cmem.h" 26 #include "machine/8364_paula.h" 27 #include "video/amigaaga.h" 28 #include "emupal.h" 29 #include "screen.h" 30 31 32 /* 33 A = Angus 34 D = Denise 35 P = Paula 36 37 R = read-only 38 ER = early read 39 W = write-only 40 S = strobe 41 */ 42 #define REG_BLTDDAT (0x000/2) /* ER A Blitter destination early read (dummy address) */ 43 #define REG_DMACONR (0x002/2) /* R A P DMA control (and blitter status) read */ 44 #define REG_VPOSR (0x004/2) /* R A Read vert most signif. bit (and frame flop) */ 45 #define REG_VHPOSR (0x006/2) /* R A Read vert and horiz. position of beam */ 46 #define REG_DSKDATR (0x008/2) /* ER P Disk data early read (dummy address) */ 47 #define REG_JOY0DAT (0x00A/2) /* R D Joystick-mouse 0 data (vert,horiz) */ 48 #define REG_JOY1DAT (0x00C/2) /* R D Joystick-mouse 1 data (vert,horiz) */ 49 #define REG_CLXDAT (0x00E/2) /* R D Collision data register (read and clear) */ 50 #define REG_ADKCONR (0x010/2) /* R P Audio, disk control register read */ 51 #define REG_POT0DAT (0x012/2) /* R P Pot counter pair 0 data (vert,horiz) */ 52 #define REG_POT1DAT (0x014/2) /* R P Pot counter pair 1 data (vert,horiz) */ 53 #define REG_POTGOR (0x016/2) /* R P Pot port data read (formerly POTINP) */ 54 #define REG_SERDATR (0x018/2) /* R P Serial port data and status read */ 55 #define REG_DSKBYTR (0x01A/2) /* R P Disk data byte and status read */ 56 #define REG_INTENAR (0x01C/2) /* R P Interrupt enable bits read */ 57 #define REG_INTREQR (0x01E/2) /* R P Interrupt request bits read */ 58 #define REG_DSKPTH (0x020/2) /* W A Disk pointer (high 3 bits) */ 59 #define REG_DSKPTL (0x022/2) /* W A Disk pointer (low 15 bits) */ 60 #define REG_DSKLEN (0x024/2) /* W P Disk length */ 61 #define REG_DSKDAT (0x026/2) /* W P Disk DMA data write */ 62 #define REG_REFPTR (0x028/2) /* W A Refresh pointer */ 63 #define REG_VPOSW (0x02A/2) /* W A Write vert most signif. bit (and frame flop) */ 64 #define REG_VHPOSW (0x02C/2) /* W A Write vert and horiz position of beam */ 65 #define REG_COPCON (0x02E/2) /* W A Coprocessor control register (CDANG) */ 66 #define REG_SERDAT (0x030/2) /* W P Serial port data and stop bits write */ 67 #define REG_SERPER (0x032/2) /* W P Serial port period and control */ 68 #define REG_POTGO (0x034/2) /* W P Pot port data write and start */ 69 #define REG_JOYTEST (0x036/2) /* W D Write to all 4 joystick-mouse counters at once */ 70 #define REG_STREQU (0x038/2) /* S D Strobe for horiz sync with VB and EQU */ 71 #define REG_STRVBL (0x03A/2) /* S D Strobe for horiz sync with VB (vert. blank) */ 72 #define REG_STRHOR (0x03C/2) /* S D P Strobe for horiz sync */ 73 #define REG_STRLONG (0x03E/2) /* S D Strobe for identification of long horiz. line. */ 74 #define REG_BLTCON0 (0x040/2) /* W A Blitter control register 0 */ 75 #define REG_BLTCON1 (0x042/2) /* W A Blitter control register 1 */ 76 #define REG_BLTAFWM (0x044/2) /* W A Blitter first word mask for source A */ 77 #define REG_BLTALWM (0x046/2) /* W A Blitter last word mask for source A */ 78 #define REG_BLTCPTH (0x048/2) /* W A Blitter pointer to source C (high 3 bits) */ 79 #define REG_BLTCPTL (0x04A/2) /* W A Blitter pointer to source C (low 15 bits) */ 80 #define REG_BLTBPTH (0x04C/2) /* W A Blitter pointer to source B (high 3 bits) */ 81 #define REG_BLTBPTL (0x04E/2) /* W A Blitter pointer to source B (low 15 bits) */ 82 #define REG_BLTAPTH (0x050/2) /* W A Blitter pointer to source A (high 3 bits) */ 83 #define REG_BLTAPTL (0x052/2) /* W A Blitter pointer to source A (low 15 bits) */ 84 #define REG_BLTDPTH (0x054/2) /* W A Blitter pointer to destination D (high 3 bits) */ 85 #define REG_BLTDPTL (0x056/2) /* W A Blitter pointer to destination D (low 15 bits) */ 86 #define REG_BLTSIZE (0x058/2) /* W A Blitter start and size (window width, height) */ 87 #define REG_BLTCON0L (0x05A/2) /* W A Blitter control 0, lower 8 bits (minterms) */ 88 #define REG_BLTSIZV (0x05C/2) /* W A Blitter V size (for 15 bit vertical size) (ECS) */ 89 #define REG_BLTSIZH (0x05E/2) /* W A Blitter H size and start (for 11 bit H size) (ECS) */ 90 #define REG_BLTCMOD (0x060/2) /* W A Blitter modulo for source C */ 91 #define REG_BLTBMOD (0x062/2) /* W A Blitter modulo for source B */ 92 #define REG_BLTAMOD (0x064/2) /* W A Blitter modulo for source A */ 93 #define REG_BLTDMOD (0x066/2) /* W A Blitter modulo for destination D */ 94 #define REG_BLTCDAT (0x070/2) /* W A Blitter source C data register */ 95 #define REG_BLTBDAT (0x072/2) /* W A Blitter source B data reglster */ 96 #define REG_BLTADAT (0x074/2) /* W A Blitter source A data register */ 97 #define REG_DENISEID (0x07C/2) /* R D Denise ID: OCS = 0xFF, ECS = 0xFC, AGA = 0xF8 */ 98 #define REG_DSKSYNC (0x07E/2) /* W P Disk sync pattern register for disk read */ 99 #define REG_COP1LCH (0x080/2) /* W A Coprocessor first location register (high 3 bits) */ 100 #define REG_COP1LCL (0x082/2) /* W A Coprocessor first location register (low 15 bits) */ 101 #define REG_COP2LCH (0x084/2) /* W A Coprocessor second location register (high 3 bits) */ 102 #define REG_COP2LCL (0x086/2) /* W A Coprocessor second location register (low 15 bits) */ 103 #define REG_COPJMP1 (0x088/2) /* S A Coprocessor restart at first location */ 104 #define REG_COPJMP2 (0x08A/2) /* S A Coprocessor restart at second location */ 105 #define REG_COPINS (0x08C/2) /* W A Coprocessor instruction fetch identify */ 106 #define REG_DIWSTRT (0x08E/2) /* W A Display window start (upper left vert-horiz position) */ 107 #define REG_DIWSTOP (0x090/2) /* W A Display window stop (lower right vert.-horiz. position) */ 108 #define REG_DDFSTRT (0x092/2) /* W A Display bit plane data fetch start (horiz. position) */ 109 #define REG_DDFSTOP (0x094/2) /* W A Display bit plane data fetch stop (horiz. position) */ 110 #define REG_DMACON (0x096/2) /* W A D P DMA control write (clear or set) */ 111 #define REG_CLXCON (0x098/2) /* W D Collision control */ 112 #define REG_INTENA (0x09A/2) /* W P Interrupt enable bits (clear or set bits) */ 113 #define REG_INTREQ (0x09C/2) /* W P Interrupt request bits (clear or set bits) */ 114 #define REG_ADKCON (0x09E/2) /* W P Audio, disk, UART control */ 115 #define REG_AUD0LCH (0x0A0/2) /* W A Audio channel 0 location (high 3 bits) */ 116 #define REG_AUD0LCL (0x0A2/2) /* W A Audio channel 0 location (low 15 bits) */ 117 #define REG_AUD0LEN (0x0A4/2) /* W P Audio channel 0 length */ 118 #define REG_AUD0PER (0x0A6/2) /* W P Audio channel 0 period */ 119 #define REG_AUD0VOL (0x0A8/2) /* W P Audio channel 0 volume */ 120 #define REG_AUD0DAT (0x0AA/2) /* W P Audio channel 0 data */ 121 #define REG_AUD1LCH (0x0B0/2) /* W A Audio channel 1 location (high 3 bits) */ 122 #define REG_AUD1LCL (0x0B2/2) /* W A Audio channel 1 location (low 15 bits) */ 123 #define REG_AUD1LEN (0x0B4/2) /* W P Audio channel 1 length */ 124 #define REG_AUD1PER (0x0B6/2) /* W P Audio channel 1 period */ 125 #define REG_AUD1VOL (0x0B8/2) /* W P Audio channel 1 volume */ 126 #define REG_AUD1DAT (0x0BA/2) /* W P Audio channel 1 data */ 127 #define REG_AUD2LCH (0x0C0/2) /* W A Audio channel 2 location (high 3 bits) */ 128 #define REG_AUD2LCL (0x0C2/2) /* W A Audio channel 2 location (low 15 bits) */ 129 #define REG_AUD2LEN (0x0C4/2) /* W P Audio channel 2 length */ 130 #define REG_AUD2PER (0x0C6/2) /* W P Audio channel 2 period */ 131 #define REG_AUD2VOL (0x0C8/2) /* W P Audio channel 2 volume */ 132 #define REG_AUD2DAT (0x0CA/2) /* W P Audio channel 2 data */ 133 #define REG_AUD3LCH (0x0D0/2) /* W A Audio channel 3 location (high 3 bits) */ 134 #define REG_AUD3LCL (0x0D2/2) /* W A Audio channel 3 location (low 15 bits) */ 135 #define REG_AUD3LEN (0x0D4/2) /* W P Audio channel 3 length */ 136 #define REG_AUD3PER (0x0D6/2) /* W P Audio channel 3 period */ 137 #define REG_AUD3VOL (0x0D8/2) /* W P Audio channel 3 volume */ 138 #define REG_AUD3DAT (0x0DA/2) /* W P Audio channel 3 data */ 139 #define REG_BPL1PTH (0x0E0/2) /* W A Bit plane 1 pointer (high 3 bits) */ 140 #define REG_BPL1PTL (0x0E2/2) /* W A Bit plane 1 pointer (low 15 bits) */ 141 #define REG_BPL2PTH (0x0E4/2) /* W A Bit plane 2 pointer (high 3 bits) */ 142 #define REG_BPL2PTL (0x0E6/2) /* W A Bit plane 2 pointer (low 15 bits) */ 143 #define REG_BPL3PTH (0x0E8/2) /* W A Bit plane 3 pointer (high 3 bits) */ 144 #define REG_BPL3PTL (0x0EA/2) /* W A Bit plane 3 pointer (low 15 bits) */ 145 #define REG_BPL4PTH (0x0EC/2) /* W A Bit plane 4 pointer (high 3 bits) */ 146 #define REG_BPL4PTL (0x0EE/2) /* W A Bit plane 4 pointer (low 15 bits) */ 147 #define REG_BPL5PTH (0x0F0/2) /* W A Bit plane 5 pointer (high 3 bits) */ 148 #define REG_BPL5PTL (0x0F2/2) /* W A Bit plane 5 pointer (low 15 bits) */ 149 #define REG_BPL6PTH (0x0F4/2) /* W A Bit plane 6 pointer (high 3 bits) */ 150 #define REG_BPL6PTL (0x0F6/2) /* W A Bit plane 6 pointer (low 15 bits) */ 151 #define REG_BPLCON0 (0x100/2) /* W A D Bit plane control register (misc. control bits) */ 152 #define REG_BPLCON1 (0x102/2) /* W D Bit plane control reg. (scroll value PF1, PF2) */ 153 #define REG_BPLCON2 (0x104/2) /* W D Bit plane control reg. (priority control) */ 154 #define REG_BPLCON3 (0x106/2) /* W D Bit plane control reg (enhanced features) */ 155 #define REG_BPL1MOD (0x108/2) /* W A Bit plane modulo (odd planes) */ 156 #define REG_BPL2MOD (0x10A/2) /* W A Bit Plane modulo (even planes) */ 157 #define REG_BPLCON4 (0x10C/2) /* W D Bit plane control reg. (display masks) */ 158 #define REG_BPL1DAT (0x110/2) /* W D Bit plane 1 data (parallel-to-serial convert) */ 159 #define REG_BPL2DAT (0x112/2) /* W D Bit plane 2 data (parallel-to-serial convert) */ 160 #define REG_BPL3DAT (0x114/2) /* W D Bit plane 3 data (parallel-to-serial convert) */ 161 #define REG_BPL4DAT (0x116/2) /* W D Bit plane 4 data (parallel-to-serial convert) */ 162 #define REG_BPL5DAT (0x118/2) /* W D Bit plane 5 data (parallel-to-serial convert) */ 163 #define REG_BPL6DAT (0x11A/2) /* W D Bit plane 6 data (parallel-to-serial convert) */ 164 #define REG_BPL7DAT (0x11C/2) /* W D Bit plane 7 data (parallel-to-serial convert) */ 165 #define REG_BPL8DAT (0x11E/2) /* W D Bit plane 8 data (parallel-to-serial convert) */ 166 #define REG_SPR0PTH (0x120/2) /* W A Sprite 0 pointer (high 3 bits) */ 167 #define REG_SPR0PTL (0x122/2) /* W A Sprite 0 pointer (low 15 bits) */ 168 #define REG_SPR1PTH (0x124/2) /* W A Sprite 1 pointer (high 3 bits) */ 169 #define REG_SPR1PTL (0x126/2) /* W A Sprite 1 pointer (low 15 bits) */ 170 #define REG_SPR2PTH (0x128/2) /* W A Sprite 2 pointer (high 3 bits) */ 171 #define REG_SPR2PTL (0x12A/2) /* W A Sprite 2 pointer (low 15 bits) */ 172 #define REG_SPR3PTH (0x12C/2) /* W A Sprite 3 pointer (high 3 bits) */ 173 #define REG_SPR3PTL (0x12E/2) /* W A Sprite 3 pointer (low 15 bits) */ 174 #define REG_SPR4PTH (0x130/2) /* W A Sprite 4 pointer (high 3 bits) */ 175 #define REG_SPR4PTL (0x132/2) /* W A Sprite 4 pointer (low 15 bits) */ 176 #define REG_SPR5PTH (0x134/2) /* W A Sprite 5 pointer (high 3 bits) */ 177 #define REG_SPR5PTL (0x136/2) /* W A Sprite 5 pointer (low 15 bits) */ 178 #define REG_SPR6PTH (0x138/2) /* W A Sprite 6 pointer (high 3 bits) */ 179 #define REG_SPR6PTL (0x13A/2) /* W A Sprite 6 pointer (low 15 bits) */ 180 #define REG_SPR7PTH (0x13C/2) /* W A Sprite 7 pointer (high 3 bits) */ 181 #define REG_SPR7PTL (0x13E/2) /* W A Sprite 7 pointer (low 15 bits) */ 182 #define REG_SPR0POS (0x140/2) /* W A D Sprite 0 vert-horiz start position data */ 183 #define REG_SPR0CTL (0x142/2) /* W A D Sprite 0 vert stop position and control data */ 184 #define REG_SPR0DATA (0x144/2) /* W D Sprite 0 image data register A */ 185 #define REG_SPR0DATB (0x146/2) /* W D Sprite 0 image data register B */ 186 #define REG_SPR1POS (0x148/2) /* W A D Sprite 1 vert-horiz start position data */ 187 #define REG_SPR1CTL (0x14A/2) /* W A D Sprite 1 vert stop position and control data */ 188 #define REG_SPR1DATA (0x14C/2) /* W D Sprite 1 image data register A */ 189 #define REG_SPR1DATB (0x14E/2) /* W D Sprite 1 image data register B */ 190 #define REG_SPR2POS (0x150/2) /* W A D Sprite 2 vert-horiz start position data */ 191 #define REG_SPR2CTL (0x152/2) /* W A D Sprite 2 vert stop position and control data */ 192 #define REG_SPR2DATA (0x154/2) /* W D Sprite 2 image data register A */ 193 #define REG_SPR2DATB (0x156/2) /* W D Sprite 2 image data register B */ 194 #define REG_SPR3POS (0x158/2) /* W A D Sprite 3 vert-horiz start position data */ 195 #define REG_SPR3CTL (0x15A/2) /* W A D Sprite 3 vert stop position and control data */ 196 #define REG_SPR3DATA (0x15C/2) /* W D Sprite 3 image data register A */ 197 #define REG_SPR3DATB (0x15E/2) /* W D Sprite 3 image data register B */ 198 #define REG_SPR4POS (0x160/2) /* W A D Sprite 4 vert-horiz start position data */ 199 #define REG_SPR4CTL (0x162/2) /* W A D Sprite 4 vert stop position and control data */ 200 #define REG_SPR4DATA (0x164/2) /* W D Sprite 4 image data register A */ 201 #define REG_SPR4DATB (0x166/2) /* W D Sprite 4 image data register B */ 202 #define REG_SPR5POS (0x168/2) /* W A D Sprite 5 vert-horiz start position data */ 203 #define REG_SPR5CTL (0x16A/2) /* W A D Sprite 5 vert stop position and control data */ 204 #define REG_SPR5DATA (0x16C/2) /* W D Sprite 5 image data register A */ 205 #define REG_SPR5DATB (0x16E/2) /* W D Sprite 5 image data register B */ 206 #define REG_SPR6POS (0x170/2) /* W A D Sprite 6 vert-horiz start position data */ 207 #define REG_SPR6CTL (0x172/2) /* W A D Sprite 6 vert stop position and control data */ 208 #define REG_SPR6DATA (0x174/2) /* W D Sprite 6 image data register A */ 209 #define REG_SPR6DATB (0x176/2) /* W D Sprite 6 image data register B */ 210 #define REG_SPR7POS (0x178/2) /* W A D Sprite 7 vert-horiz start position data */ 211 #define REG_SPR7CTL (0x17A/2) /* W A D Sprite 7 vert stop position and control data */ 212 #define REG_SPR7DATA (0x17C/2) /* W D Sprite 7 image data register A */ 213 #define REG_SPR7DATB (0x17E/2) /* W D Sprite 7 image data register B */ 214 #define REG_COLOR00 (0x180/2) /* W D Color table 00 */ 215 #define REG_COLOR01 (0x182/2) /* W D Color table 01 */ 216 #define REG_COLOR02 (0x184/2) /* W D Color table 02 */ 217 #define REG_COLOR03 (0x186/2) /* W D Color table 03 */ 218 #define REG_COLOR04 (0x188/2) /* W D Color table 04 */ 219 #define REG_COLOR05 (0x18A/2) /* W D Color table 05 */ 220 #define REG_COLOR06 (0x18C/2) /* W D Color table 06 */ 221 #define REG_COLOR07 (0x18E/2) /* W D Color table 07 */ 222 #define REG_COLOR08 (0x190/2) /* W D Color table 08 */ 223 #define REG_COLOR09 (0x192/2) /* W D Color table 09 */ 224 #define REG_COLOR10 (0x194/2) /* W D Color table 10 */ 225 #define REG_COLOR11 (0x196/2) /* W D Color table 11 */ 226 #define REG_COLOR12 (0x198/2) /* W D Color table 12 */ 227 #define REG_COLOR13 (0x19A/2) /* W D Color table 13 */ 228 #define REG_COLOR14 (0x19C/2) /* W D Color table 14 */ 229 #define REG_COLOR15 (0x19E/2) /* W D Color table 15 */ 230 #define REG_COLOR16 (0x1A0/2) /* W D Color table 16 */ 231 #define REG_COLOR17 (0x1A2/2) /* W D Color table 17 */ 232 #define REG_COLOR18 (0x1A4/2) /* W D Color table 18 */ 233 #define REG_COLOR19 (0x1A6/2) /* W D Color table 19 */ 234 #define REG_COLOR20 (0x1A8/2) /* W D Color table 20 */ 235 #define REG_COLOR21 (0x1AA/2) /* W D Color table 21 */ 236 #define REG_COLOR22 (0x1AC/2) /* W D Color table 22 */ 237 #define REG_COLOR23 (0x1AE/2) /* W D Color table 23 */ 238 #define REG_COLOR24 (0x1B0/2) /* W D Color table 24 */ 239 #define REG_COLOR25 (0x1B2/2) /* W D Color table 25 */ 240 #define REG_COLOR26 (0x1B4/2) /* W D Color table 26 */ 241 #define REG_COLOR27 (0x1B6/2) /* W D Color table 27 */ 242 #define REG_COLOR28 (0x1B8/2) /* W D Color table 28 */ 243 #define REG_COLOR29 (0x1BA/2) /* W D Color table 29 */ 244 #define REG_COLOR30 (0x1BC/2) /* W D Color table 30 */ 245 #define REG_COLOR31 (0x1BE/2) /* W D Color table 31 */ 246 #define REG_BEAMCON0 (0x1dc/2) // W A Programmable signal generator (ECS Agnus) 247 #define REG_DIWHIGH (0x1E4/2) /* W A D Display window upper bits for start/stop */ 248 #define REG_FMODE (0x1FC/2) /* W A D Fetch mode */ 249 250 /* DMACON bit layout */ 251 #define DMACON_AUD0EN 0x0001 252 #define DMACON_AUD1EN 0x0002 253 #define DMACON_AUD2EN 0x0004 254 #define DMACON_AUD3EN 0x0008 255 #define DMACON_DSKEN 0x0010 256 #define DMACON_SPREN 0x0020 257 #define DMACON_BLTEN 0x0040 258 #define DMACON_COPEN 0x0080 259 #define DMACON_BPLEN 0x0100 260 #define DMACON_DMAEN 0x0200 261 #define DMACON_BLTPRI 0x0400 262 #define DMACON_RSVED1 0x0800 263 #define DMACON_RSVED2 0x1000 264 #define DMACON_BZERO 0x2000 265 #define DMACON_BBUSY 0x4000 266 #define DMACON_SETCLR 0x8000 267 268 /* BPLCON0 bit layout */ 269 #define BPLCON0_RSVED1 0x0001 270 #define BPLCON0_ERSY 0x0002 271 #define BPLCON0_LACE 0x0004 272 #define BPLCON0_LPEN 0x0008 273 #define BPLCON0_BPU3 0x0010 274 #define BPLCON0_RSVED3 0x0020 275 #define BPLCON0_RSVED4 0x0040 276 #define BPLCON0_RSVED5 0x0080 277 #define BPLCON0_GAUD 0x0100 278 #define BPLCON0_COLOR 0x0200 279 #define BPLCON0_DBLPF 0x0400 280 #define BPLCON0_HOMOD 0x0800 281 #define BPLCON0_BPU0 0x1000 282 #define BPLCON0_BPU1 0x2000 283 #define BPLCON0_BPU2 0x4000 284 #define BPLCON0_HIRES 0x8000 285 286 /* INTENA/INTREQ bit layout */ 287 #define INTENA_TBE 0x0001 288 #define INTENA_DSKBLK 0x0002 289 #define INTENA_SOFT 0x0004 290 #define INTENA_PORTS 0x0008 291 #define INTENA_COPER 0x0010 292 #define INTENA_VERTB 0x0020 293 #define INTENA_BLIT 0x0040 294 #define INTENA_AUD0 0x0080 295 #define INTENA_AUD1 0x0100 296 #define INTENA_AUD2 0x0200 297 #define INTENA_AUD3 0x0400 298 #define INTENA_RBF 0x0800 299 #define INTENA_DSKSYN 0x1000 300 #define INTENA_EXTER 0x2000 301 #define INTENA_INTEN 0x4000 302 #define INTENA_SETCLR 0x8000 303 304 #define MAX_PLANES 6 /* 0 to 6, inclusive ( but we count from 0 to 5 ) */ 305 306 307 class amiga_state : public driver_device 308 { 309 public: amiga_state(const machine_config & mconfig,device_type type,const char * tag)310 amiga_state(const machine_config &mconfig, device_type type, const char *tag) : 311 driver_device(mconfig, type, tag), 312 m_agnus_id(AGNUS_NTSC), 313 m_denise_id(DENISE), 314 m_maincpu(*this, "maincpu"), 315 m_cia_0(*this, "cia_0"), 316 m_cia_1(*this, "cia_1"), 317 m_rs232(*this, "rs232"), 318 m_centronics(*this, "centronics"), 319 m_paula(*this, "amiga"), 320 m_fdc(*this, "fdc"), 321 m_screen(*this, "screen"), 322 m_palette(*this, "palette"), 323 m_overlay(*this, "overlay"), 324 m_input_device(*this, "input"), 325 m_joy0dat_port(*this, "joy_0_dat"), 326 m_joy1dat_port(*this, "joy_1_dat"), 327 m_potgo_port(*this, "potgo"), 328 m_pot0dat_port(*this, "POT0DAT"), 329 m_pot1dat_port(*this, "POT1DAT"), 330 m_joy_ports(*this, "p%u_joy", 1), 331 m_p1_mouse_x(*this, "p1_mouse_x"), 332 m_p1_mouse_y(*this, "p1_mouse_y"), 333 m_p2_mouse_x(*this, "p2_mouse_x"), 334 m_p2_mouse_y(*this, "p2_mouse_y"), 335 m_hvpos(*this, "HVPOS"), 336 m_power_led(*this, "power_led"), 337 m_chip_ram_mask(0), 338 m_cia_0_irq(0), 339 m_cia_1_irq(0), 340 m_pot0x(0), m_pot1x(0), m_pot0y(0), m_pot1y(0), 341 m_pot0dat(0x0000), 342 m_pot1dat(0x0000), 343 m_centronics_busy(0), 344 m_centronics_perror(0), 345 m_centronics_select(0), 346 m_gayle_reset(false), 347 m_diw(), 348 m_diwhigh_valid(false), 349 m_previous_lof(true), 350 m_rx_shift(0), 351 m_tx_shift(0), 352 m_rx_state(0), 353 m_tx_state(0), 354 m_rx_previous(1) 355 { } 356 357 /* chip RAM access */ read_chip_ram(offs_t byteoffs)358 uint16_t read_chip_ram(offs_t byteoffs) 359 { 360 return EXPECTED(byteoffs < m_chip_ram.bytes()) ? m_chip_ram.read(byteoffs >> 1) : 0xffff; 361 } 362 write_chip_ram(offs_t byteoffs,uint16_t data)363 void write_chip_ram(offs_t byteoffs, uint16_t data) 364 { 365 if (EXPECTED(byteoffs < m_chip_ram.bytes())) 366 m_chip_ram.write(byteoffs >> 1, data); 367 } 368 369 uint16_t chip_ram_r(offs_t offset, uint16_t mem_mask = ~0) 370 { 371 return read_chip_ram(offset & ~1) & mem_mask; 372 } 373 374 void chip_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0) 375 { 376 uint16_t val = read_chip_ram(offset & ~1) & ~mem_mask; 377 write_chip_ram(offset & ~1, val | data); 378 } 379 380 /* sprite states */ 381 uint8_t m_sprite_comparitor_enable_mask; 382 uint8_t m_sprite_dma_reload_mask; 383 uint8_t m_sprite_dma_live_mask; 384 uint8_t m_sprite_ctl_written; 385 uint32_t m_sprite_shiftreg[8]; 386 uint8_t m_sprite_remain[8]; 387 388 /* copper states */ 389 uint32_t m_copper_pc; 390 uint8_t m_copper_waiting; 391 uint8_t m_copper_waitblit; 392 uint16_t m_copper_waitval; 393 uint16_t m_copper_waitmask; 394 uint16_t m_copper_pending_offset; 395 uint16_t m_copper_pending_data; 396 int m_wait_offset; 397 398 /* playfield states */ 399 int m_last_scanline; 400 rgb_t m_ham_color; 401 402 /* misc states */ 403 uint16_t m_genlock_color; 404 405 /* separate 6 in-order bitplanes into 2 x 3-bit bitplanes in two nibbles */ 406 uint8_t m_separate_bitplanes[2][64]; 407 408 /* aga */ 409 int m_aga_diwhigh_written; 410 rgb_t m_aga_palette[256]; 411 uint64_t m_aga_bpldat[8]; 412 uint16_t m_aga_sprdata[8][4]; 413 uint16_t m_aga_sprdatb[8][4]; 414 int m_aga_sprite_fetched_words; 415 int m_aga_sprite_dma_used_words[8]; 416 417 DECLARE_VIDEO_START( amiga ); 418 DECLARE_VIDEO_START( amiga_aga ); 419 void amiga_palette(palette_device &palette) const; 420 421 uint32_t screen_update_amiga(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 422 uint32_t screen_update_amiga_aga(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 423 void update_screenmode(); 424 425 TIMER_CALLBACK_MEMBER( scanline_callback ); 426 TIMER_CALLBACK_MEMBER (amiga_irq_proc ); 427 TIMER_CALLBACK_MEMBER( amiga_blitter_proc ); 428 void update_irqs(); 429 430 template <int P> DECLARE_CUSTOM_INPUT_MEMBER( amiga_joystick_convert ); 431 DECLARE_CUSTOM_INPUT_MEMBER( floppy_drive_status ); 432 433 DECLARE_WRITE_LINE_MEMBER( m68k_reset ); 434 DECLARE_WRITE_LINE_MEMBER( kbreset_w ); 435 436 uint16_t cia_r(offs_t offset, uint16_t mem_mask = ~0); 437 void cia_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); 438 void gayle_cia_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); 439 void cia_0_port_a_write(uint8_t data); 440 DECLARE_WRITE_LINE_MEMBER( cia_0_irq ); 441 uint8_t cia_1_port_a_read(); 442 void cia_1_port_a_write(uint8_t data); 443 DECLARE_WRITE_LINE_MEMBER( cia_1_irq ); 444 445 DECLARE_WRITE_LINE_MEMBER( rs232_rx_w ); 446 DECLARE_WRITE_LINE_MEMBER( rs232_dcd_w ); 447 DECLARE_WRITE_LINE_MEMBER( rs232_dsr_w ); 448 DECLARE_WRITE_LINE_MEMBER( rs232_ri_w ); 449 DECLARE_WRITE_LINE_MEMBER( rs232_cts_w ); 450 451 DECLARE_WRITE_LINE_MEMBER( centronics_ack_w ); 452 DECLARE_WRITE_LINE_MEMBER( centronics_busy_w ); 453 DECLARE_WRITE_LINE_MEMBER( centronics_perror_w ); 454 DECLARE_WRITE_LINE_MEMBER( centronics_select_w ); 455 456 uint16_t custom_chip_r(offs_t offset); 457 void custom_chip_w(offs_t offset, uint16_t data); 458 459 DECLARE_WRITE_LINE_MEMBER( paula_int_w ); 460 461 uint16_t rom_mirror_r(offs_t offset, uint16_t mem_mask = ~0); 462 uint32_t rom_mirror32_r(offs_t offset, uint32_t mem_mask = ~0); 463 464 DECLARE_WRITE_LINE_MEMBER(fdc_dskblk_w); 465 DECLARE_WRITE_LINE_MEMBER(fdc_dsksyn_w); 466 467 // standard clocks 468 static constexpr XTAL CLK_28M_PAL = XTAL(28'375'160); 469 static constexpr XTAL CLK_7M_PAL = CLK_28M_PAL / 4; 470 static constexpr XTAL CLK_C1_PAL = CLK_28M_PAL / 8; 471 static constexpr XTAL CLK_E_PAL = CLK_7M_PAL / 10; 472 473 static constexpr XTAL CLK_28M_NTSC = XTAL(28'636'363); 474 static constexpr XTAL CLK_7M_NTSC = CLK_28M_NTSC / 4; 475 static constexpr XTAL CLK_C1_NTSC = CLK_28M_NTSC / 8; 476 static constexpr XTAL CLK_E_NTSC = CLK_7M_NTSC / 10; 477 478 // screen layout 479 enum 480 { 481 SCREEN_WIDTH = 910, 482 SCREEN_HEIGHT_PAL = 625, 483 SCREEN_HEIGHT_NTSC = 525, 484 VBLANK_PAL = 58, // 52 485 VBLANK_NTSC = 42, 486 HBLANK = 186 487 }; 488 489 emu_timer *m_blitter_timer; 490 491 uint16_t m_agnus_id; 492 uint16_t m_denise_id; 493 494 void blitter_setup(); 495 496 void amiga_base(machine_config &config); 497 void pal_video(machine_config &config); 498 void ntsc_video(machine_config &config); 499 void overlay_1mb_map(address_map &map); 500 void overlay_1mb_map32(address_map &map); 501 void overlay_2mb_map16(address_map &map); 502 void overlay_2mb_map32(address_map &map); 503 void overlay_512kb_map(address_map &map); 504 protected: 505 // A bit of a trick here: some registers are 32-bit. In order to efficiently 506 // read them on both big-endian and little-endian systems, we store the custom 507 // registers in 32-bit natural order. This means we need to XOR the register 508 // address with 1 on little-endian systems. CUSTOM_REG(offs_t x)509 uint16_t &CUSTOM_REG(offs_t x) { return m_custom_regs[BYTE_XOR_BE(x)]; } CUSTOM_REG_SIGNED(offs_t x)510 int16_t &CUSTOM_REG_SIGNED(offs_t x) { return (int16_t &)CUSTOM_REG(x); } CUSTOM_REG_LONG(offs_t x)511 uint32_t &CUSTOM_REG_LONG(offs_t x) { return *(uint32_t *)&m_custom_regs[x]; } 512 513 // agnus/alice chip id 514 enum 515 { 516 AGNUS_PAL = 0x00, 517 AGNUS_NTSC = 0x10, 518 AGNUS_HR_PAL = 0x20, 519 AGNUS_HR_PAL_NEW = 0x21, 520 AGNUS_HR_NTSC = 0x30, 521 AGNUS_HR_NTSC_NEW = 0x31, 522 ALICE_PAL = 0x22, 523 ALICE_PAL_NEW = 0x23, 524 ALICE_NTSC = 0x32, 525 ALICE_NTSC_NEW = 0x33 526 }; 527 528 // denise/lisa chip id 529 enum 530 { 531 DENISE = 0xffff, // actually this register doesn't exist on ocs 532 DENISE_HR = 0x00fc, 533 LISA = 0x00f8 534 }; 535 536 // chipset IS_OCS()537 bool IS_OCS() const { return m_denise_id == 0xff; } IS_ECS()538 bool IS_ECS() const { return m_denise_id == 0xfc; } IS_AGA()539 bool IS_AGA() const { return m_denise_id == 0xf8; } 540 541 // driver_device overrides 542 virtual void machine_start() override; 543 virtual void machine_reset() override; 544 545 // device_t overrides 546 virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; 547 548 void custom_chip_reset(); 549 550 // interrupts 551 void set_interrupt(int interrupt); 552 virtual bool int2_pending(); 553 virtual bool int6_pending(); 554 void update_int2(); 555 void update_int6(); 556 557 virtual void vblank(); 558 potgo_w(uint16_t data)559 virtual void potgo_w(uint16_t data) {}; 560 561 // joystick/mouse 562 virtual uint16_t joy0dat_r(); 563 virtual uint16_t joy1dat_r(); 564 565 // serial 566 virtual void rs232_tx(int state); 567 568 // devices 569 required_device<m68000_base_device> m_maincpu; 570 required_device<mos8520_device> m_cia_0; 571 required_device<mos8520_device> m_cia_1; 572 optional_device<rs232_port_device> m_rs232; 573 optional_device<centronics_device> m_centronics; 574 required_device<paula_8364_device> m_paula; 575 optional_device<amiga_fdc_device> m_fdc; 576 required_device<screen_device> m_screen; 577 optional_device<palette_device> m_palette; 578 required_device<address_map_bank_device> m_overlay; 579 580 581 // i/o ports 582 optional_ioport m_input_device; 583 optional_ioport m_joy0dat_port; 584 optional_ioport m_joy1dat_port; 585 optional_ioport m_potgo_port; 586 optional_ioport m_pot0dat_port; 587 optional_ioport m_pot1dat_port; 588 optional_ioport_array<2> m_joy_ports; 589 optional_ioport m_p1_mouse_x; 590 optional_ioport m_p1_mouse_y; 591 optional_ioport m_p2_mouse_x; 592 optional_ioport m_p2_mouse_y; 593 optional_ioport m_hvpos; 594 595 output_finder<> m_power_led; 596 memory_array m_chip_ram; 597 uint32_t m_chip_ram_mask; 598 599 int m_cia_0_irq; 600 int m_cia_1_irq; 601 602 uint16_t m_custom_regs[256]; 603 static const char *const s_custom_reg_names[0x100]; 604 605 private: 606 // blitter helpers 607 uint32_t blit_ascending(); 608 uint32_t blit_descending(); 609 uint32_t blit_line(); 610 611 // video helpers 612 protected: 613 void set_genlock_color(uint16_t color); 614 private: 615 void copper_setpc(uint32_t pc); 616 int copper_execute_next(int xpos); 617 void sprite_dma_reset(int which); 618 void sprite_enable_comparitor(int which, int enable); 619 void fetch_sprite_data(int scanline, int sprite); 620 void update_sprite_dma(int scanline); 621 uint32_t interleave_sprite_data(uint16_t lobits, uint16_t hibits); 622 int get_sprite_pixel(int x); 623 uint8_t assemble_odd_bitplanes(int planes, int ebitoffs); 624 uint8_t assemble_even_bitplanes(int planes, int ebitoffs); 625 void fetch_bitplane_data(int plane); 626 int update_ham(int newpix); 627 void update_display_window(); 628 void render_scanline(bitmap_rgb32 &bitmap, int scanline); 629 630 // AGA video helpers 631 void aga_palette_write(int color_reg, uint16_t data); 632 void aga_fetch_sprite_data(int scanline, int sprite); 633 void aga_render_scanline(bitmap_rgb32 &bitmap, int scanline); 634 void aga_update_sprite_dma(int scanline); 635 int aga_get_sprite_pixel(int x); 636 uint8_t aga_assemble_odd_bitplanes(int planes, int obitoffs); 637 uint8_t aga_assemble_even_bitplanes(int planes, int ebitoffs); 638 void aga_fetch_bitplane_data(int plane); 639 rgb_t aga_update_ham(int newpix); 640 641 enum 642 { 643 TIMER_SCANLINE, 644 TIMER_AMIGA_IRQ, 645 TIMER_AMIGA_BLITTER, 646 TIMER_SERIAL 647 }; 648 649 enum 650 { 651 VPOSR_LOF = 0x8000 // long frame 652 }; 653 654 enum 655 { 656 ADKCON_UARTBRK = 0x800 // send break 657 }; 658 659 // serial port flags 660 enum 661 { 662 SERDATR_RXD = 0x0800, // serial data 663 SERDATR_TSRE = 0x1000, // transmit ready 664 SERDATR_TBE = 0x2000, // transmit buffer empty 665 SERDATR_RBF = 0x4000, // receive buffer full 666 SERDATR_OVRUN = 0x8000 // receive buffer overrun 667 }; 668 669 enum 670 { 671 SERPER_LONG = 0x8000 // 9-bit mode 672 }; 673 674 static const uint16_t s_expand_byte[256]; 675 676 // pot counters 677 int m_pot0x, m_pot1x, m_pot0y, m_pot1y; 678 679 uint16_t m_pot0dat; 680 uint16_t m_pot1dat; 681 682 int m_centronics_busy; 683 int m_centronics_perror; 684 int m_centronics_select; 685 686 emu_timer *m_irq_timer; 687 emu_timer *m_serial_timer; 688 emu_timer *m_scanline_timer; 689 690 bool m_gayle_reset; 691 692 // display window 693 rectangle m_diw; 694 bool m_diwhigh_valid; 695 696 bool m_previous_lof; 697 bitmap_rgb32 m_flickerfixer; 698 699 uint16_t m_rx_shift; 700 uint16_t m_tx_shift; 701 702 int m_rx_state; 703 int m_tx_state; 704 int m_rx_previous; 705 706 int m_rs232_dcd; 707 int m_rs232_dsr; 708 int m_rs232_ri; 709 int m_rs232_cts; 710 711 void serial_adjust(); 712 void serial_shift(); 713 void rx_write(int level); 714 715 uint32_t amiga_gethvpos(); 716 }; 717 718 #endif // MAME_INCLUDES_AMIGA_H 719