1 // license:BSD-3-Clause 2 // copyright-holders:Wilbert Pol, Robbbert 3 /***************************************************************************** 4 * 5 * includes/gamecom.h 6 * 7 * Tiger Game.com 8 * 9 * Driver by Wilbert Pol 10 * 11 ****************************************************************************/ 12 #ifndef MAME_INCLUDES_GAMECOM_H 13 #define MAME_INCLUDES_GAMECOM_H 14 15 #pragma once 16 17 #include "cpu/sm8500/sm8500.h" 18 #include "sound/dac.h" 19 #include "bus/generic/slot.h" 20 #include "bus/generic/carts.h" 21 #include "machine/nvram.h" 22 #include "emupal.h" 23 24 /* SM8521 register addresses */ 25 enum 26 { 27 SM8521_R0 = 0x00, 28 SM8521_R1 = 0x01, 29 SM8521_R2 = 0x02, 30 SM8521_R3 = 0x03, 31 SM8521_R4 = 0x04, 32 SM8521_R5 = 0x05, 33 SM8521_R6 = 0x06, 34 SM8521_R7 = 0x07, 35 SM8521_R8 = 0x08, 36 SM8521_R9 = 0x09, 37 SM8521_R10 = 0x0A, 38 SM8521_R11 = 0x0B, 39 SM8521_R12 = 0x0C, 40 SM8521_R13 = 0x0D, 41 SM8521_R14 = 0x0E, 42 SM8521_R15 = 0x0F, 43 SM8521_IE0 = 0x10, 44 SM8521_IE1 = 0x11, 45 SM8521_IR0 = 0x12, 46 SM8521_IR1 = 0x13, 47 SM8521_P0 = 0x14, 48 SM8521_P1 = 0x15, 49 SM8521_P2 = 0x16, 50 SM8521_P3 = 0x17, 51 SM8521_18 = 0x18, /* reserved */ 52 SM8521_SYS = 0x19, 53 SM8521_CKC = 0x1A, 54 SM8521_1B = 0x1B, /* reserved */ 55 SM8521_SPH = 0x1C, 56 SM8521_SPL = 0x1D, 57 SM8521_PS0 = 0x1E, 58 SM8521_PS1 = 0x1F, 59 SM8521_P0C = 0x20, 60 SM8521_P1C = 0x21, 61 SM8521_P2C = 0x22, 62 SM8521_P3C = 0x23, 63 SM8521_MMU0 = 0x24, 64 SM8521_MMU1 = 0x25, 65 SM8521_MMU2 = 0x26, 66 SM8521_MMU3 = 0x27, 67 SM8521_MMU4 = 0x28, 68 SM8521_29 = 0x29, /* reserved */ 69 SM8521_2A = 0x2A, /* reserved */ 70 SM8521_URTT = 0x2B, 71 SM8521_URTR = 0x2C, 72 SM8521_URTS = 0x2D, 73 SM8521_URTC = 0x2E, 74 SM8521_2F = 0x2F, /* reserved */ 75 SM8521_LCDC = 0x30, 76 SM8521_LCH = 0x31, 77 SM8521_LCV = 0x32, 78 SM8521_33 = 0x33, /* reserved */ 79 SM8521_DMC = 0x34, 80 SM8521_DMX1 = 0x35, 81 SM8521_DMY1 = 0x36, 82 SM8521_DMDX = 0x37, 83 SM8521_DMDY = 0x38, 84 SM8521_DMX2 = 0x39, 85 SM8521_DMY2 = 0x3A, 86 SM8521_DMPL = 0x3B, 87 SM8521_DMBR = 0x3C, 88 SM8521_DMVP = 0x3D, 89 SM8521_3E = 0x3E, /* reserved */ 90 SM8521_3F = 0x3F, /* reserved */ 91 SM8521_SGC = 0x40, 92 SM8521_41 = 0x41, /* reserved */ 93 SM8521_SG0L = 0x42, 94 SM8521_43 = 0x43, /* reserved */ 95 SM8521_SG1L = 0x44, 96 SM8521_45 = 0x45, /* reserved */ 97 SM8521_SG0TH = 0x46, 98 SM8521_SG0TL = 0x47, 99 SM8521_SG1TH = 0x48, 100 SM8521_SG1TL = 0x49, 101 SM8521_SG2L = 0x4A, 102 SM8521_4B = 0x4B, /* reserved */ 103 SM8521_SG2TH = 0x4C, 104 SM8521_SG2TL = 0x4D, 105 SM8521_SGDA = 0x4E, 106 SM8521_4F = 0x4F, /* reserved */ 107 SM8521_TM0C = 0x50, 108 SM8521_TM0D = 0x51, 109 SM8521_TM1C = 0x52, 110 SM8521_TM1D = 0x53, 111 SM8521_CLKT = 0x54, 112 SM8521_55 = 0x55, /* reserved */ 113 SM8521_56 = 0x56, /* reserved */ 114 SM8521_57 = 0x57, /* reserved */ 115 SM8521_58 = 0x58, /* reserved */ 116 SM8521_59 = 0x59, /* reserved */ 117 SM8521_5A = 0x5A, /* reserved */ 118 SM8521_5B = 0x5B, /* reserved */ 119 SM8521_5C = 0x5C, /* reserved */ 120 SM8521_5D = 0x5D, /* reserved */ 121 SM8521_WDT = 0x5E, 122 SM8521_WDTC = 0x5F, 123 SM8521_SG0W0 = 0x60, 124 SM8521_SG0W1 = 0x61, 125 SM8521_SG0W2 = 0x62, 126 SM8521_SG0W3 = 0x63, 127 SM8521_SG0W4 = 0x64, 128 SM8521_SG0W5 = 0x65, 129 SM8521_SG0W6 = 0x66, 130 SM8521_SG0W7 = 0x67, 131 SM8521_SG0W8 = 0x68, 132 SM8521_SG0W9 = 0x69, 133 SM8521_SG0W10 = 0x6A, 134 SM8521_SG0W11 = 0x6B, 135 SM8521_SG0W12 = 0x6C, 136 SM8521_SG0W13 = 0x6D, 137 SM8521_SG0W14 = 0x6E, 138 SM8521_SG0W15 = 0x6F, 139 SM8521_SG1W0 = 0x70, 140 SM8521_SG1W1 = 0x71, 141 SM8521_SG1W2 = 0x72, 142 SM8521_SG1W3 = 0x73, 143 SM8521_SG1W4 = 0x74, 144 SM8521_SG1W5 = 0x75, 145 SM8521_SG1W6 = 0x76, 146 SM8521_SG1W7 = 0x77, 147 SM8521_SG1W8 = 0x78, 148 SM8521_SG1W9 = 0x79, 149 SM8521_SG1W10 = 0x7A, 150 SM8521_SG1W11 = 0x7B, 151 SM8521_SG1W12 = 0x7C, 152 SM8521_SG1W13 = 0x7D, 153 SM8521_SG1W14 = 0x7E, 154 SM8521_SG1W15 = 0x7F 155 }; 156 157 struct GAMECOM_DMA 158 { 159 u8 width_x; 160 u8 width_y; 161 u8 source_x; 162 u8 source_x_current; 163 u8 source_y; 164 u8 source_width; 165 u8 dest_x; 166 u8 dest_x_current; 167 u8 dest_y; 168 u8 dest_width; 169 u8 palette; 170 u8 block_width; 171 u8 block_height; 172 u8 *source_bank; 173 u16 source_current; 174 u16 source_line; 175 u16 source_mask; 176 u8 *dest_bank; 177 u16 dest_current; 178 u16 dest_line; 179 u16 dest_mask; 180 u8 transfer_mode; 181 s16 adjust_x; 182 bool decrement_y; 183 bool overwrite_mode; 184 }; 185 186 struct GAMECOM_TIMER 187 { 188 bool enabled; 189 u32 prescale_count; 190 u32 prescale_max; 191 u8 upcounter_max; 192 }; 193 194 struct gamecom_sound_t 195 { 196 uint8_t sgc; 197 uint8_t sg0l; 198 uint8_t sg1l; 199 uint8_t sg2l; 200 uint16_t sg0t; 201 uint16_t sg1t; 202 uint16_t sg2t; 203 uint8_t sgda; 204 uint8_t sg0w[16]; 205 uint8_t sg1w[16]; 206 }; 207 208 209 class gamecom_state : public driver_device 210 { 211 public: gamecom_state(const machine_config & mconfig,device_type type,const char * tag)212 gamecom_state(const machine_config &mconfig, device_type type, const char *tag) 213 : driver_device(mconfig, type, tag) 214 , m_p_videoram(*this,"videoram") 215 , m_p_nvram(*this,"nvram") 216 , m_maincpu(*this, "maincpu") 217 , m_screen(*this, "screen") 218 , m_dac(*this, "dac") 219 , m_dac0(*this, "dac0") 220 , m_dac1(*this, "dac1") 221 , m_cart1(*this, "cartslot1") 222 , m_cart2(*this, "cartslot2") 223 , m_bank1(*this, "bank1") 224 , m_bank2(*this, "bank2") 225 , m_bank3(*this, "bank3") 226 , m_bank4(*this, "bank4") 227 , m_region_maincpu(*this, "maincpu") 228 , m_region_kernel(*this, "kernel") 229 , m_io_in0(*this, "IN0") 230 , m_io_in1(*this, "IN1") 231 , m_io_in2(*this, "IN2") 232 , m_io_grid(*this, "GRID.%u", 0) 233 { 234 } 235 236 void gamecom(machine_config &config); 237 238 void init_gamecom(); 239 240 private: 241 242 uint8_t gamecom_internal_r(offs_t offset); 243 uint8_t gamecom_pio_r(offs_t offset); 244 void gamecom_internal_w(offs_t offset, uint8_t data); 245 void gamecom_pio_w(offs_t offset, uint8_t data); 246 void gamecom_palette(palette_device &palette) const; 247 INTERRUPT_GEN_MEMBER(gamecom_interrupt); 248 TIMER_CALLBACK_MEMBER(gamecom_clock_timer_callback); 249 TIMER_CALLBACK_MEMBER(gamecom_sound0_timer_callback); 250 TIMER_CALLBACK_MEMBER(gamecom_sound1_timer_callback); 251 TIMER_CALLBACK_MEMBER(gamecom_scanline); 252 void gamecom_handle_dma(uint8_t data); 253 void gamecom_update_timers(uint8_t data); 254 DECLARE_DEVICE_IMAGE_LOAD_MEMBER( cart1_load ); 255 DECLARE_DEVICE_IMAGE_LOAD_MEMBER( cart2_load ); 256 uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); 257 void gamecom_mem_map(address_map &map); 258 259 uint8_t *m_p_ram; 260 uint8_t *m_cart_ptr; 261 uint8_t m_lcdc_reg; 262 uint8_t m_lch_reg; 263 uint8_t m_lcv_reg; 264 uint8_t m_sound0_cnt; 265 uint8_t m_sound1_cnt; 266 uint16_t m_scanline; 267 uint16_t m_base_address; 268 memory_region *m_cart1_rom; 269 memory_region *m_cart2_rom; 270 emu_timer *m_clock_timer; 271 emu_timer *m_sound0_timer; 272 emu_timer *m_sound1_timer; 273 emu_timer *m_scanline_timer; 274 GAMECOM_DMA m_dma; 275 GAMECOM_TIMER m_timer[2]; 276 gamecom_sound_t m_sound; 277 bitmap_ind16 m_bitmap; 278 void gamecom_set_mmu(uint8_t mmu, uint8_t data); 279 void handle_stylus_press(int column); 280 void recompute_lcd_params(); 281 void handle_input_press(uint16_t mux_data); 282 image_init_result common_load(device_image_interface &image, generic_slot_device *slot); 283 virtual void machine_reset() override; 284 virtual void video_start() override; 285 required_shared_ptr<uint8_t> m_p_videoram; 286 required_shared_ptr<uint8_t> m_p_nvram; 287 required_device<sm8500_cpu_device> m_maincpu; 288 required_device<screen_device> m_screen; 289 required_device<dac_byte_interface> m_dac; 290 required_device<dac_byte_interface> m_dac0; 291 required_device<dac_byte_interface> m_dac1; 292 required_device<generic_slot_device> m_cart1; 293 required_device<generic_slot_device> m_cart2; 294 required_memory_bank m_bank1; 295 required_memory_bank m_bank2; 296 required_memory_bank m_bank3; 297 required_memory_bank m_bank4; 298 required_memory_region m_region_maincpu; 299 required_memory_region m_region_kernel; 300 required_ioport m_io_in0; 301 required_ioport m_io_in1; 302 required_ioport m_io_in2; 303 required_ioport_array<13> m_io_grid; 304 }; 305 306 #endif // MAME_INCLUDES_GAMECOM_H 307