1 // license:BSD-3-Clause 2 // copyright-holders:Ryan Holtz 3 /*************************************************************************** 4 5 Skeleton driver for Philips VP415 LV ROM Player 6 7 List of Modules: 8 A - Audio Processor 9 B - RGB 10 C - Video Processor 11 D - Ref Source 12 E - Slide Drive 13 F - Motor+Sequence 14 G - Gen Lock 15 H - ETBC B 16 I - ETBC C 17 J - Focus 18 K - HF Processor 19 L - Video Dropout Correction 20 M - Radial 21 N - Display Keyboard 22 P - Front Loader 23 Q - RC5 Mirror 24 R - Drive Processor 25 S - Control 26 T - Supply 27 U - Analog I/O 28 V - Module Carrier 29 W - CPU Datagrabber 30 X - LV ROM 31 Y - Vid Mix 32 Z - Deck Electronics 33 34 TODO: 35 - Driver currently fails the initial self-test with code 073. Per 36 the service manual, code 73 means "a/d converted mirror pos. min. 37 (out of field of view)". 38 39 ***************************************************************************/ 40 41 #ifndef MAME_INCLUDES_VP415_H 42 #define MAME_INCLUDES_VP415_H 43 44 #pragma once 45 46 #include "cpu/mcs51/mcs51.h" 47 #include "cpu/mcs48/mcs48.h" 48 #include "cpu/z80/z80.h" 49 50 #include "machine/i8155.h" 51 #include "machine/i8255.h" 52 #include "machine/ncr5385.h" 53 #include "machine/saa1043.h" 54 55 #include "video/mb88303.h" 56 57 #include "screen.h" 58 59 60 class vp415_state : public driver_device 61 { 62 public: 63 vp415_state(const machine_config &mconfig, device_type type, const char *tag); 64 65 void vp415(machine_config &config); 66 67 static const char *const DATACPU_TAG; 68 static const char *const DATAMCU_TAG; 69 70 static const char *const DESCRAMBLE_ROM_TAG; 71 static const char *const SYNC_ROM_TAG; 72 static const char *const DRIVE_ROM_TAG; 73 74 static const char *const CTRLMCU_TAG; 75 static const char *const CONTROL_ROM_TAG; 76 77 static const char *const SWITCHES_TAG; 78 79 private: 80 void machine_reset() override; 81 void machine_start() override; 82 void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; 83 84 uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); 85 86 void sel34_w(uint8_t data); 87 uint8_t sel37_r(); 88 89 DECLARE_WRITE_LINE_MEMBER(cpu_int1_w); 90 91 void data_mcu_port1_w(uint8_t data); 92 uint8_t data_mcu_port1_r(); 93 void data_mcu_port2_w(uint8_t data); 94 uint8_t data_mcu_port2_r(); 95 96 void ctrl_regs_w(offs_t offset, uint8_t data); 97 uint8_t ctrl_regs_r(offs_t offset); 98 void ctrl_cpu_port1_w(uint8_t data); 99 uint8_t ctrl_cpu_port1_r(); 100 void ctrl_cpu_port3_w(uint8_t data); 101 uint8_t ctrl_cpu_port3_r(); 102 103 void ctrl_mcu_port1_w(uint8_t data); 104 uint8_t ctrl_mcu_port1_r(); 105 void ctrl_mcu_port2_w(uint8_t data); 106 uint8_t ctrl_mcu_port2_r(); 107 108 uint8_t drive_i8155_pb_r(); 109 uint8_t drive_i8155_pc_r(); 110 111 void drive_i8255_pa_w(uint8_t data); 112 void drive_i8255_pb_w(uint8_t data); 113 uint8_t drive_i8255_pc_r(); 114 void drive_cpu_port1_w(uint8_t data); 115 void drive_cpu_port3_w(uint8_t data); 116 117 DECLARE_WRITE_LINE_MEMBER(refv_w); 118 119 // CPU Board enums 120 enum 121 { 122 SEL34_INTR_N = 0x01, 123 SEL34_RES = 0x20, 124 SEL34_ERD = 0x40, 125 SEL34_ENW = 0x80, 126 SEL34_INTR_N_BIT = 0, 127 SEL34_RES_BIT = 5, 128 SEL34_ERD_BIT = 6, 129 SEL34_ENW_BIT = 7, 130 }; 131 132 enum 133 { 134 SEL37_ID0 = 0x01, 135 SEL37_ID1 = 0x02, 136 SEL37_BRD = 0x10, 137 SEL37_MON_N = 0x20, 138 SEL37_SK1c = 0x40, 139 SEL37_SK1d = 0x40, 140 141 SEL37_ID0_BIT = 0, 142 SEL37_ID1_BIT = 1, 143 SEL37_BRD_BIT = 4, 144 SEL37_MON_N_BIT = 5, 145 SEL37_SK1c_BIT = 6, 146 SEL37_SK1d_BIT = 7, 147 }; 148 149 // Control Board enums 150 enum 151 { 152 CTRL_P3_INT1 = 0x08, 153 154 CTRL_P3_INT1_BIT = 3 155 }; 156 157 // Drive Board enums 158 enum 159 { 160 I8255PC_NOT_FOCUSED = 0x02, 161 I8255PC_0RPM_N = 0x08, 162 I8255PC_DISC_REFLECTION = 0x10, 163 }; 164 165 enum 166 { 167 I8255PB_COMM1 = 0x01, 168 I8255PB_COMM2 = 0x02, 169 I8255PB_COMM3 = 0x04, 170 I8255PB_COMM4 = 0x08, 171 I8255PB_RLS_N = 0x10, 172 I8255PB_SL_PWR = 0x20, 173 I8255PB_RAD_FS_N = 0x40, 174 I8255PB_STR1 = 0x80, 175 176 I8255PB_COMM1_BIT = 0, 177 I8255PB_COMM2_BIT = 1, 178 I8255PB_COMM3_BIT = 2, 179 I8255PB_COMM4_BIT = 3, 180 I8255PB_RLS_N_BIT = 4, 181 I8255PB_SL_PWR_BIT = 5, 182 I8255PB_RAD_FS_N_BIT = 6, 183 I8255PB_STR1_BIT = 7, 184 }; 185 186 enum 187 { 188 I8155PB_2PPR = 0x01, 189 I8155PB_RAD_MIR = 0x04, 190 I8155PB_FRLOCK = 0x08, 191 192 I8155PB_2PPR_BIT = 0, 193 I8155PB_RAD_MIR_BIT = 2, 194 I8155PB_FRLOCK_BIT = 3, 195 }; 196 197 enum 198 { 199 DRIVE_P1_CP1 = 0x01, 200 DRIVE_P1_CP2 = 0x02, 201 DRIVE_P1_LDI = 0x04, 202 DRIVE_P1_ATN_N = 0x08, 203 DRIVE_P1_TX = 0x10, 204 DRIVE_P1_STB_N = 0x20, 205 DRIVE_P1_STR0_N = 0x40, 206 DRIVE_P1_TP2 = 0x80, 207 208 DRIVE_P1_CP1_BIT = 0, 209 DRIVE_P1_CP2_BIT = 1, 210 DRIVE_P1_LDI_BIT = 2, 211 DRIVE_P1_ATN_N_BIT = 3, 212 DRIVE_P1_TX_BIT = 4, 213 DRIVE_P1_STB_N_BIT = 5, 214 DRIVE_P1_STR0_N_BIT = 6, 215 DRIVE_P1_TP2_BIT = 7 216 }; 217 218 virtual void video_start() override; 219 220 void z80_program_map(address_map &map); 221 void z80_io_map(address_map &map); 222 void datamcu_program_map(address_map &map); 223 void set_int_line(uint8_t line, uint8_t value); 224 void update_cpu_int(); 225 226 void ctrl_program_map(address_map &map); 227 void ctrl_io_map(address_map &map); 228 void ctrlmcu_program_map(address_map &map); 229 void sd_w(uint8_t data); 230 uint8_t sd_r(); 231 232 void drive_program_map(address_map &map); 233 void drive_io_map(address_map &map); 234 235 required_device<z80_device> m_datacpu; 236 required_device<i8041a_device> m_datamcu; 237 required_device<ncr5385_device> m_scsi; 238 required_device<i8031_device> m_drivecpu; 239 required_device<i8031_device> m_ctrlcpu; 240 required_device<i8041a_device> m_ctrlmcu; 241 required_device<mb88303_device> m_chargen; 242 required_shared_ptr<uint8_t> m_mainram; 243 required_shared_ptr<uint8_t> m_ctrlram; 244 required_ioport m_switches; 245 246 uint8_t m_sel34; 247 uint8_t m_sel37; 248 249 uint8_t m_int_lines[2]; 250 251 uint8_t m_refv; 252 253 uint8_t m_ctrl_cpu_p1; 254 uint8_t m_ctrl_cpu_p3; 255 uint8_t m_ctrl_mcu_p1; 256 uint8_t m_ctrl_mcu_p2; 257 258 uint8_t m_drive_p1; 259 uint8_t m_drive_pc_bits; 260 261 uint8_t m_drive_rad_mir_dac; 262 uint8_t m_drive_i8255_pb; 263 emu_timer *m_drive_2ppr_timer; 264 uint8_t m_drive_2ppr; 265 266 static const char *const DATARAM_TAG; 267 static const char *const SCSI_TAG; 268 269 static const char *const CTRLCPU_TAG; 270 static const char *const CTRLRAM_TAG; 271 272 static const char *const DRIVECPU_TAG; 273 static const char *const I8155_TAG; 274 static const char *const I8255_TAG; 275 static const char *const CHARGEN_TAG; 276 static const char *const SYNCGEN_TAG; 277 278 static const device_timer_id DRIVE_2PPR_ID; 279 }; 280 281 #endif // MAME_INCLUDES_VP415_H 282