1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* 26 * DEF(name, oargs, iargs, cargs, flags) 27 */ 28 29 /* predefined ops */ 30 DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */ 31 DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT) 32 DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT) 33 DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT) 34 DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT) 35 36 /* variable number of parameters */ 37 DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT) 38 39 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) 40 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) 41 42 /* variable number of parameters */ 43 DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) 44 45 DEF(br, 0, 0, 1, TCG_OPF_BB_END) 46 47 #ifdef _MSC_VER 48 #define IMPL(X) ((0 && !(X)) ? TCG_OPF_NOT_PRESENT : 0) 49 #else 50 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0) 51 #endif 52 53 #if TCG_TARGET_REG_BITS == 32 54 # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT 55 #else 56 # define IMPL64 TCG_OPF_64BIT 57 #endif 58 59 DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) 60 DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT) 61 DEF(setcond_i32, 1, 2, 1, 0) 62 DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) 63 /* load/store */ 64 DEF(ld8u_i32, 1, 1, 1, 0) 65 DEF(ld8s_i32, 1, 1, 1, 0) 66 DEF(ld16u_i32, 1, 1, 1, 0) 67 DEF(ld16s_i32, 1, 1, 1, 0) 68 DEF(ld_i32, 1, 1, 1, 0) 69 DEF(st8_i32, 0, 2, 1, 0) 70 DEF(st16_i32, 0, 2, 1, 0) 71 DEF(st_i32, 0, 2, 1, 0) 72 /* arith */ 73 DEF(add_i32, 1, 2, 0, 0) 74 DEF(sub_i32, 1, 2, 0, 0) 75 DEF(mul_i32, 1, 2, 0, 0) 76 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 77 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) 78 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 79 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) 80 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) 81 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) 82 DEF(and_i32, 1, 2, 0, 0) 83 DEF(or_i32, 1, 2, 0, 0) 84 DEF(xor_i32, 1, 2, 0, 0) 85 /* shifts/rotates */ 86 DEF(shl_i32, 1, 2, 0, 0) 87 DEF(shr_i32, 1, 2, 0, 0) 88 DEF(sar_i32, 1, 2, 0, 0) 89 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 90 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) 91 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) 92 93 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END) 94 95 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32)) 96 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32)) 97 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32)) 98 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32)) 99 DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32)) 100 DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32)) 101 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32)) 102 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) 103 104 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32)) 105 DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32)) 106 DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32)) 107 DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32)) 108 DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32)) 109 DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32)) 110 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) 111 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) 112 DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32)) 113 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) 114 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) 115 DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32)) 116 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) 117 118 DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) 119 DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) 120 DEF(setcond_i64, 1, 2, 1, IMPL64) 121 DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) 122 /* load/store */ 123 DEF(ld8u_i64, 1, 1, 1, IMPL64) 124 DEF(ld8s_i64, 1, 1, 1, IMPL64) 125 DEF(ld16u_i64, 1, 1, 1, IMPL64) 126 DEF(ld16s_i64, 1, 1, 1, IMPL64) 127 DEF(ld32u_i64, 1, 1, 1, IMPL64) 128 DEF(ld32s_i64, 1, 1, 1, IMPL64) 129 DEF(ld_i64, 1, 1, 1, IMPL64) 130 DEF(st8_i64, 0, 2, 1, IMPL64) 131 DEF(st16_i64, 0, 2, 1, IMPL64) 132 DEF(st32_i64, 0, 2, 1, IMPL64) 133 DEF(st_i64, 0, 2, 1, IMPL64) 134 /* arith */ 135 DEF(add_i64, 1, 2, 0, IMPL64) 136 DEF(sub_i64, 1, 2, 0, IMPL64) 137 DEF(mul_i64, 1, 2, 0, IMPL64) 138 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) 139 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) 140 DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) 141 DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) 142 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) 143 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) 144 DEF(and_i64, 1, 2, 0, IMPL64) 145 DEF(or_i64, 1, 2, 0, IMPL64) 146 DEF(xor_i64, 1, 2, 0, IMPL64) 147 /* shifts/rotates */ 148 DEF(shl_i64, 1, 2, 0, IMPL64) 149 DEF(shr_i64, 1, 2, 0, IMPL64) 150 DEF(sar_i64, 1, 2, 0, IMPL64) 151 DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) 152 DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) 153 DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) 154 155 DEF(trunc_shr_i32, 1, 1, 1, 156 IMPL(TCG_TARGET_HAS_trunc_shr_i32) 157 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) 158 159 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64) 160 DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) 161 DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) 162 DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64)) 163 DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64)) 164 DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64)) 165 DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64)) 166 DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64)) 167 DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64)) 168 DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64)) 169 DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64)) 170 DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64)) 171 DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64)) 172 DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) 173 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) 174 DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64)) 175 DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64)) 176 177 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) 178 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) 179 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64)) 180 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64)) 181 DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64)) 182 DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64)) 183 184 /* QEMU specific */ 185 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 186 DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT) 187 #else 188 DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT) 189 #endif 190 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END) 191 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END) 192 193 #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) 194 #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) 195 196 DEF(qemu_ld_i32, 1, TLADDR_ARGS, 2, 197 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 198 DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 2, 199 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) 200 DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 2, 201 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) 202 DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 2, 203 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) 204 205 #undef TLADDR_ARGS 206 #undef DATA64_ARGS 207 #undef IMPL 208 #undef IMPL64 209 #undef DEF 210