1 /*
2  * GUSEMU32 - bus interface part
3  *
4  * Copyright (C) 2000-2007 Tibor "TS" Schütz
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 /*
26  * TODO: check mixer: see 7.20 of sdk for panning pos (applies to all gus models?)?
27  */
28 
29 #include "qemu/osdep.h"
30 #include "gustate.h"
31 #include "gusemu.h"
32 
33 #define GUSregb(position) (*            (gusptr+(position)))
34 #define GUSregw(position) (*(uint16_t *) (gusptr+(position)))
35 #define GUSregd(position) (*(uint32_t *)(gusptr + (position)))
36 
37 /* size given in bytes */
gus_read(GUSEmuState * state,int port,int size)38 unsigned int gus_read(GUSEmuState * state, int port, int size)
39 {
40     int             value_read = 0;
41 
42     uint8_t        *gusptr;
43     gusptr = state->gusdatapos;
44     GUSregd(portaccesses)++;
45 
46     switch (port & 0xff0f)
47     {
48         /* MixerCtrlReg (read not supported on GUS classic) */
49         /* case 0x200: return GUSregb(MixerCtrlReg2x0); */
50     case 0x206:                          /* IRQstatReg / SB2x6IRQ */
51         /* adlib/sb bits set in port handlers */
52         /* timer/voice bits set in gus_irqgen() */
53         /* dma bit set in gus_dma_transferdata */
54         /* midi not implemented yet */
55         return GUSregb(IRQStatReg2x6);
56     /* case 0x308:                       */ /* AdLib388 */
57     case 0x208:
58         if (GUSregb(GUS45TimerCtrl) & 1)
59             return GUSregb(TimerStatus2x8);
60         return GUSregb(AdLibStatus2x8);  /* AdLibStatus */
61     case 0x309:                          /* AdLib389 */
62     case 0x209:
63         return GUSregb(AdLibData2x9);    /* AdLibData */
64     case 0x20A:
65         return GUSregb(AdLibCommand2xA); /* AdLib2x8_2xA */
66 
67 #if 0
68     case 0x20B:                          /* GUS hidden registers (read not supported on GUS classic) */
69         switch (GUSregb(RegCtrl_2xF) & 0x07)
70         {
71         case 0:                                 /* IRQ/DMA select */
72             if (GUSregb(MixerCtrlReg2x0) & 0x40)
73                 return GUSregb(IRQ_2xB);        /* control register select bit */
74             else
75                 return GUSregb(DMA_2xB);
76             /* case 1-5:                        */ /* general purpose emulation regs  */
77             /*  return ...                      */ /* + status reset reg (write only) */
78         case 6:
79             return GUSregb(Jumper_2xB);         /* Joystick/MIDI enable (JumperReg) */
80         default:;
81         }
82         break;
83 #endif
84 
85     case 0x20C:                          /* SB2xCd */
86         value_read = GUSregb(SB2xCd);
87         if (GUSregb(StatRead_2xF) & 0x20)
88             GUSregb(SB2xCd) ^= 0x80; /* toggle MSB on read */
89         return value_read;
90         /* case 0x20D:                   */ /* SB2xD is write only -> 2xE writes to it*/
91     case 0x20E:
92         if (GUSregb(RegCtrl_2xF) & 0x80) /* 2xE read IRQ enabled? */
93         {
94             GUSregb(StatRead_2xF) |= 0x80;
95             GUS_irqrequest(state, state->gusirq, 1);
96         }
97         return GUSregb(SB2xE);           /* SB2xE */
98     case 0x20F:                          /* StatRead_2xF */
99         /*set/clear fixed bits */
100         /*value_read = (GUSregb(StatRead_2xF) & 0xf9)|1; */ /*(LSB not set on GUS classic!)*/
101         value_read = (GUSregb(StatRead_2xF) & 0xf9);
102         if (GUSregb(MixerCtrlReg2x0) & 0x08)
103             value_read |= 2;    /* DMA/IRQ enabled flag */
104         return value_read;
105     /* case 0x300:                      */ /* MIDI (not implemented) */
106     /* case 0x301:                      */ /* MIDI (not implemented) */
107     case 0x302:
108         return GUSregb(VoiceSelReg3x2); /* VoiceSelReg */
109     case 0x303:
110         return GUSregb(FunkSelReg3x3);  /* FunkSelReg */
111     case 0x304:                         /* DataRegLoByte3x4 + DataRegWord3x4 */
112     case 0x305:                         /* DataRegHiByte3x5 */
113         switch (GUSregb(FunkSelReg3x3))
114         {
115     /* common functions */
116         case 0x41:                      /* DramDMAContrReg */
117             value_read = GUSregb(GUS41DMACtrl); /* &0xfb */
118             GUSregb(GUS41DMACtrl) &= 0xbb;
119             if (state->gusdma >= 4)
120                 value_read |= 0x04;
121             if (GUSregb(IRQStatReg2x6) & 0x80)
122             {
123                 value_read |= 0x40;
124                 GUSregb(IRQStatReg2x6) &= 0x7f;
125                 if (!GUSregb(IRQStatReg2x6))
126                     GUS_irqclear(state, state->gusirq);
127             }
128             return (uint8_t) value_read;
129             /* DramDMAmemPosReg */
130             /* case 0x42: value_read=GUSregw(GUS42DMAStart); break;*/
131             /* 43h+44h write only */
132         case 0x45:
133             return GUSregb(GUS45TimerCtrl);         /* TimerCtrlReg */
134             /* 46h+47h write only */
135             /* 48h: samp freq - write only */
136         case 0x49:
137             return GUSregb(GUS49SampCtrl) & 0xbf;   /* SampCtrlReg */
138         /* case 4bh:                                */ /* joystick trim not supported */
139         /* case 0x4c: return GUSregb(GUS4cReset);   */ /* GUSreset: write only*/
140     /* voice specific functions */
141         case 0x80:
142         case 0x81:
143         case 0x82:
144         case 0x83:
145         case 0x84:
146         case 0x85:
147         case 0x86:
148         case 0x87:
149         case 0x88:
150         case 0x89:
151         case 0x8a:
152         case 0x8b:
153         case 0x8c:
154         case 0x8d:
155             {
156                 int             offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
157                 offset += ((int) GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /* = Voice*32 + Funktion*2 */
158                 value_read = GUSregw(offset);
159             }
160             break;
161     /* voice unspecific functions */
162         case 0x8e:                                  /* NumVoice */
163             return GUSregb(NumVoices);
164         case 0x8f:                                  /* irqstatreg */
165             /* (pseudo IRQ-FIFO is processed during a gus_write(0x3X3,0x8f)) */
166             return GUSregb(SynVoiceIRQ8f);
167         default:
168             return 0xffff;
169         }
170         if (size == 1)
171         {
172             if ((port & 0xff0f) == 0x305)
173                 value_read = value_read >> 8;
174             value_read &= 0xff;
175         }
176         return (uint16_t) value_read;
177     /* case 0x306:                                  */ /* Mixer/Version info */
178         /*  return 0xff; */ /* Pre 3.6 boards, ICS mixer NOT present */
179     case 0x307:                                     /* DRAMaccess */
180         {
181             uint8_t        *adr;
182             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
183             return *adr;
184         }
185     default:;
186     }
187     return 0xffff;
188 }
189 
gus_write(GUSEmuState * state,int port,int size,unsigned int data)190 void gus_write(GUSEmuState * state, int port, int size, unsigned int data)
191 {
192     uint8_t        *gusptr;
193     gusptr = state->gusdatapos;
194     GUSregd(portaccesses)++;
195 
196     switch (port & 0xff0f)
197     {
198     case 0x200:                 /* MixerCtrlReg */
199         GUSregb(MixerCtrlReg2x0) = (uint8_t) data;
200         break;
201     case 0x206:                 /* IRQstatReg / SB2x6IRQ */
202         if (GUSregb(GUS45TimerCtrl) & 0x20) /* SB IRQ enabled? -> set 2x6IRQ bit */
203         {
204             GUSregb(TimerStatus2x8) |= 0x08;
205             GUSregb(IRQStatReg2x6) = 0x10;
206             GUS_irqrequest(state, state->gusirq, 1);
207         }
208         break;
209     case 0x308:                /* AdLib 388h */
210     case 0x208:                /* AdLibCommandReg */
211         GUSregb(AdLibCommand2xA) = (uint8_t) data;
212         break;
213     case 0x309:                /* AdLib 389h */
214     case 0x209:                /* AdLibDataReg */
215         if ((GUSregb(AdLibCommand2xA) == 0x04) && (!(GUSregb(GUS45TimerCtrl) & 1))) /* GUS auto timer mode enabled? */
216         {
217             if (data & 0x80)
218                 GUSregb(TimerStatus2x8) &= 0x1f; /* AdLib IRQ reset? -> clear maskable adl. timer int regs */
219             else
220                 GUSregb(TimerDataReg2x9) = (uint8_t) data;
221         }
222         else
223         {
224             GUSregb(AdLibData2x9) = (uint8_t) data;
225             if (GUSregb(GUS45TimerCtrl) & 0x02)
226             {
227                 GUSregb(TimerStatus2x8) |= 0x01;
228                 GUSregb(IRQStatReg2x6) = 0x10;
229                 GUS_irqrequest(state, state->gusirq, 1);
230             }
231         }
232         break;
233     case 0x20A:
234         GUSregb(AdLibStatus2x8) = (uint8_t) data;
235         break;                 /* AdLibStatus2x8 */
236     case 0x20B:                /* GUS hidden registers */
237         switch (GUSregb(RegCtrl_2xF) & 0x7)
238         {
239         case 0:
240             if (GUSregb(MixerCtrlReg2x0) & 0x40)
241                 GUSregb(IRQ_2xB) = (uint8_t) data; /* control register select bit */
242             else
243                 GUSregb(DMA_2xB) = (uint8_t) data;
244             break;
245             /* case 1-4: general purpose emulation regs */
246         case 5:                                    /* clear stat reg 2xF */
247             GUSregb(StatRead_2xF) = 0; /* ToDo: is this identical with GUS classic? */
248             if (!GUSregb(IRQStatReg2x6))
249                 GUS_irqclear(state, state->gusirq);
250             break;
251         case 6:                                    /* Jumper reg (Joystick/MIDI enable) */
252             GUSregb(Jumper_2xB) = (uint8_t) data;
253             break;
254         default:;
255         }
256         break;
257     case 0x20C:                /* SB2xCd */
258         if (GUSregb(GUS45TimerCtrl) & 0x20)
259         {
260             GUSregb(TimerStatus2x8) |= 0x10; /* SB IRQ enabled? -> set 2xCIRQ bit */
261             GUSregb(IRQStatReg2x6) = 0x10;
262             GUS_irqrequest(state, state->gusirq, 1);
263         }
264         /* fall through */
265     case 0x20D:                /* SB2xCd no IRQ */
266         GUSregb(SB2xCd) = (uint8_t) data;
267         break;
268     case 0x20E:                /* SB2xE */
269         GUSregb(SB2xE) = (uint8_t) data;
270         break;
271     case 0x20F:
272         GUSregb(RegCtrl_2xF) = (uint8_t) data;
273         break;                 /* CtrlReg2xF */
274     case 0x302:                /* VoiceSelReg */
275         GUSregb(VoiceSelReg3x2) = (uint8_t) data;
276         break;
277     case 0x303:                /* FunkSelReg */
278         GUSregb(FunkSelReg3x3) = (uint8_t) data;
279         if ((uint8_t) data == 0x8f) /* set irqstatreg, get voicereg and clear IRQ */
280         {
281             int             voice;
282             if (GUSregd(voicewavetableirq)) /* WavetableIRQ */
283             {
284                 for (voice = 0; voice < 31; voice++)
285                 {
286                     if (GUSregd(voicewavetableirq) & (1 << voice))
287                     {
288                         GUSregd(voicewavetableirq) ^= (1 << voice); /* clear IRQ bit */
289                         GUSregb(voice << 5) &= 0x7f; /* clear voice reg irq bit */
290                         if (!GUSregd(voicewavetableirq))
291                             GUSregb(IRQStatReg2x6) &= 0xdf;
292                         if (!GUSregb(IRQStatReg2x6))
293                             GUS_irqclear(state, state->gusirq);
294                         GUSregb(SynVoiceIRQ8f) = voice | 0x60; /* (bit==0 => IRQ wartend) */
295                         return;
296                     }
297                 }
298             }
299             else if (GUSregd(voicevolrampirq)) /* VolRamp IRQ */
300             {
301                 for (voice = 0; voice < 31; voice++)
302                 {
303                     if (GUSregd(voicevolrampirq) & (1 << voice))
304                     {
305                         GUSregd(voicevolrampirq) ^= (1 << voice); /* clear IRQ bit */
306                         GUSregb((voice << 5) + VSRVolRampControl) &= 0x7f; /* clear voice volume reg irq bit */
307                         if (!GUSregd(voicevolrampirq))
308                             GUSregb(IRQStatReg2x6) &= 0xbf;
309                         if (!GUSregb(IRQStatReg2x6))
310                             GUS_irqclear(state, state->gusirq);
311                         GUSregb(SynVoiceIRQ8f) = voice | 0x80; /* (bit==0 => IRQ wartend) */
312                         return;
313                     }
314                 }
315             }
316             GUSregb(SynVoiceIRQ8f) = 0xe8; /* kein IRQ wartet */
317         }
318         break;
319     case 0x304:
320     case 0x305:
321         {
322             uint16_t         writedata = (uint16_t) data;
323             uint16_t         readmask = 0x0000;
324             if (size == 1)
325             {
326                 readmask = 0xff00;
327                 writedata &= 0xff;
328                 if ((port & 0xff0f) == 0x305)
329                 {
330                     writedata = (uint16_t) (writedata << 8);
331                     readmask = 0x00ff;
332                 }
333             }
334             switch (GUSregb(FunkSelReg3x3))
335             {
336                 /* voice specific functions */
337             case 0x00:
338             case 0x01:
339             case 0x02:
340             case 0x03:
341             case 0x04:
342             case 0x05:
343             case 0x06:
344             case 0x07:
345             case 0x08:
346             case 0x09:
347             case 0x0a:
348             case 0x0b:
349             case 0x0c:
350             case 0x0d:
351                 {
352                     int             offset;
353                     if (!(GUSregb(GUS4cReset) & 0x01))
354                         break;  /* reset flag active? */
355                     offset = 2 * (GUSregb(FunkSelReg3x3) & 0x0f);
356                     offset += (GUSregb(VoiceSelReg3x2) & 0x1f) << 5; /*  = Voice*32 + Funktion*2 */
357                     GUSregw(offset) = (uint16_t) ((GUSregw(offset) & readmask) | writedata);
358                 }
359                 break;
360                 /* voice unspecific functions */
361             case 0x0e:         /* NumVoices */
362                 GUSregb(NumVoices) = (uint8_t) data;
363                 break;
364             /* case 0x0f:      */ /* read only */
365                 /* common functions */
366             case 0x41:         /* DramDMAContrReg */
367                 GUSregb(GUS41DMACtrl) = (uint8_t) data;
368                 if (data & 0x01)
369                     GUS_dmarequest(state);
370                 break;
371             case 0x42:         /* DramDMAmemPosReg */
372                 GUSregw(GUS42DMAStart) = (GUSregw(GUS42DMAStart) & readmask) | writedata;
373                 GUSregb(GUS50DMAHigh) &= 0xf; /* compatibility stuff... */
374                 break;
375             case 0x43:         /* DRAMaddrLo */
376                 GUSregd(GUSDRAMPOS24bit) =
377                     (GUSregd(GUSDRAMPOS24bit) & (readmask | 0xff0000)) | writedata;
378                 break;
379             case 0x44:         /* DRAMaddrHi */
380                 GUSregd(GUSDRAMPOS24bit) =
381                     (GUSregd(GUSDRAMPOS24bit) & 0xffff) | ((data & 0x0f) << 16);
382                 break;
383             case 0x45:         /* TCtrlReg */
384                 GUSregb(GUS45TimerCtrl) = (uint8_t) data;
385                 if (!(data & 0x20))
386                     GUSregb(TimerStatus2x8) &= 0xe7;    /* sb IRQ dis? -> clear 2x8/2xC sb IRQ flags */
387                 if (!(data & 0x02))
388                     GUSregb(TimerStatus2x8) &= 0xfe;    /* adlib data IRQ dis? -> clear 2x8 adlib IRQ flag */
389                 if (!(GUSregb(TimerStatus2x8) & 0x19))
390                     GUSregb(IRQStatReg2x6) &= 0xef;     /* 0xe6; $$clear IRQ if both IRQ bits are inactive or cleared */
391                 /* catch up delayed timer IRQs: */
392                 if ((GUSregw(TimerIRQs) > 1) && (GUSregb(TimerDataReg2x9) & 3))
393                 {
394                     if (GUSregb(TimerDataReg2x9) & 1)   /* start timer 1 (80us decrement rate) */
395                     {
396                         if (!(GUSregb(TimerDataReg2x9) & 0x40))
397                             GUSregb(TimerStatus2x8) |= 0xc0;    /* maskable bits */
398                         if (data & 4) /* timer1 irq enable */
399                         {
400                             GUSregb(TimerStatus2x8) |= 4;       /* nonmaskable bit */
401                             GUSregb(IRQStatReg2x6) |= 4;        /* timer 1 irq pending */
402                         }
403                     }
404                     if (GUSregb(TimerDataReg2x9) & 2)   /* start timer 2 (320us decrement rate) */
405                     {
406                         if (!(GUSregb(TimerDataReg2x9) & 0x20))
407                             GUSregb(TimerStatus2x8) |= 0xa0;    /* maskable bits */
408                         if (data & 8) /* timer2 irq enable */
409                         {
410                             GUSregb(TimerStatus2x8) |= 2;       /* nonmaskable bit */
411                             GUSregb(IRQStatReg2x6) |= 8;        /* timer 2 irq pending */
412                         }
413                     }
414                     GUSregw(TimerIRQs)--;
415                     if (GUSregw(BusyTimerIRQs) > 1)
416                         GUSregw(BusyTimerIRQs)--;
417                     else
418                         GUSregw(BusyTimerIRQs) =
419                             GUS_irqrequest(state, state->gusirq, GUSregw(TimerIRQs));
420                 }
421                 else
422                     GUSregw(TimerIRQs) = 0;
423 
424                 if (!(data & 0x04))
425                 {
426                     GUSregb(TimerStatus2x8) &= 0xfb; /* clear non-maskable timer1 bit */
427                     GUSregb(IRQStatReg2x6)  &= 0xfb;
428                 }
429                 if (!(data & 0x08))
430                 {
431                     GUSregb(TimerStatus2x8) &= 0xfd; /* clear non-maskable timer2 bit */
432                     GUSregb(IRQStatReg2x6)  &= 0xf7;
433                 }
434                 if (!GUSregb(IRQStatReg2x6))
435                     GUS_irqclear(state, state->gusirq);
436                 break;
437             case 0x46:          /* Counter1 */
438                 GUSregb(GUS46Counter1) = (uint8_t) data;
439                 break;
440             case 0x47:          /* Counter2 */
441                 GUSregb(GUS47Counter2) = (uint8_t) data;
442                 break;
443             /* case 0x48:       */ /* sampling freq reg not emulated (same as interwave) */
444             case 0x49:          /* SampCtrlReg */
445                 GUSregb(GUS49SampCtrl) = (uint8_t) data;
446                 break;
447             /* case 0x4b:       */ /* joystick trim not emulated */
448             case 0x4c:          /* GUSreset */
449                 GUSregb(GUS4cReset) = (uint8_t) data;
450                 if (!(GUSregb(GUS4cReset) & 1)) /* reset... */
451                 {
452                     GUSregd(voicewavetableirq) = 0;
453                     GUSregd(voicevolrampirq) = 0;
454                     GUSregw(TimerIRQs) = 0;
455                     GUSregw(BusyTimerIRQs) = 0;
456                     GUSregb(NumVoices) = 0xcd;
457                     GUSregb(IRQStatReg2x6) = 0;
458                     GUSregb(TimerStatus2x8) = 0;
459                     GUSregb(AdLibData2x9) = 0;
460                     GUSregb(TimerDataReg2x9) = 0;
461                     GUSregb(GUS41DMACtrl) = 0;
462                     GUSregb(GUS45TimerCtrl) = 0;
463                     GUSregb(GUS49SampCtrl) = 0;
464                     GUSregb(GUS4cReset) &= 0xf9; /* clear IRQ and DAC enable bits */
465                     GUS_irqclear(state, state->gusirq);
466                 }
467                 /* IRQ enable bit checked elsewhere */
468                 /* EnableDAC bit may be used by external callers */
469                 break;
470             }
471         }
472         break;
473     case 0x307:                /* DRAMaccess */
474         {
475             uint8_t        *adr;
476             adr = state->himemaddr + (GUSregd(GUSDRAMPOS24bit) & 0xfffff);
477             *adr = (uint8_t) data;
478         }
479         break;
480     }
481 }
482 
483 /* Attention when breaking up a single DMA transfer to multiple ones:
484  * it may lead to multiple terminal count interrupts and broken transfers:
485  *
486  * 1. Whenever you transfer a piece of data, the gusemu callback is invoked
487  * 2. The callback may generate a TC irq (if the register was set up to do so)
488  * 3. The irq may result in the program using the GUS to reprogram the GUS
489  *
490  * Some programs also decide to upload by just checking if TC occurs
491  * (via interrupt or a cleared GUS dma flag)
492  * and then start the next transfer, without checking DMA state
493  *
494  * Thus: Always make sure to set the TC flag correctly!
495  *
496  * Note that the genuine GUS had a granularity of 16 bytes/words for low/high DMA
497  * while later cards had atomic granularity provided by an additional GUS50DMAHigh register
498  * GUSemu also uses this register to support byte-granular transfers for better compatibility
499  * with emulators other than GUSemu32
500  */
501 
gus_dma_transferdata(GUSEmuState * state,char * dma_addr,unsigned int count,int TC)502 void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int count, int TC)
503 {
504     /* this function gets called by the callback function as soon as a DMA transfer is about to start
505      * dma_addr is a translated address within accessible memory, not the physical one,
506      * count is (real dma count register)+1
507      * note that the amount of bytes transferred is fully determined by values in the DMA registers
508      * do not forget to update DMA states after transferring the entire block:
509      * DREQ cleared & TC asserted after the _whole_ transfer */
510 
511     char           *srcaddr;
512     char           *destaddr;
513     char            msbmask = 0;
514     uint8_t        *gusptr;
515     gusptr = state->gusdatapos;
516 
517     srcaddr = dma_addr; /* system memory address */
518     {
519         int             offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf);
520         if (state->gusdma >= 4)
521             offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */
522         destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */
523     }
524 
525     GUSregw(GUS42DMAStart) += (uint16_t)  (count >> 4);                           /* ToDo: add 16bit GUS page limit? */
526     GUSregb(GUS50DMAHigh)   = (uint8_t) ((count + GUSregb(GUS50DMAHigh)) & 0xf); /* ToDo: add 16bit GUS page limit? */
527 
528     if (GUSregb(GUS41DMACtrl) & 0x02)   /* direction, 0 := sysram->gusram */
529     {
530         char           *tmpaddr = destaddr;
531         destaddr = srcaddr;
532         srcaddr = tmpaddr;
533     }
534 
535     if ((GUSregb(GUS41DMACtrl) & 0x80) && (!(GUSregb(GUS41DMACtrl) & 0x02)))
536         msbmask = (const char) 0x80;    /* invert MSB */
537     for (; count > 0; count--)
538     {
539         if (GUSregb(GUS41DMACtrl) & 0x40)
540             *(destaddr++) = *(srcaddr++);               /* 16 bit lobyte */
541         else
542             *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 8 bit */
543         if (state->gusdma >= 4)
544             *(destaddr++) = (msbmask ^ (*(srcaddr++))); /* 16 bit hibyte */
545     }
546 
547     if (TC)
548     {
549         (GUSregb(GUS41DMACtrl)) &= 0xfe;        /* clear DMA request bit */
550         if (GUSregb(GUS41DMACtrl) & 0x20)       /* DMA terminal count IRQ */
551         {
552             GUSregb(IRQStatReg2x6) |= 0x80;
553             GUS_irqrequest(state, state->gusirq, 1);
554         }
555     }
556 }
557