1 /** @file 2 IA32/x64 architecture specific defintions needed by debug transfer protocol.It is only 3 intended to be used by Debug related module implementation. 4 5 Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef __PROCESSOR_CONTEXT_H__ 11 #define __PROCESSOR_CONTEXT_H__ 12 13 // 14 // IA-32/x64 processor register index table 15 // 16 #define SOFT_DEBUGGER_REGISTER_DR0 0x00 17 #define SOFT_DEBUGGER_REGISTER_DR1 0x01 18 #define SOFT_DEBUGGER_REGISTER_DR2 0x02 19 #define SOFT_DEBUGGER_REGISTER_DR3 0x03 20 #define SOFT_DEBUGGER_REGISTER_DR6 0x04 21 #define SOFT_DEBUGGER_REGISTER_DR7 0x05 22 #define SOFT_DEBUGGER_REGISTER_EFLAGS 0x06 23 #define SOFT_DEBUGGER_REGISTER_LDTR 0x07 24 #define SOFT_DEBUGGER_REGISTER_TR 0x08 25 #define SOFT_DEBUGGER_REGISTER_GDTR0 0x09 // the low 32bit of GDTR 26 #define SOFT_DEBUGGER_REGISTER_GDTR1 0x0A // the high 32bit of GDTR 27 #define SOFT_DEBUGGER_REGISTER_IDTR0 0x0B // the low 32bit of IDTR 28 #define SOFT_DEBUGGER_REGISTER_IDTR1 0x0C // the high 32bot of IDTR 29 #define SOFT_DEBUGGER_REGISTER_EIP 0x0D 30 #define SOFT_DEBUGGER_REGISTER_GS 0x0E 31 #define SOFT_DEBUGGER_REGISTER_FS 0x0F 32 #define SOFT_DEBUGGER_REGISTER_ES 0x10 33 #define SOFT_DEBUGGER_REGISTER_DS 0x11 34 #define SOFT_DEBUGGER_REGISTER_CS 0x12 35 #define SOFT_DEBUGGER_REGISTER_SS 0x13 36 #define SOFT_DEBUGGER_REGISTER_CR0 0x14 37 #define SOFT_DEBUGGER_REGISTER_CR1 0x15 38 #define SOFT_DEBUGGER_REGISTER_CR2 0x16 39 #define SOFT_DEBUGGER_REGISTER_CR3 0x17 40 #define SOFT_DEBUGGER_REGISTER_CR4 0x18 41 42 #define SOFT_DEBUGGER_REGISTER_DI 0x19 43 #define SOFT_DEBUGGER_REGISTER_SI 0x1A 44 #define SOFT_DEBUGGER_REGISTER_BP 0x1B 45 #define SOFT_DEBUGGER_REGISTER_SP 0x1C 46 #define SOFT_DEBUGGER_REGISTER_DX 0x1D 47 #define SOFT_DEBUGGER_REGISTER_CX 0x1E 48 #define SOFT_DEBUGGER_REGISTER_BX 0x1F 49 #define SOFT_DEBUGGER_REGISTER_AX 0x20 50 51 // 52 // This below registers are only available for x64 (not valid for Ia32 mode) 53 // 54 #define SOFT_DEBUGGER_REGISTER_CR8 0x21 55 #define SOFT_DEBUGGER_REGISTER_R8 0x22 56 #define SOFT_DEBUGGER_REGISTER_R9 0x23 57 #define SOFT_DEBUGGER_REGISTER_R10 0x24 58 #define SOFT_DEBUGGER_REGISTER_R11 0x25 59 #define SOFT_DEBUGGER_REGISTER_R12 0x26 60 #define SOFT_DEBUGGER_REGISTER_R13 0x27 61 #define SOFT_DEBUGGER_REGISTER_R14 0x28 62 #define SOFT_DEBUGGER_REGISTER_R15 0x29 63 64 // 65 // This below registers are FP / MMX / XMM registers 66 // 67 #define SOFT_DEBUGGER_REGISTER_FP_BASE 0x30 68 69 #define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x00) 70 #define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x01) 71 #define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x02) 72 #define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x03) 73 #define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x04) 74 #define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x05) 75 #define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x06) 76 #define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x07) 77 #define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x08) 78 #define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x09) 79 #define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0A) 80 #define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0B) 81 #define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0C) 82 #define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0D) 83 #define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0E) 84 #define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0F) 85 #define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x10) 86 #define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x11) 87 #define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x12) 88 #define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x13) 89 #define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x14) 90 #define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x15) 91 #define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x16) 92 #define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x17) 93 #define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x18) 94 #define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x19) 95 #define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1A) 96 #define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1B) 97 #define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1C) 98 #define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1D) 99 #define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1E) 100 #define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1F) 101 #define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x20) 102 #define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x21) 103 #define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x22) 104 #define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x23) 105 #define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x24) 106 #define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x25) 107 #define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x26) 108 #define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x27) 109 #define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x28) 110 #define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x29) 111 112 #define SOFT_DEBUGGER_REGISTER_MAX SOFT_DEBUGGER_REGISTER_MM7 113 114 #define SOFT_DEBUGGER_MSR_EFER (0xC0000080) 115 116 #pragma pack(1) 117 118 /// 119 /// FXSAVE_STATE 120 /// FP / MMX / XMM registers (see fxrstor instruction definition) 121 /// 122 typedef struct { 123 UINT16 Fcw; 124 UINT16 Fsw; 125 UINT16 Ftw; 126 UINT16 Opcode; 127 UINT32 Eip; 128 UINT16 Cs; 129 UINT16 Reserved1; 130 UINT32 DataOffset; 131 UINT16 Ds; 132 UINT8 Reserved2[2]; 133 UINT32 Mxcsr; 134 UINT32 Mxcsr_Mask; 135 UINT8 St0Mm0[10]; 136 UINT8 Reserved3[6]; 137 UINT8 St1Mm1[10]; 138 UINT8 Reserved4[6]; 139 UINT8 St2Mm2[10]; 140 UINT8 Reserved5[6]; 141 UINT8 St3Mm3[10]; 142 UINT8 Reserved6[6]; 143 UINT8 St4Mm4[10]; 144 UINT8 Reserved7[6]; 145 UINT8 St5Mm5[10]; 146 UINT8 Reserved8[6]; 147 UINT8 St6Mm6[10]; 148 UINT8 Reserved9[6]; 149 UINT8 St7Mm7[10]; 150 UINT8 Reserved10[6]; 151 UINT8 Xmm0[16]; 152 UINT8 Xmm1[16]; 153 UINT8 Xmm2[16]; 154 UINT8 Xmm3[16]; 155 UINT8 Xmm4[16]; 156 UINT8 Xmm5[16]; 157 UINT8 Xmm6[16]; 158 UINT8 Xmm7[16]; 159 UINT8 Reserved11[14 * 16]; 160 } DEBUG_DATA_IA32_FX_SAVE_STATE; 161 162 /// 163 /// IA-32 processor context definition 164 /// 165 typedef struct { 166 UINT32 ExceptionData; 167 DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState; 168 UINT32 Dr0; 169 UINT32 Dr1; 170 UINT32 Dr2; 171 UINT32 Dr3; 172 UINT32 Dr6; 173 UINT32 Dr7; 174 UINT32 Eflags; 175 UINT32 Ldtr; 176 UINT32 Tr; 177 UINT32 Gdtr[2]; 178 UINT32 Idtr[2]; 179 UINT32 Eip; 180 UINT32 Gs; 181 UINT32 Fs; 182 UINT32 Es; 183 UINT32 Ds; 184 UINT32 Cs; 185 UINT32 Ss; 186 UINT32 Cr0; 187 UINT32 Cr1; ///< Reserved 188 UINT32 Cr2; 189 UINT32 Cr3; 190 UINT32 Cr4; 191 UINT32 Edi; 192 UINT32 Esi; 193 UINT32 Ebp; 194 UINT32 Esp; 195 UINT32 Edx; 196 UINT32 Ecx; 197 UINT32 Ebx; 198 UINT32 Eax; 199 } DEBUG_DATA_IA32_SYSTEM_CONTEXT; 200 201 /// 202 /// FXSAVE_STATE 203 /// FP / MMX / XMM registers (see fxrstor instruction definition) 204 /// 205 typedef struct { 206 UINT16 Fcw; 207 UINT16 Fsw; 208 UINT16 Ftw; 209 UINT16 Opcode; 210 UINT32 Eip; 211 UINT16 Cs; 212 UINT16 Reserved1; 213 UINT32 DataOffset; 214 UINT16 Ds; 215 UINT8 Reserved2[2]; 216 UINT32 Mxcsr; 217 UINT32 Mxcsr_Mask; 218 UINT8 St0Mm0[10]; 219 UINT8 Reserved3[6]; 220 UINT8 St1Mm1[10]; 221 UINT8 Reserved4[6]; 222 UINT8 St2Mm2[10]; 223 UINT8 Reserved5[6]; 224 UINT8 St3Mm3[10]; 225 UINT8 Reserved6[6]; 226 UINT8 St4Mm4[10]; 227 UINT8 Reserved7[6]; 228 UINT8 St5Mm5[10]; 229 UINT8 Reserved8[6]; 230 UINT8 St6Mm6[10]; 231 UINT8 Reserved9[6]; 232 UINT8 St7Mm7[10]; 233 UINT8 Reserved10[6]; 234 UINT8 Xmm0[16]; 235 UINT8 Xmm1[16]; 236 UINT8 Xmm2[16]; 237 UINT8 Xmm3[16]; 238 UINT8 Xmm4[16]; 239 UINT8 Xmm5[16]; 240 UINT8 Xmm6[16]; 241 UINT8 Xmm7[16]; 242 UINT8 Xmm8[16]; 243 UINT8 Xmm9[16]; 244 UINT8 Xmm10[16]; 245 UINT8 Xmm11[16]; 246 UINT8 Xmm12[16]; 247 UINT8 Xmm13[16]; 248 UINT8 Xmm14[16]; 249 UINT8 Xmm15[16]; 250 UINT8 Reserved11[6 * 16]; 251 } DEBUG_DATA_X64_FX_SAVE_STATE; 252 253 /// 254 /// x64 processor context definition 255 /// 256 typedef struct { 257 UINT64 ExceptionData; 258 DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState; 259 UINT64 Dr0; 260 UINT64 Dr1; 261 UINT64 Dr2; 262 UINT64 Dr3; 263 UINT64 Dr6; 264 UINT64 Dr7; 265 UINT64 Eflags; 266 UINT64 Ldtr; 267 UINT64 Tr; 268 UINT64 Gdtr[2]; 269 UINT64 Idtr[2]; 270 UINT64 Eip; 271 UINT64 Gs; 272 UINT64 Fs; 273 UINT64 Es; 274 UINT64 Ds; 275 UINT64 Cs; 276 UINT64 Ss; 277 UINT64 Cr0; 278 UINT64 Cr1; ///< Reserved 279 UINT64 Cr2; 280 UINT64 Cr3; 281 UINT64 Cr4; 282 UINT64 Rdi; 283 UINT64 Rsi; 284 UINT64 Rbp; 285 UINT64 Rsp; 286 UINT64 Rdx; 287 UINT64 Rcx; 288 UINT64 Rbx; 289 UINT64 Rax; 290 UINT64 Cr8; 291 UINT64 R8; 292 UINT64 R9; 293 UINT64 R10; 294 UINT64 R11; 295 UINT64 R12; 296 UINT64 R13; 297 UINT64 R14; 298 UINT64 R15; 299 } DEBUG_DATA_X64_SYSTEM_CONTEXT; 300 301 #pragma pack() 302 303 #endif 304 305