1 /* Copyright 2013-2014 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 18 /* 19 * IBM System P PSI (Processor Service Interface) 20 */ 21 #ifndef __PSI_H 22 #define __PSI_H 23 24 #include <skiboot.h> 25 26 /* 27 * PSI Host Bridge Registers (MMIO) 28 * 29 * The PSI interface is the bridge to the FPS, it has its own 30 * registers. The FSP registers appear at an offset within the 31 * aperture defined by the PSI_FSPBAR 32 */ 33 /* Base address of the PSI MMIO space and LSB is the enable/valid bit */ 34 #define PSIHB_BBAR 0x00 35 36 /* FSP MMIO region -- this is where the mbx regs are (offset defined below) */ 37 #define PSIHB_FSPBAR 0x08 38 39 /* FSP MMIO region mask register -- determines size of region */ 40 #define PSIHB_FSPMMR 0x10 41 42 /* TCE address register */ 43 #define PSIHB_TAR 0x18 44 #define PSIHB_TAR_8K_ENTRIES 0 45 #define PSIHB_TAR_16K_ENTRIES 1 46 #define PSIHB_TAR_256K_ENTRIES 2 /* P8 only */ 47 #define PSIHB_TAR_512K_ENTRIES 4 /* P8 only */ 48 49 /* PSI Host Bridge Control Register 50 * 51 * note: TCE_ENABLE moved to the new PSIHB_PHBSCR on P8 but is 52 * the same bit position 53 */ 54 #define PSIHB_CR 0x20 55 #define PSIHB_CR_FSP_CMD_ENABLE PPC_BIT(0) 56 #define PSIHB_CR_FSP_MMIO_ENABLE PPC_BIT(1) 57 #define PSIHB_CR_TCE_ENABLE PPC_BIT(2) 58 #define PSIHB_CR_FSP_IRQ_ENABLE PPC_BIT(3) 59 #define PSIHB_CR_FSP_ERR_RSP_ENABLE PPC_BIT(4) 60 #define PSIHB_CR_PSI_LINK_ENABLE PPC_BIT(5) 61 #define PSIHB_CR_FSP_RESET PPC_BIT(6) 62 #define PSIHB_CR_PSIHB_RESET PPC_BIT(7) 63 #define PSIHB_CR_PSI_IRQ PPC_BIT(16) /* PSIHB interrupt */ 64 #define PSIHB_CR_FSP_IRQ PPC_BIT(17) /* FSP interrupt */ 65 #define PSIHB_CR_FSP_LINK_ACTIVE PPC_BIT(18) /* FSP link active */ 66 67 /* Error conditions in the GXHB */ 68 #define PSIHB_CR_PSI_ERROR PPC_BIT(32) /* PSI error */ 69 #define PSIHB_CR_PSI_LINK_INACTIVE PPC_BIT(33) /* Link inactive */ 70 #define PSIHB_CR_FSP_ACK_TIMEOUT PPC_BIT(34) /* FSP ack timeout */ 71 #define PSIHB_CR_MMIO_LOAD_TIMEOUT PPC_BIT(35) /* MMIO load timeout */ 72 #define PSIHB_CR_MMIO_LENGTH_ERROR PPC_BIT(36) /* MMIO length error */ 73 #define PSIHB_CR_MMIO_ADDRESS_ERROR PPC_BIT(37) /* MMIO address error */ 74 #define PSIHB_CR_MMIO_TYPE_ERROR PPC_BIT(38) /* MMIO type error */ 75 #define PSIHB_CR_UE PPC_BIT(39) /* UE detected */ 76 #define PSIHB_CR_PARITY_ERROR PPC_BIT(40) /* Parity error */ 77 #define PSIHB_CR_SYNC_ERR_ALERT1 PPC_BIT(41) /* Sync alert 1 */ 78 #define PSIHB_CR_SYNC_ERR_ALERT2 PPC_BIT(42) /* Sync alert 2 */ 79 #define PSIHB_CR_FSP_COMMAND_ERROR PPC_BIT(43) /* FSP cmd error */ 80 81 /* PSI Status / Error Mask Register */ 82 #define PSIHB_SEMR 0x28 83 84 /* XIVR and BUID used for PSI interrupts on P8 */ 85 #define PSIHB_XIVR_FSP 0x30 86 #define PSIHB_XIVR_OCC 0x60 87 #define PSIHB_XIVR_FSI 0x68 88 #define PSIHB_XIVR_LPC 0x70 89 #define PSIHB_XIVR_LOCAL_ERR 0x78 90 #define PSIHB_XIVR_HOST_ERR 0x80 91 #define PSIHB_IRSN 0x88 92 #define PSIHB_IRSN_COMP PPC_BITMASK(0,18) 93 #define PSIHB_IRSN_IRQ_MUX PPC_BIT(28) 94 #define PSIHB_IRSN_IRQ_RESET PPC_BIT(29) 95 #define PSIHB_IRSN_DOWNSTREAM_EN PPC_BIT(30) 96 #define PSIHB_IRSN_UPSTREAM_EN PPC_BIT(31) 97 #define PSIHB_IRSN_MASK PPC_BITMASK(32,50) 98 99 #define PSIHB_IRQ_STATUS 0x58 100 #define PSIHB_IRQ_STAT_OCC PPC_BIT(27) 101 #define PSIHB_IRQ_STAT_FSI PPC_BIT(28) 102 #define PSIHB_IRQ_STAT_LPC PPC_BIT(29) 103 #define PSIHB_IRQ_STAT_LOCAL_ERR PPC_BIT(30) 104 #define PSIHB_IRQ_STAT_HOST_ERR PPC_BIT(31) 105 106 /* Secure version of CR for P8 and P9 (TCE enable bit) */ 107 #define PSIHB_PHBSCR 0x90 108 109 /* P9 registers */ 110 111 #define PSIHB_INTERRUPT_CONTROL 0x58 112 #define PSIHB_IRQ_METHOD PPC_BIT(0) 113 #define PSIHB_IRQ_RESET PPC_BIT(1) 114 #define PSIHB_ESB_CI_BASE 0x60 115 #define PSIHB_ESB_CI_VALID 1 116 #define PSIHB_ESB_NOTIF_ADDR 0x68 117 #define PSIHB_ESB_NOTIF_VALID 1 118 #define PSIHB_IVT_OFFSET 0x70 119 #define PSIHB_IVT_OFF_SHIFT 32 120 /* 121 * PSI Host Bridge Registers (XSCOM) 122 */ 123 #define PSIHB_XSCOM_P8_BASE 0xa 124 #define PSIHB_XSCOM_P8_HBBAR_EN PPC_BIT(63) 125 #define PSIHB_XSCOM_P8_HBCSR 0xe 126 #define PSIHB_XSCOM_P8_HBCSR_SET 0x12 127 #define PSIHB_XSCOM_P8_HBCSR_CLR 0x13 128 #define PSIHB_XSCOM_P8_HBSCR_FSP_IRQ PPC_BIT(17) 129 130 #define PSIHB_XSCOM_P9_BASE 0xa 131 #define PSIHB_XSCOM_P9_HBBAR_EN PPC_BIT(63) 132 #define PSIHB_XSCOM_P9_HBCSR 0xe 133 #define PSIHB_XSCOM_P9_HBCSR_SET 0x12 134 #define PSIHB_XSCOM_P9_HBCSR_CLR 0x13 135 #define PSIHB_XSCOM_P9_HBSCR_FSP_IRQ PPC_BIT(17) 136 137 /* P9 PSI Interrupts */ 138 #define P9_PSI_IRQ_PSI 0 139 #define P9_PSI_IRQ_OCC 1 140 #define P9_PSI_IRQ_FSI 2 141 #define P9_PSI_IRQ_LPCHC 3 142 #define P9_PSI_IRQ_LOCAL_ERR 4 143 #define P9_PSI_IRQ_GLOBAL_ERR 5 144 #define P9_PSI_IRQ_EXTERNAL 6 145 #define P9_PSI_IRQ_LPC_SIRQ0 7 146 #define P9_PSI_IRQ_LPC_SIRQ1 8 147 #define P9_PSI_IRQ_LPC_SIRQ2 9 148 #define P9_PSI_IRQ_LPC_SIRQ3 10 149 #define P9_PSI_IRQ_SBE_I2C 11 150 #define P9_PSI_IRQ_DIO 12 151 #define P9_PSI_IRQ_PSU 13 152 #define P9_PSI_NUM_IRQS 14 153 154 155 156 /* 157 * Layout of the PSI DMA address space 158 * 159 * On P8, we use a larger mapping of 256K TCEs which provides 160 * us with a 1G window in order to fit the trace buffers 161 * 162 * Currently we have: 163 * 164 * - 4x256K serial areas (each divided in 2: in and out buffers) 165 * - 1M region for inbound buffers 166 * - 2M region for generic data fetches 167 */ 168 #define PSI_DMA_SER0_BASE 0x00000000 169 #define PSI_DMA_SER0_SIZE 0x00040000 170 #define PSI_DMA_SER1_BASE 0x00040000 171 #define PSI_DMA_SER1_SIZE 0x00040000 172 #define PSI_DMA_SER2_BASE 0x00080000 173 #define PSI_DMA_SER2_SIZE 0x00040000 174 #define PSI_DMA_SER3_BASE 0x000c0000 175 #define PSI_DMA_SER3_SIZE 0x00040000 176 #define PSI_DMA_INBOUND_BUF 0x00100000 177 #define PSI_DMA_INBOUND_SIZE 0x00100000 178 #define PSI_DMA_FETCH 0x00200000 179 #define PSI_DMA_FETCH_SIZE 0x00800000 180 #define PSI_DMA_NVRAM_BODY 0x00a00000 181 #define PSI_DMA_NVRAM_BODY_SZ 0x00100000 182 #define PSI_DMA_NVRAM_TRIPL 0x00b00000 183 #define PSI_DMA_NVRAM_TRIPL_SZ 0x00001000 184 #define PSI_DMA_OP_PANEL_MISC 0x00b01000 185 #define PSI_DMA_OP_PANEL_SIZE 0x00001000 186 #define PSI_DMA_GET_SYSPARAM 0x00b02000 187 #define PSI_DMA_GET_SYSPARAM_SZ 0x00001000 188 #define PSI_DMA_SET_SYSPARAM 0x00b03000 189 #define PSI_DMA_SET_SYSPARAM_SZ 0x00001000 190 #define PSI_DMA_ERRLOG_READ_BUF 0x00b04000 191 #define PSI_DMA_ERRLOG_READ_BUF_SZ 0x00040000 192 #define PSI_DMA_ELOG_PANIC_WRITE_BUF 0x00b44000 193 #define PSI_DMA_ELOG_PANIC_WRITE_BUF_SZ 0x00010000 194 #define PSI_DMA_ERRLOG_WRITE_BUF 0x00b54000 195 #define PSI_DMA_ERRLOG_WRITE_BUF_SZ 0x00040000 196 #define PSI_DMA_ELOG_WR_TO_HOST_BUF 0x00b94000 /* Unused */ 197 #define PSI_DMA_ELOG_WR_TO_HOST_BUF_SZ 0x00010000 198 #define PSI_DMA_HBRT_LOG_WRITE_BUF 0x00ba4000 199 #define PSI_DMA_HBRT_LOG_WRITE_BUF_SZ 0x00001000 200 #define PSI_DMA_CODE_UPD 0x00c04000 201 #define PSI_DMA_CODE_UPD_SIZE 0x01001000 202 #define PSI_DMA_DUMP_DATA 0x01c05000 203 #define PSI_DMA_DUMP_DATA_SIZE 0x00500000 204 #define PSI_DMA_SENSOR_BUF 0x02105000 205 #define PSI_DMA_SENSOR_BUF_SZ 0x00080000 206 #define PSI_DMA_MDST_TABLE 0x02185000 207 #define PSI_DMA_MDST_TABLE_SIZE 0x00001000 208 #define PSI_DMA_HYP_DUMP 0x02186000 209 #define PSI_DMA_HYP_DUMP_SIZE 0x01000000 210 #define PSI_DMA_PCIE_INVENTORY 0x03186000 211 #define PSI_DMA_PCIE_INVENTORY_SIZE 0x00010000 212 #define PSI_DMA_LED_BUF 0x03196000 213 #define PSI_DMA_LED_BUF_SZ 0x00001000 214 #define PSI_DMA_LOC_COD_BUF 0x03197000 215 #define PSI_DMA_LOC_COD_BUF_SZ 0x00008000 216 #define PSI_DMA_MEMCONS 0x0319f000 217 #define PSI_DMA_MEMCONS_SZ 0x00001000 218 #define PSI_DMA_LOG_BUF 0x03200000 219 #define PSI_DMA_LOG_BUF_SZ 0x00100000 /* INMEM_CON_LEN */ 220 #define PSI_DMA_PLAT_REQ_BUF 0x03300000 221 #define PSI_DMA_PLAT_REQ_BUF_SIZE 0x00001000 222 #define PSI_DMA_PLAT_RESP_BUF 0x03301000 223 #define PSI_DMA_PLAT_RESP_BUF_SIZE 0x00001000 224 /* 225 * Our PRD interface can handle upto 64KB data transfer between 226 * OPAL - opal-prd. Hence adding TCE size as 68KB. If we increase 227 * OPAL - opal-prd message size, then we have to fix this. 228 */ 229 #define PSI_DMA_HBRT_FSP_MSG 0x03302000 230 #define PSI_DMA_HBRT_FSP_MSG_SIZE 0x00011000 231 232 /* P8 only mappings */ 233 #define PSI_DMA_TRACE_BASE 0x04000000 234 235 struct psi { 236 struct list_node list; 237 uint64_t xscom_base; 238 void *regs; 239 void *esb_mmio; 240 unsigned int chip_id; 241 unsigned int interrupt; 242 bool active; 243 bool no_lpc_irqs; 244 struct dt_node *node; 245 }; 246 247 extern void psi_set_link_polling(bool active); 248 249 extern struct psi *first_psi; 250 extern void psi_init(void); 251 extern struct psi *psi_find_link(uint32_t chip_id); 252 extern void psi_init_for_fsp(struct psi *psi); 253 extern void psi_disable_link(struct psi *psi); 254 extern void psi_reset_fsp(struct psi *psi); 255 extern bool psi_check_link_active(struct psi *psi); 256 extern bool psi_poll_fsp_interrupt(struct psi *psi); 257 extern struct psi *psi_find_functional_chip(void); 258 259 /* Interrupts */ 260 extern void psi_irq_reset(void); 261 extern void psi_enable_fsp_interrupt(struct psi *psi); 262 extern void psi_fsp_link_in_use(struct psi *psi); 263 264 /* 265 * Must be called by the platform probe() function as the policy 266 * is established before platform.init 267 * 268 * This defines whether the external interrupt should be passed to 269 * the OS or handled locally in skiboot. Return true for skiboot 270 * handling. Default if not called is Linux. 271 */ 272 #define EXTERNAL_IRQ_POLICY_LINUX false 273 #define EXTERNAL_IRQ_POLICY_SKIBOOT true 274 extern void psi_set_external_irq_policy(bool policy); 275 276 extern struct lock psi_lock; 277 278 #endif /* __PSI_H */ 279