1 /*
2 * TNETV107X: Watchdog timer implementation (for reset)
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <common.h>
23 #include <asm/io.h>
24 #include <asm/arch/clock.h>
25
26 #define MAX_DIV 0xFFFE0001
27
28 struct wdt_regs {
29 u32 kick_lock;
30 #define KICK_LOCK_1 0x5555
31 #define KICK_LOCK_2 0xaaaa
32 u32 kick;
33
34 u32 change_lock;
35 #define CHANGE_LOCK_1 0x6666
36 #define CHANGE_LOCK_2 0xbbbb
37 u32 change;
38
39 u32 disable_lock;
40 #define DISABLE_LOCK_1 0x7777
41 #define DISABLE_LOCK_2 0xcccc
42 #define DISABLE_LOCK_3 0xdddd
43 u32 disable;
44
45 u32 prescale_lock;
46 #define PRESCALE_LOCK_1 0x5a5a
47 #define PRESCALE_LOCK_2 0xa5a5
48 u32 prescale;
49 };
50
51 static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
52
53 #define wdt_reg_read(reg) __raw_readl(®s->reg)
54 #define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg)
55
write_prescale_reg(unsigned long prescale_value)56 static int write_prescale_reg(unsigned long prescale_value)
57 {
58 wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
59 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
60 return -1;
61
62 wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
63 if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
64 return -1;
65
66 wdt_reg_write(prescale, prescale_value);
67
68 return 0;
69 }
70
write_change_reg(unsigned long initial_timer_value)71 static int write_change_reg(unsigned long initial_timer_value)
72 {
73 wdt_reg_write(change_lock, CHANGE_LOCK_1);
74 if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
75 return -1;
76
77 wdt_reg_write(change_lock, CHANGE_LOCK_2);
78 if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
79 return -1;
80
81 wdt_reg_write(change, initial_timer_value);
82
83 return 0;
84 }
85
wdt_control(unsigned long disable_value)86 static int wdt_control(unsigned long disable_value)
87 {
88 wdt_reg_write(disable_lock, DISABLE_LOCK_1);
89 if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
90 return -1;
91
92 wdt_reg_write(disable_lock, DISABLE_LOCK_2);
93 if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
94 return -1;
95
96 wdt_reg_write(disable_lock, DISABLE_LOCK_3);
97 if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
98 return -1;
99
100 wdt_reg_write(disable, disable_value);
101 return 0;
102 }
103
wdt_set_period(unsigned long msec)104 static int wdt_set_period(unsigned long msec)
105 {
106 unsigned long change_value, count_value;
107 unsigned long prescale_value = 1;
108 unsigned long refclk_khz, maxdiv;
109 int ret;
110
111 refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
112 maxdiv = (MAX_DIV / refclk_khz);
113
114 if ((!msec) || (msec > maxdiv))
115 return -1;
116
117 count_value = refclk_khz * msec;
118 if (count_value > 0xffff) {
119 change_value = count_value / 0xffff + 1;
120 prescale_value = count_value / change_value;
121 } else {
122 change_value = count_value;
123 }
124
125 ret = write_prescale_reg(prescale_value - 1);
126 if (ret)
127 return ret;
128
129 ret = write_change_reg(change_value);
130 if (ret)
131 return ret;
132
133 return 0;
134 }
135
136 unsigned long last_wdt = -1;
137
wdt_start(unsigned long msecs)138 int wdt_start(unsigned long msecs)
139 {
140 int ret;
141 ret = wdt_control(0);
142 if (ret)
143 return ret;
144 ret = wdt_set_period(msecs);
145 if (ret)
146 return ret;
147 ret = wdt_control(1);
148 if (ret)
149 return ret;
150 ret = wdt_kick();
151 last_wdt = msecs;
152 return ret;
153 }
154
wdt_stop(void)155 int wdt_stop(void)
156 {
157 last_wdt = -1;
158 return wdt_control(0);
159 }
160
wdt_kick(void)161 int wdt_kick(void)
162 {
163 wdt_reg_write(kick_lock, KICK_LOCK_1);
164 if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
165 return -1;
166
167 wdt_reg_write(kick_lock, KICK_LOCK_2);
168 if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
169 return -1;
170
171 wdt_reg_write(kick, 1);
172 return 0;
173 }
174
reset_cpu(ulong addr)175 void reset_cpu(ulong addr)
176 {
177 clk_enable(TNETV107X_LPSC_WDT_ARM);
178 wdt_start(1);
179 wdt_kick();
180 }
181