1 /* 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] 3 * 4 * (C) 2007 Atmel Corporation. 5 * 6 * Common definitions. 7 * Based on AT91SAM9263 datasheet revision B (Preliminary). 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #ifndef AT91SAM9263_H 16 #define AT91SAM9263_H 17 18 /* 19 * Peripheral identifiers/interrupts. 20 */ 21 #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 22 #define AT91_ID_SYS 1 /* System Peripherals */ 23 #define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ 24 #define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ 25 #define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ 26 #define AT91SAM9263_ID_US0 7 /* USART 0 */ 27 #define AT91SAM9263_ID_US1 8 /* USART 1 */ 28 #define AT91SAM9263_ID_US2 9 /* USART 2 */ 29 #define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ 30 #define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ 31 #define AT91SAM9263_ID_CAN 12 /* CAN */ 32 #define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ 33 #define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ 34 #define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ 35 #define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ 36 #define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ 37 #define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ 38 #define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ 39 #define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ 40 #define AT91SAM9263_ID_EMAC 21 /* Ethernet */ 41 #define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ 42 #define AT91SAM9263_ID_UDP 24 /* USB Device Port */ 43 #define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ 44 #define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ 45 #define AT91SAM9263_ID_DMA 27 /* DMA Controller */ 46 #define AT91SAM9263_ID_UHP 29 /* USB Host port */ 47 #define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ 48 #define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ 49 50 #define AT91_EMAC_BASE 0xfffbc000 51 #define AT91_ECC0_BASE 0xffffe000 52 #define AT91_SDRAMC0_BASE 0xffffe200 53 #define AT91_SMC0_BASE 0xffffe400 54 #define AT91_ECC1_BASE 0xffffe600 55 #define AT91_SDRAMC1_BASE 0xffffe800 56 #define AT91_SMC1_BASE 0xffffea00 57 #define AT91_MATRIX_BASE 0xffffec00 58 #define AT91_CCFG_BASE 0xffffed10 59 #define AT91_DBGU_BASE 0xffffee00 60 #define AT91_AIC_BASE 0xfffff000 61 #define AT91_PIO_BASE 0xfffff200 62 #define AT91_PMC_BASE 0xfffffc00 63 #define AT91_RSTC_BASE 0xfffffd00 64 #define AT91_RTT0_BASE 0xfffffd20 65 #define AT91_PIT_BASE 0xfffffd30 66 #define AT91_WDT_BASE 0xfffffd40 67 #define AT91_RTT1_BASE 0xfffffd50 68 #define AT91_GPBR_BASE 0xfffffd60 69 70 #ifdef CONFIG_AT91_LEGACY 71 72 /* 73 * User Peripheral physical base addresses. 74 */ 75 #define AT91SAM9263_BASE_UDP 0xfff78000 76 #define AT91SAM9263_BASE_TCB0 0xfff7c000 77 #define AT91SAM9263_BASE_TC0 0xfff7c000 78 #define AT91SAM9263_BASE_TC1 0xfff7c040 79 #define AT91SAM9263_BASE_TC2 0xfff7c080 80 #define AT91SAM9263_BASE_MCI0 0xfff80000 81 #define AT91SAM9263_BASE_MCI1 0xfff84000 82 #define AT91SAM9263_BASE_TWI 0xfff88000 83 #define AT91SAM9263_BASE_US0 0xfff8c000 84 #define AT91SAM9263_BASE_US1 0xfff90000 85 #define AT91SAM9263_BASE_US2 0xfff94000 86 #define AT91SAM9263_BASE_SSC0 0xfff98000 87 #define AT91SAM9263_BASE_SSC1 0xfff9c000 88 #define AT91SAM9263_BASE_AC97C 0xfffa0000 89 #define AT91SAM9263_BASE_SPI0 0xfffa4000 90 #define AT91SAM9263_BASE_SPI1 0xfffa8000 91 #define AT91SAM9263_BASE_CAN 0xfffac000 92 #define AT91SAM9263_BASE_PWMC 0xfffb8000 93 #define AT91SAM9263_BASE_EMAC 0xfffbc000 94 #define AT91SAM9263_BASE_ISI 0xfffc4000 95 #define AT91SAM9263_BASE_2DGE 0xfffc8000 96 #define AT91_BASE_SYS 0xffffe000 97 98 /* 99 * System Peripherals (offset from AT91_BASE_SYS) 100 */ 101 #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) 102 #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) 103 #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) 104 #define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) 105 #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 106 #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) 107 #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) 108 #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) 109 #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) 110 #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) 111 #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) 112 #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) 113 #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) 114 #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) 115 #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) 116 #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 117 #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 118 #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 119 #define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) 120 #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) 121 #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 122 #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) 123 #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 124 125 #define AT91_USART0 AT91SAM9263_BASE_US0 126 #define AT91_USART1 AT91SAM9263_BASE_US1 127 #define AT91_USART2 AT91SAM9263_BASE_US2 128 129 #define AT91_SMC AT91_SMC0 130 #define AT91_SDRAMC AT91_SDRAMC0 131 132 #endif /* CONFIG_AT91_LEGACY */ 133 134 /* 135 * Internal Memory. 136 */ 137 #define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ 138 #define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ 139 140 #define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ 141 #define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ 142 143 #define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ 144 #define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ 145 146 #define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ 147 #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ 148 #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ 149 150 /* 151 * Cpu Name 152 */ 153 #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" 154 155 #endif 156