1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ASM_ARCH_MXC_MX51_H__ 24 #define __ASM_ARCH_MXC_MX51_H__ 25 26 #define __REG(x) (*((volatile u32 *)(x))) 27 #define __REG16(x) (*((volatile u16 *)(x))) 28 #define __REG8(x) (*((volatile u8 *)(x))) 29 /* 30 * IRAM 31 */ 32 #define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ 33 /* 34 * Graphics Memory of GPU 35 */ 36 #define GPU_BASE_ADDR 0x20000000 37 #define GPU_CTRL_BASE_ADDR 0x30000000 38 #define IPU_CTRL_BASE_ADDR 0x40000000 39 /* 40 * Debug 41 */ 42 #define DEBUG_BASE_ADDR 0x60000000 43 #define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) 44 #define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) 45 #define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) 46 #define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) 47 #define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) 48 #define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) 49 #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) 50 #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) 51 52 /* 53 * SPBA global module enabled #0 54 */ 55 #define SPBA0_BASE_ADDR 0x70000000 56 57 #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 58 #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 59 #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) 60 #define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) 61 #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) 62 #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) 63 #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) 64 #define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) 65 #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) 66 #define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) 67 #define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) 68 #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) 69 70 /* 71 * AIPS 1 72 */ 73 #define AIPS1_BASE_ADDR 0x73F00000 74 75 #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) 76 #define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) 77 #define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 78 #define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 79 #define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) 80 #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) 81 #define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) 82 #define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) 83 #define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) 84 #define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) 85 #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) 86 #define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) 87 #define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 88 #define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 89 #define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) 90 #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) 91 #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) 92 #define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) 93 #define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) 94 #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) 95 96 /* 97 * AIPS 2 98 */ 99 #define AIPS2_BASE_ADDR 0x83F00000 100 101 #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) 102 #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 103 #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) 104 #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) 105 #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) 106 #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) 107 #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) 108 #define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) 109 #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) 110 #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) 111 #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) 112 #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) 113 #define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) 114 #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) 115 #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) 116 #define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) 117 #define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 118 #define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) 119 #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) 120 #define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) 121 #define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) 122 #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) 123 #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) 124 #define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) 125 #define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) 126 #define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) 127 #define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) 128 #define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) 129 #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) 130 #define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) 131 #define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) 132 #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) 133 134 #define TZIC_BASE_ADDR 0x8FFFC000 135 136 /* 137 * Memory regions and CS 138 */ 139 #define CSD0_BASE_ADDR 0x90000000 140 #define CSD1_BASE_ADDR 0xA0000000 141 #define CS0_BASE_ADDR 0xB0000000 142 #define CS1_BASE_ADDR 0xB8000000 143 #define CS2_BASE_ADDR 0xC0000000 144 #define CS3_BASE_ADDR 0xC8000000 145 #define CS4_BASE_ADDR 0xCC000000 146 #define CS5_BASE_ADDR 0xCE000000 147 148 /* 149 * NFC 150 */ 151 #define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ 152 153 /*! 154 * Number of GPIO port as defined in the IC Spec 155 */ 156 #define GPIO_PORT_NUM 4 157 /*! 158 * Number of GPIO pins per port 159 */ 160 #define GPIO_NUM_PIN 32 161 162 #define IIM_SREV 0x24 163 #define ROM_SI_REV 0x48 164 165 #define NFC_BUF_SIZE 0x1000 166 167 /* M4IF */ 168 #define M4IF_FBPM0 0x40 169 #define M4IF_FIDBP 0x48 170 171 /* Assuming 24MHz input clock with doubler ON */ 172 /* MFI PDF */ 173 #define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) 174 #define DP_MFD_850 (48 - 1) 175 #define DP_MFN_850 41 176 177 #define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) 178 #define DP_MFD_800 (3 - 1) 179 #define DP_MFN_800 1 180 181 #define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) 182 #define DP_MFD_700 (24 - 1) 183 #define DP_MFN_700 7 184 185 #define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) 186 #define DP_MFD_665 (96 - 1) 187 #define DP_MFN_665 89 188 189 #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) 190 #define DP_MFD_532 (24 - 1) 191 #define DP_MFN_532 13 192 193 #define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) 194 #define DP_MFD_400 (3 - 1) 195 #define DP_MFN_400 1 196 197 #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) 198 #define DP_MFD_216 (4 - 1) 199 #define DP_MFN_216 3 200 201 #define CHIP_REV_1_0 0x10 202 #define CHIP_REV_1_1 0x11 203 #define CHIP_REV_2_0 0x20 204 #define CHIP_REV_2_5 0x25 205 #define CHIP_REV_3_0 0x30 206 207 #define BOARD_REV_1_0 0x0 208 #define BOARD_REV_2_0 0x1 209 210 #ifndef __ASSEMBLY__ 211 212 struct clkctl { 213 u32 ccr; 214 u32 ccdr; 215 u32 csr; 216 u32 ccsr; 217 u32 cacrr; 218 u32 cbcdr; 219 u32 cbcmr; 220 u32 cscmr1; 221 u32 cscmr2; 222 u32 cscdr1; 223 u32 cs1cdr; 224 u32 cs2cdr; 225 u32 cdcdr; 226 u32 chsccdr; 227 u32 cscdr2; 228 u32 cscdr3; 229 u32 cscdr4; 230 u32 cwdr; 231 u32 cdhipr; 232 u32 cdcr; 233 u32 ctor; 234 u32 clpcr; 235 u32 cisr; 236 u32 cimr; 237 u32 ccosr; 238 u32 cgpr; 239 u32 ccgr0; 240 u32 ccgr1; 241 u32 ccgr2; 242 u32 ccgr3; 243 u32 ccgr4; 244 u32 ccgr5; 245 u32 ccgr6; 246 u32 cmeor; 247 }; 248 249 /* WEIM registers */ 250 struct weim { 251 u32 csgcr1; 252 u32 csgcr2; 253 u32 csrcr1; 254 u32 csrcr2; 255 u32 cswcr1; 256 u32 cswcr2; 257 }; 258 259 #endif /* __ASSEMBLER__*/ 260 261 #endif /* __ASM_ARCH_MXC_MX51_H__ */ 262