1 /*
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * PCI Configuration space access support
26 */
27 #include <common.h>
28 #include <pci.h>
29 #include <asm/io.h>
30 #include <asm/immap.h>
31
32 #if defined(CONFIG_PCI)
33 /* System RAM mapped over PCI */
34 #define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
35 #define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
36 #define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
37
38 #define cfg_read(val, addr, type, op) *val = op((type)(addr));
39 #define cfg_write(val, addr, type, op) op((type *)(addr), (val));
40
41 #define PCI_OP(rw, size, type, op, mask) \
42 int pci_##rw##_cfg_##size(struct pci_controller *hose, \
43 pci_dev_t dev, int offset, type val) \
44 { \
45 u32 addr = 0; \
46 u16 cfg_type = 0; \
47 addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
48 out_be32(hose->cfg_addr, addr); \
49 cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
50 out_be32(hose->cfg_addr, addr & 0x7fffffff); \
51 return 0; \
52 }
53
54 PCI_OP(read, byte, u8 *, in_8, 3)
55 PCI_OP(read, word, u16 *, in_le16, 2)
56 PCI_OP(read, dword, u32 *, in_le32, 0)
57 PCI_OP(write, byte, u8, out_8, 3)
58 PCI_OP(write, word, u16, out_le16, 2)
59 PCI_OP(write, dword, u32, out_le32, 0)
60
pci_mcf5445x_init(struct pci_controller * hose)61 void pci_mcf5445x_init(struct pci_controller *hose)
62 {
63 volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
64 volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
65 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
66 u32 barEn = 0;
67
68 pciarb->acr = 0x001F001F;
69
70 /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
71 PCIREQ2, PCIGNT2 */
72 gpio->par_pci =
73 GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
74 GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
75 GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
76
77 /* Assert reset bit */
78 pci->gscr |= PCI_GSCR_PR;
79
80 pci->tcr1 |= PCI_TCR1_P;
81
82 /* Initiator windows */
83 pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
84 pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
85 pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
86
87 pci->iwcr =
88 PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
89 PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
90
91 pci->icr = 0;
92
93 /* Enable bus master and mem access */
94 pci->scr = PCI_SCR_B | PCI_SCR_M;
95
96 /* Cache line size and master latency */
97 pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
98 pci->cr2 = 0;
99
100 #ifdef CONFIG_SYS_PCI_BAR0
101 pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
102 pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
103 barEn |= PCI_TCR2_B0E;
104 #endif
105 #ifdef CONFIG_SYS_PCI_BAR1
106 pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
107 pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
108 barEn |= PCI_TCR2_B1E;
109 #endif
110 #ifdef CONFIG_SYS_PCI_BAR2
111 pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
112 pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
113 barEn |= PCI_TCR2_B2E;
114 #endif
115 #ifdef CONFIG_SYS_PCI_BAR3
116 pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
117 pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
118 barEn |= PCI_TCR2_B3E;
119 #endif
120 #ifdef CONFIG_SYS_PCI_BAR4
121 pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
122 pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
123 barEn |= PCI_TCR2_B4E;
124 #endif
125 #ifdef CONFIG_SYS_PCI_BAR5
126 pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
127 pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
128 barEn |= PCI_TCR2_B5E;
129 #endif
130
131 pci->tcr2 = barEn;
132
133 /* Deassert reset bit */
134 pci->gscr &= ~PCI_GSCR_PR;
135 udelay(1000);
136
137 /* Enable PCI bus master support */
138 hose->first_busno = 0;
139 hose->last_busno = 0xff;
140
141 pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
142 CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
143
144 pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
145 CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
146
147 pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
148 CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
149 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
150
151 hose->region_count = 3;
152
153 hose->cfg_addr = &(pci->car);
154 hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
155
156 pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
157 pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
158 pci_write_cfg_dword);
159
160 /* Hose scan */
161 pci_register_hose(hose);
162 hose->last_busno = pci_hose_scan(hose);
163 }
164 #endif /* CONFIG_PCI */
165