1 2 /* 3 * MPC8260 Communication Processor Module. 4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) 5 * 6 * This file contains structures and information for the communication 7 * processor channels found in the dual port RAM or parameter RAM. 8 * All CPM control and status is available through the MPC8260 internal 9 * memory map. See immap.h for details. 10 */ 11 #ifndef __CPM_82XX__ 12 #define __CPM_82XX__ 13 14 #include <asm/immap_8260.h> 15 16 /* CPM Command register. 17 */ 18 #define CPM_CR_RST ((uint)0x80000000) 19 #define CPM_CR_PAGE ((uint)0x7c000000) 20 #define CPM_CR_SBLOCK ((uint)0x03e00000) 21 #define CPM_CR_FLG ((uint)0x00010000) 22 #define CPM_CR_MCN ((uint)0x00003fc0) 23 #define CPM_CR_OPCODE ((uint)0x0000000f) 24 25 /* Device sub-block and page codes. 26 */ 27 #define CPM_CR_SCC1_SBLOCK (0x04) 28 #define CPM_CR_SCC2_SBLOCK (0x05) 29 #define CPM_CR_SCC3_SBLOCK (0x06) 30 #define CPM_CR_SCC4_SBLOCK (0x07) 31 #define CPM_CR_SMC1_SBLOCK (0x08) 32 #define CPM_CR_SMC2_SBLOCK (0x09) 33 #define CPM_CR_SPI_SBLOCK (0x0a) 34 #define CPM_CR_I2C_SBLOCK (0x0b) 35 #define CPM_CR_TIMER_SBLOCK (0x0f) 36 #define CPM_CR_RAND_SBLOCK (0x0e) 37 #define CPM_CR_FCC1_SBLOCK (0x10) 38 #define CPM_CR_FCC2_SBLOCK (0x11) 39 #define CPM_CR_FCC3_SBLOCK (0x12) 40 #define CPM_CR_IDMA1_SBLOCK (0x14) 41 #define CPM_CR_IDMA2_SBLOCK (0x15) 42 #define CPM_CR_IDMA3_SBLOCK (0x16) 43 #define CPM_CR_IDMA4_SBLOCK (0x17) 44 #define CPM_CR_MCC1_SBLOCK (0x1c) 45 46 #define CPM_CR_SCC1_PAGE (0x00) 47 #define CPM_CR_SCC2_PAGE (0x01) 48 #define CPM_CR_SCC3_PAGE (0x02) 49 #define CPM_CR_SCC4_PAGE (0x03) 50 #define CPM_CR_SMC1_PAGE (0x07) 51 #define CPM_CR_SMC2_PAGE (0x08) 52 #define CPM_CR_SPI_PAGE (0x09) 53 #define CPM_CR_I2C_PAGE (0x0a) 54 #define CPM_CR_TIMER_PAGE (0x0a) 55 #define CPM_CR_RAND_PAGE (0x0a) 56 #define CPM_CR_FCC1_PAGE (0x04) 57 #define CPM_CR_FCC2_PAGE (0x05) 58 #define CPM_CR_FCC3_PAGE (0x06) 59 #define CPM_CR_IDMA1_PAGE (0x07) 60 #define CPM_CR_IDMA2_PAGE (0x08) 61 #define CPM_CR_IDMA3_PAGE (0x09) 62 #define CPM_CR_IDMA4_PAGE (0x0a) 63 #define CPM_CR_MCC1_PAGE (0x07) 64 #define CPM_CR_MCC2_PAGE (0x08) 65 66 /* Some opcodes (there are more...later) 67 */ 68 #define CPM_CR_INIT_TRX ((ushort)0x0000) 69 #define CPM_CR_INIT_RX ((ushort)0x0001) 70 #define CPM_CR_INIT_TX ((ushort)0x0002) 71 #define CPM_CR_HUNT_MODE ((ushort)0x0003) 72 #define CPM_CR_STOP_TX ((ushort)0x0004) 73 #define CPM_CR_RESTART_TX ((ushort)0x0006) 74 #define CPM_CR_SET_GADDR ((ushort)0x0008) 75 76 #define mk_cr_cmd(PG, SBC, MCN, OP) \ 77 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) 78 79 /* Dual Port RAM addresses. The first 16K is available for almost 80 * any CPM use, so we put the BDs there. The first 128 bytes are 81 * used for SMC1 and SMC2 parameter RAM, so we start allocating 82 * BDs above that. All of this must change when we start 83 * downloading RAM microcode. 84 */ 85 #define CPM_DATAONLY_BASE ((uint)128) 86 #define CPM_DP_NOSPACE ((uint)0x7fffffff) 87 #ifndef CONFIG_MPC8272_FAMILY 88 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE) 89 #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000) 90 #else /* 8247/48/71/72 */ 91 #define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE) 92 #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000) 93 #endif /* !CONFIG_MPC8272_FAMILY */ 94 95 /* The number of pages of host memory we allocate for CPM. This is 96 * done early in kernel initialization to get physically contiguous 97 * pages. 98 */ 99 #define NUM_CPM_HOST_PAGES 2 100 101 102 /* Export the base address of the communication processor registers 103 * and dual port ram. 104 */ 105 extern cpm8260_t *cpmp; /* Pointer to comm processor */ 106 uint m8260_cpm_dpalloc(uint size, uint align); 107 uint m8260_cpm_hostalloc(uint size, uint align); 108 void m8260_cpm_setbrg(uint brg, uint rate); 109 void m8260_cpm_fastbrg(uint brg, uint rate, int div16); 110 void m8260_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel); 111 112 /* Buffer descriptors used by many of the CPM protocols. 113 */ 114 typedef struct cpm_buf_desc { 115 ushort cbd_sc; /* Status and Control */ 116 ushort cbd_datlen; /* Data length in buffer */ 117 uint cbd_bufaddr; /* Buffer address in host memory */ 118 } cbd_t; 119 120 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 121 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 122 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 123 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 124 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 125 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 126 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 127 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 128 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 129 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 130 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 131 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 132 #define BD_SC_CD ((ushort)0x0001) /* ?? */ 133 134 /* Function code bits, usually generic to devices. 135 */ 136 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */ 137 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */ 138 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */ 139 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */ 140 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */ 141 142 /* Parameter RAM offsets from the base. 143 */ 144 #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR 145 #define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */ 146 #else 147 #define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR 148 #endif 149 150 #ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR 151 #define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) 152 #else 153 #define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR 154 #endif 155 156 #define PROFF_SCC1 ((uint)0x8000) 157 #define PROFF_SCC2 ((uint)0x8100) 158 #define PROFF_SCC3 ((uint)0x8200) 159 #define PROFF_SCC4 ((uint)0x8300) 160 #define PROFF_FCC1 ((uint)0x8400) 161 #define PROFF_FCC2 ((uint)0x8500) 162 #define PROFF_FCC3 ((uint)0x8600) 163 #define PROFF_MCC1 ((uint)0x8700) 164 #define PROFF_SMC1_BASE ((uint)0x87fc) 165 #define PROFF_IDMA1_BASE ((uint)0x87fe) 166 #define PROFF_MCC2 ((uint)0x8800) 167 #define PROFF_SMC2_BASE ((uint)0x88fc) 168 #define PROFF_IDMA2_BASE ((uint)0x88fe) 169 #define PROFF_SPI_BASE ((uint)0x89fc) 170 #define PROFF_IDMA3_BASE ((uint)0x89fe) 171 #define PROFF_TIMERS ((uint)0x8ae0) 172 #define PROFF_REVNUM ((uint)0x8af0) 173 #define PROFF_RAND ((uint)0x8af8) 174 #define PROFF_I2C_BASE ((uint)0x8afc) 175 #define PROFF_IDMA4_BASE ((uint)0x8afe) 176 177 /* The SMCs are relocated to any of the first eight DPRAM pages. 178 * We will fix these at the first locations of DPRAM, until we 179 * get some microcode patches :-). 180 * The parameter ram space for the SMCs is fifty-some bytes, and 181 * they are required to start on a 64 byte boundary. 182 */ 183 #define PROFF_SMC1 (0) 184 #define PROFF_SMC2 (64) 185 #define PROFF_SPI ((16*1024) - 128) 186 187 /* Define enough so I can at least use the serial port as a UART. 188 */ 189 typedef struct smc_uart { 190 ushort smc_rbase; /* Rx Buffer descriptor base address */ 191 ushort smc_tbase; /* Tx Buffer descriptor base address */ 192 u_char smc_rfcr; /* Rx function code */ 193 u_char smc_tfcr; /* Tx function code */ 194 ushort smc_mrblr; /* Max receive buffer length */ 195 uint smc_rstate; /* Internal */ 196 uint smc_idp; /* Internal */ 197 ushort smc_rbptr; /* Internal */ 198 ushort smc_ibc; /* Internal */ 199 uint smc_rxtmp; /* Internal */ 200 uint smc_tstate; /* Internal */ 201 uint smc_tdp; /* Internal */ 202 ushort smc_tbptr; /* Internal */ 203 ushort smc_tbc; /* Internal */ 204 uint smc_txtmp; /* Internal */ 205 ushort smc_maxidl; /* Maximum idle characters */ 206 ushort smc_tmpidl; /* Temporary idle counter */ 207 ushort smc_brklen; /* Last received break length */ 208 ushort smc_brkec; /* rcv'd break condition counter */ 209 ushort smc_brkcr; /* xmt break count register */ 210 ushort smc_rmask; /* Temporary bit mask */ 211 uint smc_stmp; /* SDMA Temp */ 212 } smc_uart_t; 213 214 /* SMC uart mode register (Internal memory map). 215 */ 216 #define SMCMR_REN ((ushort)0x0001) 217 #define SMCMR_TEN ((ushort)0x0002) 218 #define SMCMR_DM ((ushort)0x000c) 219 #define SMCMR_SM_GCI ((ushort)0x0000) 220 #define SMCMR_SM_UART ((ushort)0x0020) 221 #define SMCMR_SM_TRANS ((ushort)0x0030) 222 #define SMCMR_SM_MASK ((ushort)0x0030) 223 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 224 #define SMCMR_REVD SMCMR_PM_EVEN 225 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 226 #define SMCMR_BS SMCMR_PEN 227 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 228 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 229 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 230 231 /* SMC Event and Mask register. 232 */ 233 #define SMCM_TXE ((unsigned char)0x10) 234 #define SMCM_BSY ((unsigned char)0x04) 235 #define SMCM_TX ((unsigned char)0x02) 236 #define SMCM_RX ((unsigned char)0x01) 237 238 /* Baud rate generators. 239 */ 240 #define CPM_BRG_RST ((uint)0x00020000) 241 #define CPM_BRG_EN ((uint)0x00010000) 242 #define CPM_BRG_EXTC_INT ((uint)0x00000000) 243 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) 244 #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) 245 #define CPM_BRG_ATB ((uint)0x00002000) 246 #define CPM_BRG_CD_MASK ((uint)0x00001ffe) 247 #define CPM_BRG_DIV16 ((uint)0x00000001) 248 249 /* SCCs. 250 */ 251 #define SCC_GSMRH_IRP ((uint)0x00040000) 252 #define SCC_GSMRH_GDE ((uint)0x00010000) 253 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 254 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 255 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 256 #define SCC_GSMRH_REVD ((uint)0x00002000) 257 #define SCC_GSMRH_TRX ((uint)0x00001000) 258 #define SCC_GSMRH_TTX ((uint)0x00000800) 259 #define SCC_GSMRH_CDP ((uint)0x00000400) 260 #define SCC_GSMRH_CTSP ((uint)0x00000200) 261 #define SCC_GSMRH_CDS ((uint)0x00000100) 262 #define SCC_GSMRH_CTSS ((uint)0x00000080) 263 #define SCC_GSMRH_TFL ((uint)0x00000040) 264 #define SCC_GSMRH_RFW ((uint)0x00000020) 265 #define SCC_GSMRH_TXSY ((uint)0x00000010) 266 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 267 #define SCC_GSMRH_SYNL8 ((uint)0x00000008) 268 #define SCC_GSMRH_SYNL4 ((uint)0x00000004) 269 #define SCC_GSMRH_RTSM ((uint)0x00000002) 270 #define SCC_GSMRH_RSYN ((uint)0x00000001) 271 272 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 273 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 274 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 275 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 276 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 277 #define SCC_GSMRL_TCI ((uint)0x10000000) 278 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 279 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 280 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 281 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 282 #define SCC_GSMRL_RINV ((uint)0x02000000) 283 #define SCC_GSMRL_TINV ((uint)0x01000000) 284 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 285 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 286 #define SCC_GSMRL_TPL_48 ((uint)0x00800000) 287 #define SCC_GSMRL_TPL_32 ((uint)0x00600000) 288 #define SCC_GSMRL_TPL_16 ((uint)0x00400000) 289 #define SCC_GSMRL_TPL_8 ((uint)0x00200000) 290 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 291 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 292 #define SCC_GSMRL_TPP_01 ((uint)0x00100000) 293 #define SCC_GSMRL_TPP_10 ((uint)0x00080000) 294 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 295 #define SCC_GSMRL_TEND ((uint)0x00040000) 296 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 297 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 298 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 299 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 300 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 301 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 302 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 303 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 304 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 305 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 306 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 307 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 308 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 309 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 310 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 311 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 312 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 313 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 314 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 315 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 316 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 317 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 318 #define SCC_GSMRL_ENR ((uint)0x00000020) 319 #define SCC_GSMRL_ENT ((uint)0x00000010) 320 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 321 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 322 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 323 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 324 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 325 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 326 #define SCC_GSMRL_MODE_UART ((uint)0x00000004) 327 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 328 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 329 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 330 331 #define SCC_TODR_TOD ((ushort)0x8000) 332 333 /* SCC Event and Mask register. 334 */ 335 #define SCCM_TXE ((unsigned char)0x10) 336 #define SCCM_BSY ((unsigned char)0x04) 337 #define SCCM_TX ((unsigned char)0x02) 338 #define SCCM_RX ((unsigned char)0x01) 339 340 typedef struct scc_param { 341 ushort scc_rbase; /* Rx Buffer descriptor base address */ 342 ushort scc_tbase; /* Tx Buffer descriptor base address */ 343 u_char scc_rfcr; /* Rx function code */ 344 u_char scc_tfcr; /* Tx function code */ 345 ushort scc_mrblr; /* Max receive buffer length */ 346 uint scc_rstate; /* Internal */ 347 uint scc_idp; /* Internal */ 348 ushort scc_rbptr; /* Internal */ 349 ushort scc_ibc; /* Internal */ 350 uint scc_rxtmp; /* Internal */ 351 uint scc_tstate; /* Internal */ 352 uint scc_tdp; /* Internal */ 353 ushort scc_tbptr; /* Internal */ 354 ushort scc_tbc; /* Internal */ 355 uint scc_txtmp; /* Internal */ 356 uint scc_rcrc; /* Internal */ 357 uint scc_tcrc; /* Internal */ 358 } sccp_t; 359 360 /* CPM Ethernet through SCC1. 361 */ 362 typedef struct scc_enet { 363 sccp_t sen_genscc; 364 uint sen_cpres; /* Preset CRC */ 365 uint sen_cmask; /* Constant mask for CRC */ 366 uint sen_crcec; /* CRC Error counter */ 367 uint sen_alec; /* alignment error counter */ 368 uint sen_disfc; /* discard frame counter */ 369 ushort sen_pads; /* Tx short frame pad character */ 370 ushort sen_retlim; /* Retry limit threshold */ 371 ushort sen_retcnt; /* Retry limit counter */ 372 ushort sen_maxflr; /* maximum frame length register */ 373 ushort sen_minflr; /* minimum frame length register */ 374 ushort sen_maxd1; /* maximum DMA1 length */ 375 ushort sen_maxd2; /* maximum DMA2 length */ 376 ushort sen_maxd; /* Rx max DMA */ 377 ushort sen_dmacnt; /* Rx DMA counter */ 378 ushort sen_maxb; /* Max BD byte count */ 379 ushort sen_gaddr1; /* Group address filter */ 380 ushort sen_gaddr2; 381 ushort sen_gaddr3; 382 ushort sen_gaddr4; 383 uint sen_tbuf0data0; /* Save area 0 - current frame */ 384 uint sen_tbuf0data1; /* Save area 1 - current frame */ 385 uint sen_tbuf0rba; /* Internal */ 386 uint sen_tbuf0crc; /* Internal */ 387 ushort sen_tbuf0bcnt; /* Internal */ 388 ushort sen_paddrh; /* physical address (MSB) */ 389 ushort sen_paddrm; 390 ushort sen_paddrl; /* physical address (LSB) */ 391 ushort sen_pper; /* persistence */ 392 ushort sen_rfbdptr; /* Rx first BD pointer */ 393 ushort sen_tfbdptr; /* Tx first BD pointer */ 394 ushort sen_tlbdptr; /* Tx last BD pointer */ 395 uint sen_tbuf1data0; /* Save area 0 - current frame */ 396 uint sen_tbuf1data1; /* Save area 1 - current frame */ 397 uint sen_tbuf1rba; /* Internal */ 398 uint sen_tbuf1crc; /* Internal */ 399 ushort sen_tbuf1bcnt; /* Internal */ 400 ushort sen_txlen; /* Tx Frame length counter */ 401 ushort sen_iaddr1; /* Individual address filter */ 402 ushort sen_iaddr2; 403 ushort sen_iaddr3; 404 ushort sen_iaddr4; 405 ushort sen_boffcnt; /* Backoff counter */ 406 407 /* NOTE: Some versions of the manual have the following items 408 * incorrectly documented. Below is the proper order. 409 */ 410 ushort sen_taddrh; /* temp address (MSB) */ 411 ushort sen_taddrm; 412 ushort sen_taddrl; /* temp address (LSB) */ 413 } scc_enet_t; 414 415 416 /* SCC Event register as used by Ethernet. 417 */ 418 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 419 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 420 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 421 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 422 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 423 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 424 425 /* SCC Mode Register (PSMR) as used by Ethernet. 426 */ 427 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 428 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 429 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 430 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 431 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 432 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 433 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 434 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 435 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 436 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 437 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 438 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 439 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 440 441 /* Buffer descriptor control/status used by Ethernet receive. 442 * Common to SCC and FCC. 443 */ 444 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 445 #define BD_ENET_RX_WRAP ((ushort)0x2000) 446 #define BD_ENET_RX_INTR ((ushort)0x1000) 447 #define BD_ENET_RX_LAST ((ushort)0x0800) 448 #define BD_ENET_RX_FIRST ((ushort)0x0400) 449 #define BD_ENET_RX_MISS ((ushort)0x0100) 450 #define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */ 451 #define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */ 452 #define BD_ENET_RX_LG ((ushort)0x0020) 453 #define BD_ENET_RX_NO ((ushort)0x0010) 454 #define BD_ENET_RX_SH ((ushort)0x0008) 455 #define BD_ENET_RX_CR ((ushort)0x0004) 456 #define BD_ENET_RX_OV ((ushort)0x0002) 457 #define BD_ENET_RX_CL ((ushort)0x0001) 458 #define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */ 459 460 /* Buffer descriptor control/status used by Ethernet transmit. 461 * Common to SCC and FCC. 462 */ 463 #define BD_ENET_TX_READY ((ushort)0x8000) 464 #define BD_ENET_TX_PAD ((ushort)0x4000) 465 #define BD_ENET_TX_WRAP ((ushort)0x2000) 466 #define BD_ENET_TX_INTR ((ushort)0x1000) 467 #define BD_ENET_TX_LAST ((ushort)0x0800) 468 #define BD_ENET_TX_TC ((ushort)0x0400) 469 #define BD_ENET_TX_DEF ((ushort)0x0200) 470 #define BD_ENET_TX_HB ((ushort)0x0100) 471 #define BD_ENET_TX_LC ((ushort)0x0080) 472 #define BD_ENET_TX_RL ((ushort)0x0040) 473 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 474 #define BD_ENET_TX_UN ((ushort)0x0002) 475 #define BD_ENET_TX_CSL ((ushort)0x0001) 476 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 477 478 /* SCC as UART 479 */ 480 typedef struct scc_uart { 481 sccp_t scc_genscc; 482 uint scc_res1; /* Reserved */ 483 uint scc_res2; /* Reserved */ 484 ushort scc_maxidl; /* Maximum idle chars */ 485 ushort scc_idlc; /* temp idle counter */ 486 ushort scc_brkcr; /* Break count register */ 487 ushort scc_parec; /* receive parity error counter */ 488 ushort scc_frmec; /* receive framing error counter */ 489 ushort scc_nosec; /* receive noise counter */ 490 ushort scc_brkec; /* receive break condition counter */ 491 ushort scc_brkln; /* last received break length */ 492 ushort scc_uaddr1; /* UART address character 1 */ 493 ushort scc_uaddr2; /* UART address character 2 */ 494 ushort scc_rtemp; /* Temp storage */ 495 ushort scc_toseq; /* Transmit out of sequence char */ 496 ushort scc_char1; /* control character 1 */ 497 ushort scc_char2; /* control character 2 */ 498 ushort scc_char3; /* control character 3 */ 499 ushort scc_char4; /* control character 4 */ 500 ushort scc_char5; /* control character 5 */ 501 ushort scc_char6; /* control character 6 */ 502 ushort scc_char7; /* control character 7 */ 503 ushort scc_char8; /* control character 8 */ 504 ushort scc_rccm; /* receive control character mask */ 505 ushort scc_rccr; /* receive control character register */ 506 ushort scc_rlbc; /* receive last break character */ 507 } scc_uart_t; 508 509 /* SCC Event and Mask registers when it is used as a UART. 510 */ 511 #define UART_SCCM_GLR ((ushort)0x1000) 512 #define UART_SCCM_GLT ((ushort)0x0800) 513 #define UART_SCCM_AB ((ushort)0x0200) 514 #define UART_SCCM_IDL ((ushort)0x0100) 515 #define UART_SCCM_GRA ((ushort)0x0080) 516 #define UART_SCCM_BRKE ((ushort)0x0040) 517 #define UART_SCCM_BRKS ((ushort)0x0020) 518 #define UART_SCCM_CCR ((ushort)0x0008) 519 #define UART_SCCM_BSY ((ushort)0x0004) 520 #define UART_SCCM_TX ((ushort)0x0002) 521 #define UART_SCCM_RX ((ushort)0x0001) 522 523 /* The SCC PSMR when used as a UART. 524 */ 525 #define SCU_PSMR_FLC ((ushort)0x8000) 526 #define SCU_PSMR_SL ((ushort)0x4000) 527 #define SCU_PSMR_CL ((ushort)0x3000) 528 #define SCU_PSMR_UM ((ushort)0x0c00) 529 #define SCU_PSMR_FRZ ((ushort)0x0200) 530 #define SCU_PSMR_RZS ((ushort)0x0100) 531 #define SCU_PSMR_SYN ((ushort)0x0080) 532 #define SCU_PSMR_DRT ((ushort)0x0040) 533 #define SCU_PSMR_PEN ((ushort)0x0010) 534 #define SCU_PSMR_RPM ((ushort)0x000c) 535 #define SCU_PSMR_REVP ((ushort)0x0008) 536 #define SCU_PSMR_TPM ((ushort)0x0003) 537 #define SCU_PSMR_TEVP ((ushort)0x0003) 538 539 /* CPM Transparent mode SCC. 540 */ 541 typedef struct scc_trans { 542 sccp_t st_genscc; 543 uint st_cpres; /* Preset CRC */ 544 uint st_cmask; /* Constant mask for CRC */ 545 } scc_trans_t; 546 547 #define BD_SCC_TX_LAST ((ushort)0x0800) 548 549 /* SCC as HDLC controller - taken from commproc.h 550 */ 551 typedef struct scc_hdlc { 552 sccp_t sh_genscc; 553 /* 554 * HDLC specific parameter RAM 555 */ 556 uchar res[4]; /* reserved */ 557 ulong sh_cmask; /* CRC constant */ 558 ulong sh_cpres; /* CRC preset */ 559 ushort sh_disfc; /* discarded frame counter */ 560 ushort sh_crcec; /* CRC error counter */ 561 ushort sh_abtsc; /* abort sequence counter */ 562 ushort sh_nmarc; /* nonmatching address rx cnt */ 563 ushort sh_retrc; /* frame retransmission cnt */ 564 ushort sh_mflr; /* maximum frame length reg */ 565 ushort sh_maxcnt; /* maximum length counter */ 566 ushort sh_rfthr; /* received frames threshold */ 567 ushort sh_rfcnt; /* received frames count */ 568 ushort sh_hmask; /* user defined frm addr mask */ 569 ushort sh_haddr1; /* user defined frm address 1 */ 570 ushort sh_haddr2; /* user defined frm address 2 */ 571 ushort sh_haddr3; /* user defined frm address 3 */ 572 ushort sh_haddr4; /* user defined frm address 4 */ 573 ushort tmp; /* temp */ 574 ushort tmp_mb; /* temp */ 575 } scc_hdlc_t; 576 577 /* How about some FCCs..... 578 */ 579 #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 580 #define FCC_GFMR_DIAG_LE ((uint)0x40000000) 581 #define FCC_GFMR_DIAG_AE ((uint)0x80000000) 582 #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) 583 #define FCC_GFMR_TCI ((uint)0x20000000) 584 #define FCC_GFMR_TRX ((uint)0x10000000) 585 #define FCC_GFMR_TTX ((uint)0x08000000) 586 #define FCC_GFMR_TTX ((uint)0x08000000) 587 #define FCC_GFMR_CDP ((uint)0x04000000) 588 #define FCC_GFMR_CTSP ((uint)0x02000000) 589 #define FCC_GFMR_CDS ((uint)0x01000000) 590 #define FCC_GFMR_CTSS ((uint)0x00800000) 591 #define FCC_GFMR_SYNL_NONE ((uint)0x00000000) 592 #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) 593 #define FCC_GFMR_SYNL_8 ((uint)0x00008000) 594 #define FCC_GFMR_SYNL_16 ((uint)0x0000c000) 595 #define FCC_GFMR_RTSM ((uint)0x00002000) 596 #define FCC_GFMR_RENC_NRZ ((uint)0x00000000) 597 #define FCC_GFMR_RENC_NRZI ((uint)0x00000800) 598 #define FCC_GFMR_REVD ((uint)0x00000400) 599 #define FCC_GFMR_TENC_NRZ ((uint)0x00000000) 600 #define FCC_GFMR_TENC_NRZI ((uint)0x00000100) 601 #define FCC_GFMR_TCRC_16 ((uint)0x00000000) 602 #define FCC_GFMR_TCRC_32 ((uint)0x00000080) 603 #define FCC_GFMR_ENR ((uint)0x00000020) 604 #define FCC_GFMR_ENT ((uint)0x00000010) 605 #define FCC_GFMR_MODE_ENET ((uint)0x0000000c) 606 #define FCC_GFMR_MODE_ATM ((uint)0x0000000a) 607 #define FCC_GFMR_MODE_HDLC ((uint)0x00000000) 608 609 /* Generic FCC parameter ram. 610 */ 611 typedef struct fcc_param { 612 ushort fcc_riptr; /* Rx Internal temp pointer */ 613 ushort fcc_tiptr; /* Tx Internal temp pointer */ 614 ushort fcc_res1; 615 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ 616 uint fcc_rstate; /* Upper byte is Func code, must be set */ 617 uint fcc_rbase; /* Receive BD base */ 618 ushort fcc_rbdstat; /* RxBD status */ 619 ushort fcc_rbdlen; /* RxBD down counter */ 620 uint fcc_rdptr; /* RxBD internal data pointer */ 621 uint fcc_tstate; /* Upper byte is Func code, must be set */ 622 uint fcc_tbase; /* Transmit BD base */ 623 ushort fcc_tbdstat; /* TxBD status */ 624 ushort fcc_tbdlen; /* TxBD down counter */ 625 uint fcc_tdptr; /* TxBD internal data pointer */ 626 uint fcc_rbptr; /* Rx BD Internal buf pointer */ 627 uint fcc_tbptr; /* Tx BD Internal buf pointer */ 628 uint fcc_rcrc; /* Rx temp CRC */ 629 uint fcc_res2; 630 uint fcc_tcrc; /* Tx temp CRC */ 631 } fccp_t; 632 633 634 /* Ethernet controller through FCC. 635 */ 636 typedef struct fcc_enet { 637 fccp_t fen_genfcc; 638 uint fen_statbuf; /* Internal status buffer */ 639 uint fen_camptr; /* CAM address */ 640 uint fen_cmask; /* Constant mask for CRC */ 641 uint fen_cpres; /* Preset CRC */ 642 uint fen_crcec; /* CRC Error counter */ 643 uint fen_alec; /* alignment error counter */ 644 uint fen_disfc; /* discard frame counter */ 645 ushort fen_retlim; /* Retry limit */ 646 ushort fen_retcnt; /* Retry counter */ 647 ushort fen_pper; /* Persistence */ 648 ushort fen_boffcnt; /* backoff counter */ 649 uint fen_gaddrh; /* Group address filter, high 32-bits */ 650 uint fen_gaddrl; /* Group address filter, low 32-bits */ 651 ushort fen_tfcstat; /* out of sequence TxBD */ 652 ushort fen_tfclen; 653 uint fen_tfcptr; 654 ushort fen_mflr; /* Maximum frame length (1518) */ 655 ushort fen_paddrh; /* MAC address */ 656 ushort fen_paddrm; 657 ushort fen_paddrl; 658 ushort fen_ibdcount; /* Internal BD counter */ 659 ushort fen_idbstart; /* Internal BD start pointer */ 660 ushort fen_ibdend; /* Internal BD end pointer */ 661 ushort fen_txlen; /* Internal Tx frame length counter */ 662 uint fen_ibdbase[8]; /* Internal use */ 663 uint fen_iaddrh; /* Individual address filter */ 664 uint fen_iaddrl; 665 ushort fen_minflr; /* Minimum frame length (64) */ 666 ushort fen_taddrh; /* Filter transfer MAC address */ 667 ushort fen_taddrm; 668 ushort fen_taddrl; 669 ushort fen_padptr; /* Pointer to pad byte buffer */ 670 ushort fen_cftype; /* control frame type */ 671 ushort fen_cfrange; /* control frame range */ 672 ushort fen_maxb; /* maximum BD count */ 673 ushort fen_maxd1; /* Max DMA1 length (1520) */ 674 ushort fen_maxd2; /* Max DMA2 length (1520) */ 675 ushort fen_maxd; /* internal max DMA count */ 676 ushort fen_dmacnt; /* internal DMA counter */ 677 uint fen_octc; /* Total octect counter */ 678 uint fen_colc; /* Total collision counter */ 679 uint fen_broc; /* Total broadcast packet counter */ 680 uint fen_mulc; /* Total multicast packet count */ 681 uint fen_uspc; /* Total packets < 64 bytes */ 682 uint fen_frgc; /* Total packets < 64 bytes with errors */ 683 uint fen_ospc; /* Total packets > 1518 */ 684 uint fen_jbrc; /* Total packets > 1518 with errors */ 685 uint fen_p64c; /* Total packets == 64 bytes */ 686 uint fen_p65c; /* Total packets 64 < bytes <= 127 */ 687 uint fen_p128c; /* Total packets 127 < bytes <= 255 */ 688 uint fen_p256c; /* Total packets 256 < bytes <= 511 */ 689 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ 690 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ 691 uint fen_cambuf; /* Internal CAM buffer poiner */ 692 ushort fen_rfthr; /* Received frames threshold */ 693 ushort fen_rfcnt; /* Received frames count */ 694 } fcc_enet_t; 695 696 /* FCC Event/Mask register as used by Ethernet. 697 */ 698 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 699 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ 700 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ 701 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 702 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ 703 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ 704 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 705 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 706 707 /* FCC Mode Register (FPSMR) as used by Ethernet. 708 */ 709 #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ 710 #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ 711 #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ 712 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ 713 #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ 714 #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ 715 #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ 716 #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ 717 #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ 718 #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ 719 #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ 720 #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ 721 #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ 722 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ 723 724 /* IIC parameter RAM. 725 */ 726 typedef struct iic { 727 ushort iic_rbase; /* Rx Buffer descriptor base address */ 728 ushort iic_tbase; /* Tx Buffer descriptor base address */ 729 u_char iic_rfcr; /* Rx function code */ 730 u_char iic_tfcr; /* Tx function code */ 731 ushort iic_mrblr; /* Max receive buffer length */ 732 uint iic_rstate; /* Internal */ 733 uint iic_rdp; /* Internal */ 734 ushort iic_rbptr; /* Internal */ 735 ushort iic_rbc; /* Internal */ 736 uint iic_rxtmp; /* Internal */ 737 uint iic_tstate; /* Internal */ 738 uint iic_tdp; /* Internal */ 739 ushort iic_tbptr; /* Internal */ 740 ushort iic_tbc; /* Internal */ 741 uint iic_txtmp; /* Internal */ 742 } iic_t; 743 744 /* SPI parameter RAM. 745 */ 746 typedef struct spi { 747 ushort spi_rbase; /* Rx Buffer descriptor base address */ 748 ushort spi_tbase; /* Tx Buffer descriptor base address */ 749 u_char spi_rfcr; /* Rx function code */ 750 u_char spi_tfcr; /* Tx function code */ 751 ushort spi_mrblr; /* Max receive buffer length */ 752 uint spi_rstate; /* Internal */ 753 uint spi_rdp; /* Internal */ 754 ushort spi_rbptr; /* Internal */ 755 ushort spi_rbc; /* Internal */ 756 uint spi_rxtmp; /* Internal */ 757 uint spi_tstate; /* Internal */ 758 uint spi_tdp; /* Internal */ 759 ushort spi_tbptr; /* Internal */ 760 ushort spi_tbc; /* Internal */ 761 uint spi_txtmp; /* Internal */ 762 uint spi_res; /* Tx temp. */ 763 uint spi_res1[4]; /* SDMA temp. */ 764 } spi_t; 765 766 /* SPI Mode register. 767 */ 768 #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 769 #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 770 #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 771 #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 772 #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 773 #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 774 #define SPMODE_EN ((ushort)0x0100) /* Enable */ 775 #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 776 #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 777 778 #define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 779 #define SPMODE_PM(x) ((x) &0xF) 780 781 /* SPI Event/Mask register. 782 */ 783 #define SPI_EMASK 0x37 /* Event Mask */ 784 #define SPI_MME 0x20 /* Multi-Master Error */ 785 #define SPI_TXE 0x10 /* Transmit Error */ 786 #define SPI_BSY 0x04 /* Busy */ 787 #define SPI_TXB 0x02 /* Tx Buffer Empty */ 788 #define SPI_RXB 0x01 /* RX Buffer full/closed */ 789 790 #define SPI_STR 0x80 /* SPCOM: Start transmit */ 791 792 #define SPI_EB ((u_char)0x10) /* big endian byte order */ 793 794 #define BD_IIC_START ((ushort)0x0400) 795 796 #endif /* __CPM_82XX__ */ 797