1 /* 2 * A collection of structures, addresses, and values associated with 3 * the Motorola 860T FADS board. Copied from the MBX stuff. 4 * Magnus Damm added defines for 8xxrom and extended bd_info. 5 * Helmut Buchsbaum added bitvalues for BCSRx 6 * 7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) 8 */ 9 10 /* 11 * The GENIETV is using the following physical memorymap (copied from 12 * the FADS configuration): 13 * 14 * ff020000 -> ff02ffff : pcmcia 15 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM 16 * ff000000 -> ff00ffff : IMAP internal in the cpu 17 * 30000000 -> 300fffff : flash connected to CS0 18 * 00000000 -> nnnnnnnn : sdram setup by U-Boot 19 * 20 * CS pins are connected as follows: 21 * 22 * CS0 -512Kb boot flash 23 * CS1 - SDRAM #1 24 * CS2 - SDRAM #2 25 * CS3 - Flash #1 26 * CS4 - Flash #2 27 * CS5 - Lon (if present) 28 * CS6 - PCMCIA #1 29 * CS7 - PCMCIA #2 30 */ 31 32 /* ------------------------------------------------------------------------- */ 33 34 /* 35 * board/config.h - configuration options, board specific 36 */ 37 38 #ifndef __CONFIG_H 39 #define __CONFIG_H 40 41 #define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */ 42 #define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */ 43 44 #define CONFIG_SYS_ALLOC_DPRAM /* Use dynamic DPRAM allocation */ 45 46 #define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ 47 48 /*#define CONFIG_VIDEO 1 / To enable the video initialization */ 49 /*#define CONFIG_VIDEO_ADDR 0x00200000 */ 50 /*#define CONFIG_HARD_I2C 1 / I2C with hardware support */ 51 /*#define CONFIG_PCMCIA 1 / To enable the PCMCIA initialization */ 52 53 /*#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000 */ 54 /*#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000 */ 55 /*#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000 */ 56 /*#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000 */ 57 58 /* Video related */ 59 60 /*#define CONFIG_VIDEO_LOGO 1 / Show the logo */ 61 /*#define CONFIG_VIDEO_ENCODER_AD7177 1 / Enable this encoder */ 62 /*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR 0xF4 / ALSB to ground */ 63 64 /* Wireless 56Khz 4PPM keyboard on SMCx */ 65 66 /*#define CONFIG_KEYBOARD 0 */ 67 /*#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 / SMC to use (0 indexed) */ 68 69 /* 70 * High Level Configuration Options 71 * (easy to change) 72 */ 73 #include <mpc8xx_irq.h> 74 75 #define CONFIG_GENIETV 1 76 #define CONFIG_MPC823 1 77 78 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 79 #undef CONFIG_8xx_CONS_SMC2 80 #undef CONFIG_8xx_CONS_NONE 81 #define CONFIG_BAUDRATE 9600 82 83 #define MPC8XX_FACT 12 /* Multiply by 12 */ 84 #define MPC8XX_XIN 5000000 /* 4 MHz clock */ 85 86 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) 87 #define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20) 88 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ 89 90 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 91 92 #if 1 93 #define CONFIG_BOOTDELAY 1 /* autoboot after 2 seconds */ 94 #define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ 95 #define CONFIG_BOOTARGS "" 96 #define CONFIG_BOOTCOMMAND \ 97 "bootp; tftp; " \ 98 "setenv bootargs console=tty0 console=ttyS0 " \ 99 "root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ 100 "ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ 101 "bootm " 102 #else 103 #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ 104 #endif 105 106 #undef CONFIG_WATCHDOG /* watchdog disabled */ 107 108 109 /* 110 * BOOTP options 111 */ 112 #define CONFIG_BOOTP_BOOTFILESIZE 113 #define CONFIG_BOOTP_BOOTPATH 114 #define CONFIG_BOOTP_GATEWAY 115 #define CONFIG_BOOTP_HOSTNAME 116 117 118 /* 119 * Command line configuration. 120 */ 121 #include <config_cmd_default.h> 122 123 124 /* 125 * Miscellaneous configurable options 126 */ 127 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 128 #define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */ 129 #if defined(CONFIG_CMD_KGDB) 130 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 131 #else 132 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 133 #endif 134 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 135 #define CONFIG_SYS_MAXARGS 8 /* max number of command args */ 136 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 137 138 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 139 #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 0 ... 8 MB in DRAM */ 140 141 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ 142 143 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 144 145 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } 146 147 /* 148 * Low Level Configuration Settings 149 * (address mappings, register initial values, etc.) 150 * You should know what you are doing if you make changes here. 151 */ 152 /*----------------------------------------------------------------------- 153 * Internal Memory Mapped Register 154 */ 155 #define CONFIG_SYS_IMMR 0xFF000000 156 #define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) 157 158 /*----------------------------------------------------------------------- 159 * Definitions for initial stack pointer and data area (in DPRAM) 160 */ 161 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 162 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 163 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 164 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 165 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 166 167 /*----------------------------------------------------------------------- 168 * Start addresses for the final memory configuration 169 * (Set up by the startup code) 170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 171 * Also NOTE that it doesn't mean SDRAM - it means MEMORY. 172 */ 173 #define CONFIG_SYS_SDRAM_BASE 0x00000000 174 #define CONFIG_SYS_FLASH_BASE 0x02800000 175 #define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ 176 #if 0 177 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */ 178 #else 179 #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ 180 #endif 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 182 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ 183 184 /* 185 * For booting Linux, the board info and command line data 186 * have to be in the first 8 MB of memory, since this is 187 * the maximum mapped by the Linux kernel during initialization. 188 */ 189 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 190 /*----------------------------------------------------------------------- 191 * FLASH organization 192 */ 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ 195 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 198 199 #define CONFIG_ENV_IS_IN_FLASH 1 200 #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ 201 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ 202 203 /* values according to the manual */ 204 205 /*----------------------------------------------------------------------- 206 * Cache Configuration 207 */ 208 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 209 #if defined(CONFIG_CMD_KGDB) 210 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 211 #endif 212 213 /*----------------------------------------------------------------------- 214 * SYPCR - System Protection Control 11-9 215 * SYPCR can only be written once after reset! 216 *----------------------------------------------------------------------- 217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 218 */ 219 #if defined(CONFIG_WATCHDOG) 220 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 221 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 222 #else 223 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 224 #endif 225 226 /*----------------------------------------------------------------------- 227 * SIUMCR - SIU Module Configuration 11-6 228 *----------------------------------------------------------------------- 229 * PCMCIA config., multi-function pin tri-state 230 * 231 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 232 */ 233 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10) 234 235 /*----------------------------------------------------------------------- 236 * TBSCR - Time Base Status and Control 11-26 237 *----------------------------------------------------------------------- 238 * Clear Reference Interrupt Status, Timebase freezing enabled 239 */ 240 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) 241 242 /*----------------------------------------------------------------------- 243 * PISCR - Periodic Interrupt Status and Control 11-31 244 *----------------------------------------------------------------------- 245 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 246 */ 247 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 248 249 /*----------------------------------------------------------------------- 250 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 251 *----------------------------------------------------------------------- 252 * Reset PLL lock status sticky bit, timer expired status bit and timer * 253 * interrupt status bit - leave PLL multiplication factor unchanged ! 254 * 255 * #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 256 */ 257 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF) 258 259 /*----------------------------------------------------------------------- 260 * SCCR - System Clock and reset Control Register 15-27 261 *----------------------------------------------------------------------- 262 * Set clock output, timebase and RTC source and divider, 263 * power management and some other internal clocks 264 */ 265 #define SCCR_MASK SCCR_EBDF11 266 #define CONFIG_SYS_SCCR (SCCR_TBS | \ 267 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 268 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 269 SCCR_DFALCD00) 270 271 /*----------------------------------------------------------------------- 272 * 273 *----------------------------------------------------------------------- 274 * 275 */ 276 #define CONFIG_SYS_DER 0 277 278 /* Because of the way the 860 starts up and assigns CS0 the 279 * entire address space, we have to set the memory controller 280 * differently. Normally, you write the option register 281 * first, and then enable the chip select by writing the 282 * base register. For CS0, you must write the base register 283 * first, followed by the option register. 284 */ 285 286 /* 287 * Init Memory Controller: 288 * 289 * BR0 and OR0(FLASH) 290 */ 291 292 #define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ 293 294 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 295 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ 296 297 /* FLASH timing */ 298 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 299 OR_SCY_15_CLK | OR_TRLX ) 300 301 /*#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) */ 302 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 0xfff80ff4 */ 303 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ 304 305 /* 306 * BR1/2 and OR1/2 (SDRAM) 307 */ 308 309 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 310 311 #define SDRAM_MAX_SIZE 0x04000000 /* 64Mb bank */ 312 #define SDRAM_BASE1_PRELIM 0x00000000 /* First bank */ 313 #define SDRAM_BASE2_PRELIM 0x10000000 /* Second bank */ 314 315 /* 316 * Memory Periodic Timer Prescaler 317 */ 318 319 /* periodic timer for refresh */ 320 #define CONFIG_SYS_MBMR_PTB 0x5d /* start with divider for 100 MHz */ 321 322 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 323 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 324 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 325 /* 326 * MBMR settings for SDRAM 327 */ 328 329 /* 8 column SDRAM */ 330 #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 331 MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \ 332 | MAMR_TLFA_4X) /* 0x5d802114 */ 333 334 /* 335 * Internal Definitions 336 * 337 * Boot Flags 338 */ 339 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 340 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 341 342 /* values according to the manual */ 343 344 #define CONFIG_DRAM_50MHZ 1 345 #define CONFIG_SDRAM_50MHZ 346 347 /* We don't use the 8259. 348 */ 349 #define NR_8259_INTS 0 350 351 /* 352 * MPC8xx CPM Options 353 */ 354 #define CONFIG_SCC_ENET 1 355 356 #define CONFIG_DISK_SPINUP_TIME 1000000 357 358 /* PCMCIA configuration */ 359 360 #define PCMCIA_MAX_SLOTS 1 361 #define PCMCIA_SLOT_B 1 362 363 #endif /* __CONFIG_H */ 364