1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_E300 1 /* E300 family */ 24 #define CONFIG_QE 1 /* Has QE */ 25 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 26 #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ 27 #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ 28 29 /* 30 * System Clock Setup 31 */ 32 #ifdef CONFIG_CLKIN_33MHZ 33 #define CONFIG_83XX_CLKIN 33333333 34 #define CONFIG_SYS_CLK_FREQ 33333333 35 #define PCI_33M 1 36 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 37 #else 38 #define CONFIG_83XX_CLKIN 66000000 39 #define CONFIG_SYS_CLK_FREQ 66000000 40 #define PCI_66M 1 41 #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 42 #endif /* CONFIG_CLKIN_33MHZ */ 43 44 /* 45 * Hardware Reset Configuration Word 46 */ 47 #define CONFIG_SYS_HRCW_LOW (\ 48 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 50 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ 51 HRCWL_CORE_TO_CSB_2X1 |\ 52 HRCWL_CE_TO_PLL_1X15) 53 54 #define CONFIG_SYS_HRCW_HIGH (\ 55 HRCWH_PCI_HOST |\ 56 HRCWH_PCI1_ARBITER_ENABLE |\ 57 HRCWH_PCICKDRV_ENABLE |\ 58 HRCWH_CORE_ENABLE |\ 59 HRCWH_FROM_0X00000100 |\ 60 HRCWH_BOOTSEQ_DISABLE |\ 61 HRCWH_SW_WATCHDOG_DISABLE |\ 62 HRCWH_ROM_LOC_LOCAL_16BIT |\ 63 HRCWH_SECONDARY_DDR_DISABLE |\ 64 HRCWH_BIG_ENDIAN |\ 65 HRCWH_LALE_EARLY) 66 67 /* 68 * System IO Config 69 */ 70 #define CONFIG_SYS_SICRH 0x00000000 71 #define CONFIG_SYS_SICRL 0x40000000 72 73 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 74 #define CONFIG_BOARD_EARLY_INIT_R 75 76 /* 77 * IMMR new address 78 */ 79 #define CONFIG_SYS_IMMR 0xE0000000 80 81 /* 82 * DDR Setup 83 */ 84 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 86 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 87 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 88 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 89 90 #define CONFIG_SYS_83XX_DDR_USES_CS0 91 92 #define CONFIG_DDR_ECC /* support DDR ECC function */ 93 #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 94 95 /* 96 * DDRCDR - DDR Control Driver Register 97 */ 98 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 99 100 #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ 101 102 /* 103 * Manually set up DDR parameters 104 */ 105 #define CONFIG_DDR_II 106 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 108 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ 109 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) 110 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN) 111 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 112 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 113 #define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 114 (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) 115 #define CONFIG_SYS_DDR_MODE 0x47800432 116 #define CONFIG_SYS_DDR_MODE2 0x8000c000 117 118 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 119 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 120 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 121 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 122 (0 << TIMING_CFG0_WWT_SHIFT) | \ 123 (0 << TIMING_CFG0_RRT_SHIFT) | \ 124 (0 << TIMING_CFG0_WRT_SHIFT) | \ 125 (0 << TIMING_CFG0_RWT_SHIFT)) 126 127 #define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_30) | \ 128 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ 129 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 130 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \ 131 (10 << TIMING_CFG1_REFREC_SHIFT) | \ 132 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 133 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 134 ( 3 << TIMING_CFG1_PRETOACT_SHIFT)) 135 136 #define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 137 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 138 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 139 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 140 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 141 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 142 (0 << TIMING_CFG2_CPO_SHIFT)) 143 144 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 145 146 /* 147 * Memory test 148 */ 149 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 150 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 151 #define CONFIG_SYS_MEMTEST_END 0x00100000 152 153 /* 154 * The reserved memory 155 */ 156 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 157 #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */ 158 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 160 #define CONFIG_SYS_RAMBOOT 161 #else 162 #undef CONFIG_SYS_RAMBOOT 163 #endif 164 165 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 166 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 167 168 /* 169 * Initial RAM Base Address Setup 170 */ 171 #define CONFIG_SYS_INIT_RAM_LOCK 1 172 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 173 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 174 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 175 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 176 177 /* 178 * Local Bus Configuration & Clock Setup 179 */ 180 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 181 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 182 #define CONFIG_SYS_LBC_LBCR 0x00000000 183 184 /* 185 * FLASH on the Local Bus 186 */ 187 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 188 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 189 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 190 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ 191 192 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 193 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 194 195 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ 196 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 197 BR_V) /* valid */ 198 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 199 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 200 OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 201 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 202 203 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 204 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 205 206 #undef CONFIG_SYS_FLASH_CHECKSUM 207 208 /* 209 * NAND flash on the local bus 210 */ 211 #define CONFIG_SYS_NAND_BASE 0x60000000 212 #define CONFIG_CMD_NAND 1 213 #define CONFIG_NAND_FSL_UPM 1 214 #define CONFIG_SYS_MAX_NAND_DEVICE 1 215 #define CONFIG_MTD_NAND_VERIFY_WRITE 216 217 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 218 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ 219 220 /* Port size 8 bit, UPMA */ 221 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881) 222 #define CONFIG_SYS_OR1_PRELIM 0xfc000001 223 224 /* 225 * Fujitsu MB86277 (MINT) graphics controller 226 */ 227 #define CONFIG_SYS_VIDEO_BASE 0x70000000 228 229 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE 230 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */ 231 232 /* Port size 32 bit, UPMB */ 233 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */ 234 #define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */ 235 236 /* 237 * Serial Port 238 */ 239 #define CONFIG_CONS_INDEX 1 240 #undef CONFIG_SERIAL_SOFTWARE_FIFO 241 #define CONFIG_SYS_NS16550 242 #define CONFIG_SYS_NS16550_SERIAL 243 #define CONFIG_SYS_NS16550_REG_SIZE 1 244 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 245 246 #define CONFIG_SYS_BAUDRATE_TABLE \ 247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,} 248 249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 251 252 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 253 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 254 /* Use the HUSH parser */ 255 #define CONFIG_SYS_HUSH_PARSER 256 #ifdef CONFIG_SYS_HUSH_PARSER 257 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 258 #endif 259 260 /* Pass open firmware flat tree */ 261 #define CONFIG_OF_LIBFDT 1 262 #define CONFIG_OF_BOARD_SETUP 1 263 #define CONFIG_OF_STDOUT_VIA_ALIAS 264 265 /* I2C */ 266 #define CONFIG_HARD_I2C /* I2C with hardware support */ 267 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 268 #define CONFIG_FSL_I2C 269 #define CONFIG_I2C_MULTI_BUS 270 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 271 #define CONFIG_SYS_I2C_SLAVE 0x7F 272 #define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */ 273 #define CONFIG_SYS_I2C_OFFSET 0x3000 274 #define CONFIG_SYS_I2C2_OFFSET 0x3100 275 276 /* 277 * General PCI 278 * Addresses are mapped 1-1. 279 */ 280 #define CONFIG_PCI 281 282 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 283 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 284 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 285 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 286 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 287 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 288 #define CONFIG_SYS_PCI1_IO_BASE 0xE0300000 289 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 290 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 291 292 #ifdef CONFIG_PCI 293 294 #define CONFIG_NET_MULTI 295 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 296 297 #undef CONFIG_EEPRO100 298 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 299 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 300 301 #endif /* CONFIG_PCI */ 302 303 304 #ifndef CONFIG_NET_MULTI 305 #define CONFIG_NET_MULTI 1 306 #endif 307 308 /* 309 * QE UEC ethernet configuration 310 */ 311 #define CONFIG_UEC_ETH 312 #define CONFIG_ETHPRIME "FSL UEC0" 313 314 #define CONFIG_UEC_ETH1 /* GETH1 */ 315 316 #ifdef CONFIG_UEC_ETH1 317 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 318 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 319 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 320 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 321 #define CONFIG_SYS_UEC1_PHY_ADDR 2 322 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_RXID 323 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 324 #endif 325 326 #define CONFIG_UEC_ETH2 /* GETH2 */ 327 328 #ifdef CONFIG_UEC_ETH2 329 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 330 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 331 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 332 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 333 #define CONFIG_SYS_UEC2_PHY_ADDR 4 334 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_RXID 335 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 336 #endif 337 338 /* 339 * Environment 340 */ 341 342 #ifndef CONFIG_SYS_RAMBOOT 343 #define CONFIG_ENV_IS_IN_FLASH 1 344 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 345 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 346 #define CONFIG_ENV_SIZE 0x20000 347 #else /* CONFIG_SYS_RAMBOOT */ 348 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 349 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 351 #define CONFIG_ENV_SIZE 0x2000 352 #endif /* CONFIG_SYS_RAMBOOT */ 353 354 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 355 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 356 357 /* 358 * BOOTP options 359 */ 360 #define CONFIG_BOOTP_BOOTFILESIZE 361 #define CONFIG_BOOTP_BOOTPATH 362 #define CONFIG_BOOTP_GATEWAY 363 #define CONFIG_BOOTP_HOSTNAME 364 365 366 /* 367 * Command line configuration. 368 */ 369 #include <config_cmd_default.h> 370 371 #define CONFIG_CMD_PING 372 #define CONFIG_CMD_I2C 373 #define CONFIG_CMD_ASKENV 374 #define CONFIG_CMD_DHCP 375 376 #if defined(CONFIG_PCI) 377 #define CONFIG_CMD_PCI 378 #endif 379 380 #if defined(CONFIG_SYS_RAMBOOT) 381 #undef CONFIG_CMD_SAVEENV 382 #undef CONFIG_CMD_LOADS 383 #endif 384 385 #undef CONFIG_WATCHDOG /* watchdog disabled */ 386 387 /* 388 * Miscellaneous configurable options 389 */ 390 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 391 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 392 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 393 394 #if defined(CONFIG_CMD_KGDB) 395 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 396 #else 397 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 398 #endif 399 400 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 401 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 402 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 403 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 404 405 /* 406 * For booting Linux, the board info and command line data 407 * have to be in the first 8 MB of memory, since this is 408 * the maximum mapped by the Linux kernel during initialization. 409 */ 410 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 411 412 /* 413 * Core HID Setup 414 */ 415 #define CONFIG_SYS_HID0_INIT 0x000000000 416 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 417 HID0_ENABLE_INSTRUCTION_CACHE) 418 #define CONFIG_SYS_HID2 HID2_HBE 419 420 /* 421 * MMU Setup 422 */ 423 424 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 425 426 /* DDR: cache cacheable */ 427 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 428 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 429 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 430 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 431 432 /* IMMRBAR & PCI IO: cache-inhibit and guarded */ 433 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 434 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 435 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) 436 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 437 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 438 439 /* NAND: cache-inhibit and guarded */ 440 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ 441 BATL_GUARDEDSTORAGE) 442 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP) 443 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 444 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 445 446 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 447 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 448 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 449 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 450 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 451 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 452 453 /* Stack in dcache: cacheable, no memory coherence */ 454 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 455 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 456 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 457 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 458 459 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \ 460 BATL_GUARDEDSTORAGE) 461 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP) 462 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 463 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 464 465 #ifdef CONFIG_PCI 466 /* PCI MEM space: cacheable */ 467 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 468 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 469 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 470 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 471 /* PCI MMIO space: cache-inhibit and guarded */ 472 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ 473 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 474 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 475 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 476 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 477 #else /* CONFIG_PCI */ 478 #define CONFIG_SYS_IBAT6L (0) 479 #define CONFIG_SYS_IBAT6U (0) 480 #define CONFIG_SYS_IBAT7L (0) 481 #define CONFIG_SYS_IBAT7U (0) 482 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 483 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 484 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 485 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 486 #endif /* CONFIG_PCI */ 487 488 /* 489 * Internal Definitions 490 * 491 * Boot Flags 492 */ 493 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 494 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 495 496 #if defined(CONFIG_CMD_KGDB) 497 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 498 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 499 #endif 500 501 /* 502 * Environment Configuration 503 */ 504 #define CONFIG_ENV_OVERWRITE 505 506 #if defined(CONFIG_UEC_ETH) 507 #define CONFIG_HAS_ETH0 508 #define CONFIG_HAS_ETH1 509 #define CONFIG_HAS_ETH2 510 #define CONFIG_HAS_ETH3 511 #endif 512 513 #define CONFIG_BAUDRATE 115200 514 515 #define CONFIG_LOADADDR a00000 516 #define CONFIG_HOSTNAME mpc8360erdk 517 #define CONFIG_BOOTFILE uImage 518 519 #define CONFIG_ROOTPATH /nfsroot/ 520 521 #define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ 522 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 523 524 #define CONFIG_EXTRA_ENV_SETTINGS \ 525 "netdev=eth0\0"\ 526 "consoledev=ttyS0\0"\ 527 "loadaddr=a00000\0"\ 528 "fdtaddr=900000\0"\ 529 "fdtfile=mpc836x_rdk.dtb\0"\ 530 "fsfile=fs\0"\ 531 "ubootfile=u-boot.bin\0"\ 532 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ 533 "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ 534 "$mtdparts panic=1\0"\ 535 "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ 536 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ 537 "$gatewayip:$netmask:$hostname:$netdev:off "\ 538 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ 539 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ 540 "rootfstype=jffs2 rw\0"\ 541 "tftp_get_uboot=tftp 100000 $ubootfile\0"\ 542 "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ 543 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ 544 "tftp_get_fs=tftp c00000 $fsfile\0"\ 545 "nand_erase_kernel=nand erase 0 400000\0"\ 546 "nand_erase_dtb=nand erase 400000 20000\0"\ 547 "nand_erase_fs=nand erase 420000 3be0000\0"\ 548 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"\ 549 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"\ 550 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"\ 551 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ 552 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ 553 "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ 554 "cp.b 100000 ff800000 $filesize\0"\ 555 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ 556 "nand_write_kernel\0"\ 557 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ 558 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"\ 559 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb "\ 560 "nand_reflash_fs\0"\ 561 "boot_m=bootm $loadaddr - $fdtaddr\0"\ 562 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\ 563 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ 564 "boot_m\0"\ 565 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ 566 "boot_m\0"\ 567 "" 568 569 #define CONFIG_BOOTCOMMAND "run dhcpboot" 570 571 #endif /* __CONFIG_H */ 572