1 /* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #undef CONFIG_SYS_RAMBOOT 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 39 #define CONFIG_PM826 1 /* ...on a PM8260 module */ 40 #define CONFIG_CPM2 1 /* Has a CPM2 */ 41 42 #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ 43 44 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 45 46 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 47 48 #undef CONFIG_BOOTARGS 49 #define CONFIG_BOOTCOMMAND \ 50 "bootp; " \ 51 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 52 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 53 "bootm" 54 55 /* enable I2C and select the hardware/software driver */ 56 #undef CONFIG_HARD_I2C 57 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 58 # define CONFIG_SYS_I2C_SPEED 50000 59 # define CONFIG_SYS_I2C_SLAVE 0xFE 60 /* 61 * Software (bit-bang) I2C driver configuration 62 */ 63 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 64 #define I2C_ACTIVE (iop->pdir |= 0x00010000) 65 #define I2C_TRISTATE (iop->pdir &= ~0x00010000) 66 #define I2C_READ ((iop->pdat & 0x00010000) != 0) 67 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 68 else iop->pdat &= ~0x00010000 69 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 70 else iop->pdat &= ~0x00020000 71 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 72 73 74 #define CONFIG_RTC_PCF8563 75 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 76 77 /* 78 * select serial console configuration 79 * 80 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 81 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 82 * for SCC). 83 * 84 * if CONFIG_CONS_NONE is defined, then the serial console routines must 85 * defined elsewhere (for example, on the cogent platform, there are serial 86 * ports on the motherboard which are used for the serial console - see 87 * cogent/cma101/serial.[ch]). 88 */ 89 #define CONFIG_CONS_ON_SMC /* define if console on SMC */ 90 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 91 #undef CONFIG_CONS_NONE /* define if console on something else*/ 92 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 93 94 /* 95 * select ethernet configuration 96 * 97 * if CONFIG_ETHER_ON_SCC is selected, then 98 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) 99 * - CONFIG_NET_MULTI must not be defined 100 * 101 * if CONFIG_ETHER_ON_FCC is selected, then 102 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected 103 * - CONFIG_NET_MULTI must be defined 104 * 105 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 106 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 107 */ 108 #define CONFIG_NET_MULTI 109 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 110 111 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 112 #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ 113 114 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 115 /* 116 * - Rx-CLK is CLK11 117 * - Tx-CLK is CLK10 118 */ 119 #define CONFIG_ETHER_ON_FCC1 120 # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 121 #ifndef CONFIG_DB_CR826_J30x_ON 122 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) 123 #else 124 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) 125 #endif 126 /* 127 * - Rx-CLK is CLK15 128 * - Tx-CLK is CLK14 129 */ 130 #define CONFIG_ETHER_ON_FCC2 131 # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 132 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 133 /* 134 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 135 * - Enable Full Duplex in FSMR 136 */ 137 # define CONFIG_SYS_CPMFCR_RAMTYPE 0 138 # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 139 140 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 141 #define CONFIG_8260_CLKIN 64000000 /* in Hz */ 142 143 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 144 #define CONFIG_BAUDRATE 230400 145 #else 146 #define CONFIG_BAUDRATE 9600 147 #endif 148 149 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 150 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 151 152 #undef CONFIG_WATCHDOG /* watchdog disabled */ 153 154 /* 155 * BOOTP options 156 */ 157 #define CONFIG_BOOTP_SUBNETMASK 158 #define CONFIG_BOOTP_GATEWAY 159 #define CONFIG_BOOTP_HOSTNAME 160 #define CONFIG_BOOTP_BOOTPATH 161 #define CONFIG_BOOTP_BOOTFILESIZE 162 163 164 /* 165 * Command line configuration. 166 */ 167 #include <config_cmd_default.h> 168 169 #define CONFIG_CMD_BEDBUG 170 #define CONFIG_CMD_DATE 171 #define CONFIG_CMD_DHCP 172 #define CONFIG_CMD_EEPROM 173 #define CONFIG_CMD_I2C 174 #define CONFIG_CMD_NFS 175 #define CONFIG_CMD_SNTP 176 177 #ifdef CONFIG_PCI 178 #define CONFIG_CMD_PCI 179 #endif 180 181 /* 182 * Miscellaneous configurable options 183 */ 184 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 185 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 186 #if defined(CONFIG_CMD_KGDB) 187 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 188 #else 189 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 190 #endif 191 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 192 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 193 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 194 195 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 196 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 197 198 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 199 200 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 201 202 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 203 204 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 205 206 /* 207 * For booting Linux, the board info and command line data 208 * have to be in the first 8 MB of memory, since this is 209 * the maximum mapped by the Linux kernel during initialization. 210 */ 211 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 212 213 /*----------------------------------------------------------------------- 214 * Flash and Boot ROM mapping 215 */ 216 #ifdef CONFIG_FLASH_32MB 217 #define CONFIG_SYS_FLASH0_BASE 0x40000000 218 #define CONFIG_SYS_FLASH0_SIZE 0x02000000 219 #else 220 #define CONFIG_SYS_FLASH0_BASE 0xFF000000 221 #define CONFIG_SYS_FLASH0_SIZE 0x00800000 222 #endif 223 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000 224 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000 225 #define CONFIG_SYS_DOC_BASE 0xFF800000 226 #define CONFIG_SYS_DOC_SIZE 0x00100000 227 228 /* Flash bank size (for preliminary settings) 229 */ 230 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 231 232 /*----------------------------------------------------------------------- 233 * FLASH organization 234 */ 235 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 236 #ifdef CONFIG_FLASH_32MB 237 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ 238 #else 239 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 240 #endif 241 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 242 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 243 244 #if 0 245 /* Start port with environment in flash; switch to EEPROM later */ 246 #define CONFIG_ENV_IS_IN_FLASH 1 247 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) 248 #define CONFIG_ENV_SIZE 0x40000 249 #define CONFIG_ENV_SECT_SIZE 0x40000 250 #else 251 /* Final version: environment in EEPROM */ 252 #define CONFIG_ENV_IS_IN_EEPROM 1 253 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 254 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 257 #define CONFIG_ENV_OFFSET 512 258 #define CONFIG_ENV_SIZE (2048 - 512) 259 #endif 260 261 /*----------------------------------------------------------------------- 262 * Hard Reset Configuration Words 263 * 264 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 265 * defines for the various registers affected by the HRCW e.g. changing 266 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 267 */ 268 #if defined(CONFIG_BOOT_ROM) 269 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 270 #else 271 #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 272 #endif 273 274 /* no slaves so just fill with zeros */ 275 #define CONFIG_SYS_HRCW_SLAVE1 0 276 #define CONFIG_SYS_HRCW_SLAVE2 0 277 #define CONFIG_SYS_HRCW_SLAVE3 0 278 #define CONFIG_SYS_HRCW_SLAVE4 0 279 #define CONFIG_SYS_HRCW_SLAVE5 0 280 #define CONFIG_SYS_HRCW_SLAVE6 0 281 #define CONFIG_SYS_HRCW_SLAVE7 0 282 283 /*----------------------------------------------------------------------- 284 * Internal Memory Mapped Register 285 */ 286 #define CONFIG_SYS_IMMR 0xF0000000 287 288 /*----------------------------------------------------------------------- 289 * Definitions for initial stack pointer and data area (in DPRAM) 290 */ 291 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 292 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ 293 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ 294 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 296 297 /*----------------------------------------------------------------------- 298 * Start addresses for the final memory configuration 299 * (Set up by the startup code) 300 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 301 * 302 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM 303 * is mapped at SDRAM_BASE2_PRELIM. 304 */ 305 #define CONFIG_SYS_SDRAM_BASE 0x00000000 306 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 307 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 308 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 309 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 310 311 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 312 # define CONFIG_SYS_RAMBOOT 313 #endif 314 315 #ifdef CONFIG_PCI 316 #define CONFIG_PCI_PNP 317 #define CONFIG_EEPRO100 318 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 319 #endif 320 321 /* 322 * Internal Definitions 323 * 324 * Boot Flags 325 */ 326 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 327 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 328 329 330 /*----------------------------------------------------------------------- 331 * Cache Configuration 332 */ 333 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 334 #if defined(CONFIG_CMD_KGDB) 335 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 336 #endif 337 338 /*----------------------------------------------------------------------- 339 * HIDx - Hardware Implementation-dependent Registers 2-11 340 *----------------------------------------------------------------------- 341 * HID0 also contains cache control - initially enable both caches and 342 * invalidate contents, then the final state leaves only the instruction 343 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 344 * but Soft reset does not. 345 * 346 * HID1 has only read-only information - nothing to set. 347 */ 348 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 349 HID0_IFEM|HID0_ABE) 350 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 351 #define CONFIG_SYS_HID2 0 352 353 /*----------------------------------------------------------------------- 354 * RMR - Reset Mode Register 5-5 355 *----------------------------------------------------------------------- 356 * turn on Checkstop Reset Enable 357 */ 358 #define CONFIG_SYS_RMR RMR_CSRE 359 360 /*----------------------------------------------------------------------- 361 * BCR - Bus Configuration 4-25 362 *----------------------------------------------------------------------- 363 */ 364 365 #define BCR_APD01 0x10000000 366 #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 367 368 /*----------------------------------------------------------------------- 369 * SIUMCR - SIU Module Configuration 4-31 370 *----------------------------------------------------------------------- 371 */ 372 #if 0 373 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) 374 #else 375 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) 376 #endif 377 378 379 /*----------------------------------------------------------------------- 380 * SYPCR - System Protection Control 4-35 381 * SYPCR can only be written once after reset! 382 *----------------------------------------------------------------------- 383 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 384 */ 385 #if defined(CONFIG_WATCHDOG) 386 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 387 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 388 #else 389 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 390 SYPCR_SWRI|SYPCR_SWP) 391 #endif /* CONFIG_WATCHDOG */ 392 393 /*----------------------------------------------------------------------- 394 * TMCNTSC - Time Counter Status and Control 4-40 395 *----------------------------------------------------------------------- 396 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 397 * and enable Time Counter 398 */ 399 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 400 401 /*----------------------------------------------------------------------- 402 * PISCR - Periodic Interrupt Status and Control 4-42 403 *----------------------------------------------------------------------- 404 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 405 * Periodic timer 406 */ 407 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 408 409 /*----------------------------------------------------------------------- 410 * SCCR - System Clock Control 9-8 411 *----------------------------------------------------------------------- 412 */ 413 #define CONFIG_SYS_SCCR (SCCR_DFBRG00) 414 415 /*----------------------------------------------------------------------- 416 * RCCR - RISC Controller Configuration 13-7 417 *----------------------------------------------------------------------- 418 */ 419 #define CONFIG_SYS_RCCR 0 420 421 /* 422 * Init Memory Controller: 423 * 424 * Bank Bus Machine PortSz Device 425 * ---- --- ------- ------ ------ 426 * 0 60x GPCM 64 bit FLASH 427 * 1 60x SDRAM 64 bit SDRAM 428 * 429 */ 430 431 /* Initialize SDRAM on local bus 432 */ 433 #define CONFIG_SYS_INIT_LOCAL_SDRAM 434 435 436 /* Minimum mask to separate preliminary 437 * address ranges for CS[0:2] 438 */ 439 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000 440 441 /* 442 * we use the same values for 32 MB and 128 MB SDRAM 443 * refresh rate = 7.73 uS (64 MHz Bus Clock) 444 */ 445 #define CONFIG_SYS_MPTPR 0x2000 446 #define CONFIG_SYS_PSRT 0x0E 447 448 #define CONFIG_SYS_MRS_OFFS 0x00000000 449 450 451 #if defined(CONFIG_BOOT_ROM) 452 /* 453 * Bank 0 - Boot ROM (8 bit wide) 454 */ 455 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ 456 BRx_PS_8 |\ 457 BRx_MS_GPCM_P |\ 458 BRx_V) 459 460 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ 461 ORxG_CSNT |\ 462 ORxG_ACS_DIV1 |\ 463 ORxG_SCY_3_CLK |\ 464 ORxG_EHTR |\ 465 ORxG_TRLX) 466 467 /* 468 * Bank 1 - Flash (64 bit wide) 469 */ 470 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 471 BRx_PS_64 |\ 472 BRx_MS_GPCM_P |\ 473 BRx_V) 474 475 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 476 ORxG_CSNT |\ 477 ORxG_ACS_DIV1 |\ 478 ORxG_SCY_3_CLK |\ 479 ORxG_EHTR |\ 480 ORxG_TRLX) 481 482 #else /* ! CONFIG_BOOT_ROM */ 483 484 /* 485 * Bank 0 - Flash (64 bit wide) 486 */ 487 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 488 BRx_PS_64 |\ 489 BRx_MS_GPCM_P |\ 490 BRx_V) 491 492 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 493 ORxG_CSNT |\ 494 ORxG_ACS_DIV1 |\ 495 ORxG_SCY_3_CLK |\ 496 ORxG_EHTR |\ 497 ORxG_TRLX) 498 499 /* 500 * Bank 1 - Disk-On-Chip 501 */ 502 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ 503 BRx_PS_8 |\ 504 BRx_MS_GPCM_P |\ 505 BRx_V) 506 507 #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ 508 ORxG_CSNT |\ 509 ORxG_ACS_DIV1 |\ 510 ORxG_SCY_3_CLK |\ 511 ORxG_EHTR |\ 512 ORxG_TRLX) 513 514 #endif /* CONFIG_BOOT_ROM */ 515 516 /* Bank 2 - SDRAM 517 */ 518 519 #ifndef CONFIG_SYS_RAMBOOT 520 #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 521 BRx_PS_64 |\ 522 BRx_MS_SDRAM_P |\ 523 BRx_V) 524 525 /* SDRAM initialization values for 8-column chips 526 */ 527 #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ 528 ORxS_BPD_4 |\ 529 ORxS_ROWST_PBI0_A9 |\ 530 ORxS_NUMR_12) 531 532 #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ 533 PSDMR_BSMA_A14_A16 |\ 534 PSDMR_SDA10_PBI0_A10 |\ 535 PSDMR_RFRC_7_CLK |\ 536 PSDMR_PRETOACT_2W |\ 537 PSDMR_ACTTORW_1W |\ 538 PSDMR_LDOTOPRE_1C |\ 539 PSDMR_WRC_1C |\ 540 PSDMR_CL_2) 541 542 /* SDRAM initialization values for 9-column chips 543 */ 544 #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ 545 ORxS_BPD_4 |\ 546 ORxS_ROWST_PBI0_A7 |\ 547 ORxS_NUMR_13) 548 549 #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ 550 PSDMR_BSMA_A13_A15 |\ 551 PSDMR_SDA10_PBI0_A9 |\ 552 PSDMR_RFRC_7_CLK |\ 553 PSDMR_PRETOACT_2W |\ 554 PSDMR_ACTTORW_1W |\ 555 PSDMR_LDOTOPRE_1C |\ 556 PSDMR_WRC_1C |\ 557 PSDMR_CL_2) 558 559 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL 560 #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL 561 562 #endif /* CONFIG_SYS_RAMBOOT */ 563 564 #endif /* __CONFIG_H */ 565