1 /* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 37 #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ 38 39 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 40 #define CONFIG_SYS_SMC_RXBUFLEN 128 41 #define CONFIG_SYS_MAXIDLE 10 42 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 43 44 #define CONFIG_BOOTCOUNT_LIMIT 45 46 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 47 48 #define CONFIG_BOARD_TYPES 1 /* support board types */ 49 50 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 51 52 #undef CONFIG_BOOTARGS 53 54 #define CONFIG_EXTRA_ENV_SETTINGS \ 55 "netdev=eth0\0" \ 56 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 57 "nfsroot=${serverip}:${rootpath}\0" \ 58 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 59 "addip=setenv bootargs ${bootargs} " \ 60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 61 ":${hostname}:${netdev}:off panic=1\0" \ 62 "flash_nfs=run nfsargs addip;" \ 63 "bootm ${kernel_addr}\0" \ 64 "flash_self=run ramargs addip;" \ 65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 67 "rootpath=/opt/eldk/ppc_8xx\0" \ 68 "hostname=TQM850L\0" \ 69 "bootfile=TQM850L/uImage\0" \ 70 "fdt_addr=40040000\0" \ 71 "kernel_addr=40060000\0" \ 72 "ramdisk_addr=40200000\0" \ 73 "u-boot=TQM850L/u-image.bin\0" \ 74 "load=tftp 200000 ${u-boot}\0" \ 75 "update=prot off 40000000 +${filesize};" \ 76 "era 40000000 +${filesize};" \ 77 "cp.b 200000 40000000 ${filesize};" \ 78 "sete filesize;save\0" \ 79 "" 80 #define CONFIG_BOOTCOMMAND "run flash_self" 81 82 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 83 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 84 85 #undef CONFIG_WATCHDOG /* watchdog disabled */ 86 87 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 88 89 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 90 91 /* 92 * BOOTP options 93 */ 94 #define CONFIG_BOOTP_SUBNETMASK 95 #define CONFIG_BOOTP_GATEWAY 96 #define CONFIG_BOOTP_HOSTNAME 97 #define CONFIG_BOOTP_BOOTPATH 98 #define CONFIG_BOOTP_BOOTFILESIZE 99 100 101 #define CONFIG_MAC_PARTITION 102 #define CONFIG_DOS_PARTITION 103 104 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 105 106 /* 107 * Command line configuration. 108 */ 109 #include <config_cmd_default.h> 110 111 #define CONFIG_CMD_ASKENV 112 #define CONFIG_CMD_DATE 113 #define CONFIG_CMD_DHCP 114 #define CONFIG_CMD_ELF 115 #define CONFIG_CMD_EXT2 116 #define CONFIG_CMD_IDE 117 #define CONFIG_CMD_JFFS2 118 #define CONFIG_CMD_NFS 119 #define CONFIG_CMD_SNTP 120 121 122 #define CONFIG_NETCONSOLE 123 124 /* 125 * Miscellaneous configurable options 126 */ 127 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 128 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 129 130 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 131 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 132 #ifdef CONFIG_SYS_HUSH_PARSER 133 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 134 #endif 135 136 #if defined(CONFIG_CMD_KGDB) 137 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 138 #else 139 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 140 #endif 141 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 142 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 143 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 144 145 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 146 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 147 148 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 149 150 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 151 152 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 153 154 /* 155 * Low Level Configuration Settings 156 * (address mappings, register initial values, etc.) 157 * You should know what you are doing if you make changes here. 158 */ 159 /*----------------------------------------------------------------------- 160 * Internal Memory Mapped Register 161 */ 162 #define CONFIG_SYS_IMMR 0xFFF00000 163 164 /*----------------------------------------------------------------------- 165 * Definitions for initial stack pointer and data area (in DPRAM) 166 */ 167 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 168 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 169 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172 173 /*----------------------------------------------------------------------- 174 * Start addresses for the final memory configuration 175 * (Set up by the startup code) 176 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 177 */ 178 #define CONFIG_SYS_SDRAM_BASE 0x00000000 179 #define CONFIG_SYS_FLASH_BASE 0x40000000 180 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 182 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 183 184 /* 185 * For booting Linux, the board info and command line data 186 * have to be in the first 8 MB of memory, since this is 187 * the maximum mapped by the Linux kernel during initialization. 188 */ 189 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 190 191 /*----------------------------------------------------------------------- 192 * FLASH organization 193 */ 194 195 /* use CFI flash driver */ 196 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 197 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 198 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 199 #define CONFIG_SYS_FLASH_EMPTY_INFO 200 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 201 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 202 #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 203 204 #define CONFIG_ENV_IS_IN_FLASH 1 205 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 206 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 207 208 /* Address and size of Redundant Environment Sector */ 209 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 210 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 211 212 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 213 214 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 215 216 /*----------------------------------------------------------------------- 217 * Dynamic MTD partition support 218 */ 219 #define CONFIG_CMD_MTDPARTS 220 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 221 #define CONFIG_FLASH_CFI_MTD 222 #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 223 224 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 225 "128k(dtb)," \ 226 "1664k(kernel)," \ 227 "2m(rootfs)," \ 228 "4m(data)" 229 230 /*----------------------------------------------------------------------- 231 * Hardware Information Block 232 */ 233 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 234 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 235 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 236 237 /*----------------------------------------------------------------------- 238 * Cache Configuration 239 */ 240 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 241 #if defined(CONFIG_CMD_KGDB) 242 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 243 #endif 244 245 /*----------------------------------------------------------------------- 246 * SYPCR - System Protection Control 11-9 247 * SYPCR can only be written once after reset! 248 *----------------------------------------------------------------------- 249 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 250 */ 251 #if defined(CONFIG_WATCHDOG) 252 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 253 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 254 #else 255 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 256 #endif 257 258 /*----------------------------------------------------------------------- 259 * SIUMCR - SIU Module Configuration 11-6 260 *----------------------------------------------------------------------- 261 * PCMCIA config., multi-function pin tri-state 262 */ 263 #ifndef CONFIG_CAN_DRIVER 264 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 265 #else /* we must activate GPL5 in the SIUMCR for CAN */ 266 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 267 #endif /* CONFIG_CAN_DRIVER */ 268 269 /*----------------------------------------------------------------------- 270 * TBSCR - Time Base Status and Control 11-26 271 *----------------------------------------------------------------------- 272 * Clear Reference Interrupt Status, Timebase freezing enabled 273 */ 274 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 275 276 /*----------------------------------------------------------------------- 277 * RTCSC - Real-Time Clock Status and Control Register 11-27 278 *----------------------------------------------------------------------- 279 */ 280 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 281 282 /*----------------------------------------------------------------------- 283 * PISCR - Periodic Interrupt Status and Control 11-31 284 *----------------------------------------------------------------------- 285 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 286 */ 287 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 288 289 /*----------------------------------------------------------------------- 290 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 291 *----------------------------------------------------------------------- 292 * Reset PLL lock status sticky bit, timer expired status bit and timer 293 * interrupt status bit 294 */ 295 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 296 297 /*----------------------------------------------------------------------- 298 * SCCR - System Clock and reset Control Register 15-27 299 *----------------------------------------------------------------------- 300 * Set clock output, timebase and RTC source and divider, 301 * power management and some other internal clocks 302 */ 303 #define SCCR_MASK SCCR_EBDF11 304 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 305 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 306 SCCR_DFALCD00) 307 308 /*----------------------------------------------------------------------- 309 * PCMCIA stuff 310 *----------------------------------------------------------------------- 311 * 312 */ 313 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 314 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 315 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 316 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 317 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 318 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 319 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 320 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 321 322 /*----------------------------------------------------------------------- 323 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 324 *----------------------------------------------------------------------- 325 */ 326 327 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 328 329 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 330 #undef CONFIG_IDE_LED /* LED for ide not supported */ 331 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 332 333 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 334 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 335 336 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 337 338 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 339 340 /* Offset for data I/O */ 341 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 342 343 /* Offset for normal register accesses */ 344 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 345 346 /* Offset for alternate registers */ 347 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 348 349 /*----------------------------------------------------------------------- 350 * 351 *----------------------------------------------------------------------- 352 * 353 */ 354 #define CONFIG_SYS_DER 0 355 356 /* 357 * Init Memory Controller: 358 * 359 * BR0/1 and OR0/1 (FLASH) 360 */ 361 362 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 363 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 364 365 /* used to re-map FLASH both when starting from SRAM or FLASH: 366 * restrict access enough to keep SRAM working (if any) 367 * but not too much to meddle with FLASH accesses 368 */ 369 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 370 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 371 372 /* 373 * FLASH timing: 374 */ 375 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 376 OR_SCY_3_CLK | OR_EHTR | OR_BI) 377 378 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 379 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 380 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 381 382 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 383 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 384 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 385 386 /* 387 * BR2/3 and OR2/3 (SDRAM) 388 * 389 */ 390 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 391 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 392 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 393 394 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 395 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 396 397 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 398 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 399 400 #ifndef CONFIG_CAN_DRIVER 401 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 402 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 403 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 404 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 405 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 406 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 407 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 408 BR_PS_8 | BR_MS_UPMB | BR_V ) 409 #endif /* CONFIG_CAN_DRIVER */ 410 411 /* 412 * Memory Periodic Timer Prescaler 413 * 414 * The Divider for PTA (refresh timer) configuration is based on an 415 * example SDRAM configuration (64 MBit, one bank). The adjustment to 416 * the number of chip selects (NCS) and the actually needed refresh 417 * rate is done by setting MPTPR. 418 * 419 * PTA is calculated from 420 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 421 * 422 * gclk CPU clock (not bus clock!) 423 * Trefresh Refresh cycle * 4 (four word bursts used) 424 * 425 * 4096 Rows from SDRAM example configuration 426 * 1000 factor s -> ms 427 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 428 * 4 Number of refresh cycles per period 429 * 64 Refresh cycle in ms per number of rows 430 * -------------------------------------------- 431 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 432 * 433 * 50 MHz => 50.000.000 / Divider = 98 434 * 66 Mhz => 66.000.000 / Divider = 129 435 * 80 Mhz => 80.000.000 / Divider = 156 436 */ 437 438 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 439 #define CONFIG_SYS_MAMR_PTA 98 440 441 /* 442 * For 16 MBit, refresh rates could be 31.3 us 443 * (= 64 ms / 2K = 125 / quad bursts). 444 * For a simpler initialization, 15.6 us is used instead. 445 * 446 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 447 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 448 */ 449 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 450 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 451 452 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 453 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 454 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 455 456 /* 457 * MAMR settings for SDRAM 458 */ 459 460 /* 8 column SDRAM */ 461 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 462 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 463 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 464 /* 9 column SDRAM */ 465 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 466 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 467 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 468 469 470 /* 471 * Internal Definitions 472 * 473 * Boot Flags 474 */ 475 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 476 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 477 478 /* pass open firmware flat tree */ 479 #define CONFIG_OF_LIBFDT 1 480 #define CONFIG_OF_BOARD_SETUP 1 481 #define CONFIG_HWCONFIG 1 482 483 #endif /* __CONFIG_H */ 484