1 /* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuation settings for the LUBBOCK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #ifndef __CONFIG_H 31 #define __CONFIG_H 32 33 /* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ 38 #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ 39 #define CONFIG_LCD 1 40 #ifdef CONFIG_LCD 41 #define CONFIG_SHARP_LM8V31 42 #endif 43 #define CONFIG_MMC 44 #define BOARD_LATE_INIT 1 45 #define CONFIG_DOS_PARTITION 46 47 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 48 49 /* we will never enable dcache, because we have to setup MMU first */ 50 #define CONFIG_SYS_NO_DCACHE 51 52 /* 53 * Size of malloc() pool 54 */ 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 56 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 57 58 /* 59 * Hardware drivers 60 */ 61 #define CONFIG_NET_MULTI 62 #define CONFIG_LAN91C96 63 #define CONFIG_LAN91C96_BASE 0x0C000000 64 65 /* 66 * select serial console configuration 67 */ 68 #define CONFIG_PXA_SERIAL 69 #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ 70 71 /* allow to overwrite serial and ethaddr */ 72 #define CONFIG_ENV_OVERWRITE 73 74 #define CONFIG_BAUDRATE 115200 75 76 77 /* 78 * BOOTP options 79 */ 80 #define CONFIG_BOOTP_BOOTFILESIZE 81 #define CONFIG_BOOTP_BOOTPATH 82 #define CONFIG_BOOTP_GATEWAY 83 #define CONFIG_BOOTP_HOSTNAME 84 85 86 /* 87 * Command line configuration. 88 */ 89 #include <config_cmd_default.h> 90 91 #define CONFIG_CMD_FAT 92 93 94 #define CONFIG_BOOTDELAY 3 95 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b 96 #define CONFIG_NETMASK 255.255.0.0 97 #define CONFIG_IPADDR 192.168.0.21 98 #define CONFIG_SERVERIP 192.168.0.250 99 #define CONFIG_BOOTCOMMAND "bootm 80000" 100 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" 101 #define CONFIG_CMDLINE_TAG 102 #define CONFIG_TIMESTAMP 103 104 #if defined(CONFIG_CMD_KGDB) 105 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 106 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 107 #endif 108 109 /* 110 * Miscellaneous configurable options 111 */ 112 #define CONFIG_SYS_HUSH_PARSER 1 113 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 114 115 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 116 #ifdef CONFIG_SYS_HUSH_PARSER 117 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 118 #else 119 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 120 #endif 121 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 122 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 123 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 124 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 125 #define CONFIG_SYS_DEVICE_NULLDEV 1 126 127 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 129 130 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ 131 132 #define CONFIG_SYS_HZ 1000 133 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ 134 135 /* valid baudrates */ 136 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 137 138 #ifdef CONFIG_MMC 139 #define CONFIG_PXA_MMC 140 #define CONFIG_CMD_MMC 141 #define CONFIG_SYS_MMC_BASE 0xF0000000 142 #endif 143 144 /* 145 * Stack sizes 146 * 147 * The stack sizes are set up in start.S using the settings below 148 */ 149 #define CONFIG_STACKSIZE (128*1024) /* regular stack */ 150 #ifdef CONFIG_USE_IRQ 151 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 152 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 153 #endif 154 155 /* 156 * Physical Memory Map 157 */ 158 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ 159 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 160 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 161 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 162 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 163 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 164 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 165 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 166 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 167 168 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 169 #define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 170 #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 171 #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 172 #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 173 174 #define CONFIG_SYS_DRAM_BASE 0xa0000000 175 #define CONFIG_SYS_DRAM_SIZE 0x04000000 176 177 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 178 179 #define FPGA_REGS_BASE_PHYSICAL 0x08000000 180 181 /* 182 * GPIO settings 183 */ 184 #define CONFIG_SYS_GPSR0_VAL 0x00008000 185 #define CONFIG_SYS_GPSR1_VAL 0x00FC0382 186 #define CONFIG_SYS_GPSR2_VAL 0x0001FFFF 187 #define CONFIG_SYS_GPCR0_VAL 0x00000000 188 #define CONFIG_SYS_GPCR1_VAL 0x00000000 189 #define CONFIG_SYS_GPCR2_VAL 0x00000000 190 #define CONFIG_SYS_GPDR0_VAL 0x0060A800 191 #define CONFIG_SYS_GPDR1_VAL 0x00FF0382 192 #define CONFIG_SYS_GPDR2_VAL 0x0001C000 193 #define CONFIG_SYS_GAFR0_L_VAL 0x98400000 194 #define CONFIG_SYS_GAFR0_U_VAL 0x00002950 195 #define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 196 #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 197 #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 198 #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 199 200 #define CONFIG_SYS_PSSR_VAL 0x20 201 202 /* 203 * Memory settings 204 */ 205 #define CONFIG_SYS_MSC0_VAL 0x23F223F2 206 #define CONFIG_SYS_MSC1_VAL 0x3FF1A441 207 #define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 208 #define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 209 #define CONFIG_SYS_MDREFR_VAL 0x00018018 210 #define CONFIG_SYS_MDMRS_VAL 0x00000000 211 212 /* 213 * PCMCIA and CF Interfaces 214 */ 215 #define CONFIG_SYS_MECR_VAL 0x00000000 216 #define CONFIG_SYS_MCMEM0_VAL 0x00010504 217 #define CONFIG_SYS_MCMEM1_VAL 0x00010504 218 #define CONFIG_SYS_MCATT0_VAL 0x00010504 219 #define CONFIG_SYS_MCATT1_VAL 0x00010504 220 #define CONFIG_SYS_MCIO0_VAL 0x00004715 221 #define CONFIG_SYS_MCIO1_VAL 0x00004715 222 223 #define _LED 0x08000010 224 #define LED_BLANK 0x08000040 225 226 /* 227 * FLASH and environment organization 228 */ 229 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 230 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 231 232 /* timeout values are in ticks */ 233 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 234 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 235 236 /* NOTE: many default partitioning schemes assume the kernel starts at the 237 * second sector, not an environment. You have been warned! 238 */ 239 #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 240 #define CONFIG_ENV_IS_IN_FLASH 1 241 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) 242 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE 243 #define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) 244 245 246 /* 247 * FPGA Offsets 248 */ 249 #define WHOAMI_OFFSET 0x00 250 #define HEXLED_OFFSET 0x10 251 #define BLANKLED_OFFSET 0x40 252 #define DISCRETELED_OFFSET 0x40 253 #define CNFG_SWITCHES_OFFSET 0x50 254 #define USER_SWITCHES_OFFSET 0x60 255 #define MISC_WR_OFFSET 0x80 256 #define MISC_RD_OFFSET 0x90 257 #define INT_MASK_OFFSET 0xC0 258 #define INT_CLEAR_OFFSET 0xD0 259 #define GP_OFFSET 0x100 260 261 #endif /* __CONFIG_H */ 262