1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <spl.h>
8 #include <asm/io.h>
9 #include <fsl_ifc.h>
10 #include <i2c.h>
11 #include <fsl_csu.h>
12 #include <asm/arch/fdt.h>
13 #include <asm/arch/ppa.h>
14 #include <asm/arch/soc.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
spl_boot_device(void)18 u32 spl_boot_device(void)
19 {
20 #ifdef CONFIG_SPL_MMC_SUPPORT
21 return BOOT_DEVICE_MMC1;
22 #endif
23 #ifdef CONFIG_SPL_NAND_SUPPORT
24 return BOOT_DEVICE_NAND;
25 #endif
26 #ifdef CONFIG_QSPI_BOOT
27 return BOOT_DEVICE_NOR;
28 #endif
29 return 0;
30 }
31
32 #ifdef CONFIG_SPL_BUILD
33
spl_board_init(void)34 void spl_board_init(void)
35 {
36 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
37 /*
38 * In case of Secure Boot, the IBR configures the SMMU
39 * to allow only Secure transactions.
40 * SMMU must be reset in bypass mode.
41 * Set the ClientPD bit and Clear the USFCFG Bit
42 */
43 u32 val;
44 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
45 out_le32(SMMU_SCR0, val);
46 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
47 out_le32(SMMU_NSCR0, val);
48 #endif
49 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
50 enable_layerscape_ns_access();
51 #endif
52 #ifdef CONFIG_SPL_FSL_LS_PPA
53 ppa_init();
54 #endif
55 }
56
board_init_f(ulong dummy)57 void board_init_f(ulong dummy)
58 {
59 icache_enable();
60 /* Clear global data */
61 memset((void *)gd, 0, sizeof(gd_t));
62 board_early_init_f();
63 timer_init();
64 #ifdef CONFIG_ARCH_LS2080A
65 env_init();
66 #endif
67 get_clocks();
68
69 preloader_console_init();
70 spl_set_bd();
71
72 #ifdef CONFIG_SPL_I2C_SUPPORT
73 i2c_init_all();
74 #endif
75 #ifdef CONFIG_VID
76 init_func_vid();
77 #endif
78 dram_init();
79 #ifdef CONFIG_SPL_FSL_LS_PPA
80 #ifndef CONFIG_SYS_MEM_RESERVE_SECURE
81 #error Need secure RAM for PPA
82 #endif
83 /*
84 * Secure memory location is determined in dram_init_banksize().
85 * gd->ram_size is deducted by the size of secure ram.
86 */
87 dram_init_banksize();
88
89 /*
90 * After dram_init_bank_size(), we know U-Boot only uses the first
91 * memory bank regardless how big the memory is.
92 */
93 gd->ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
94
95 /*
96 * If PPA is loaded, U-Boot will resume running at EL2.
97 * Cache and MMU will be enabled. Need a place for TLB.
98 * U-Boot will be relocated to the end of available memory
99 * in first bank. At this point, we cannot know how much
100 * memory U-Boot uses. Put TLB table lower by SPL_TLB_SETBACK
101 * to avoid overlapping. As soon as the RAM version U-Boot sets
102 * up new MMU, this space is no longer needed.
103 */
104 gd->ram_top -= SPL_TLB_SETBACK;
105 gd->arch.tlb_size = PGTABLE_SIZE;
106 gd->arch.tlb_addr = (gd->ram_top - gd->arch.tlb_size) & ~(0x10000 - 1);
107 gd->arch.tlb_allocated = gd->arch.tlb_addr;
108 #endif /* CONFIG_SPL_FSL_LS_PPA */
109 #if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
110 qspi_ahb_init();
111 #endif
112 }
113
114 #ifdef CONFIG_SPL_OS_BOOT
115 /*
116 * Return
117 * 0 if booting into OS is selected
118 * 1 if booting into U-Boot is selected
119 */
spl_start_uboot(void)120 int spl_start_uboot(void)
121 {
122 env_init();
123 if (env_get_yesno("boot_os") != 0)
124 return 0;
125
126 return 1;
127 }
128 #endif /* CONFIG_SPL_OS_BOOT */
129 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)130 int board_fit_config_name_match(const char *name)
131 {
132 /* Just empty function now - can't decide what to choose */
133 debug("%s: %s\n", __func__, name);
134
135 return 0;
136 }
137 #endif
138 #endif /* CONFIG_SPL_BUILD */
139