1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * (C) Copyright 2015 Google, Inc
4  * Copyright 2014 Rockchip Inc.
5  */
6 
7 #ifndef _ASM_ARCH_GRF_RK3288_H
8 #define _ASM_ARCH_GRF_RK3288_H
9 
10 struct rk3288_grf_gpio_lh {
11 	u32 l;
12 	u32 h;
13 };
14 
15 struct rk3288_grf {
16 	u32 reserved[3];
17 	u32 gpio1d_iomux;
18 	u32 gpio2a_iomux;
19 	u32 gpio2b_iomux;
20 
21 	u32 gpio2c_iomux;
22 	u32 reserved2;
23 	u32 gpio3a_iomux;
24 	u32 gpio3b_iomux;
25 
26 	u32 gpio3c_iomux;
27 	u32 gpio3dl_iomux;
28 	u32 gpio3dh_iomux;
29 	u32 gpio4al_iomux;
30 
31 	u32 gpio4ah_iomux;
32 	u32 gpio4bl_iomux;
33 	u32 reserved3;
34 	u32 gpio4c_iomux;
35 
36 	u32 gpio4d_iomux;
37 	u32 reserved4;
38 	u32 gpio5b_iomux;
39 	u32 gpio5c_iomux;
40 
41 	u32 reserved5;
42 	u32 gpio6a_iomux;
43 	u32 gpio6b_iomux;
44 	u32 gpio6c_iomux;
45 	u32 reserved6;
46 	u32 gpio7a_iomux;
47 	u32 gpio7b_iomux;
48 	u32 gpio7cl_iomux;
49 	u32 gpio7ch_iomux;
50 	u32 reserved7;
51 	u32 gpio8a_iomux;
52 	u32 gpio8b_iomux;
53 	u32 reserved8[30];
54 	struct rk3288_grf_gpio_lh gpio_sr[8];
55 	u32 gpio1_p[8][4];
56 	u32 gpio1_e[8][4];
57 	u32 gpio_smt;
58 	u32 soc_con0;
59 	u32 soc_con1;
60 	u32 soc_con2;
61 	u32 soc_con3;
62 	u32 soc_con4;
63 	u32 soc_con5;
64 	u32 soc_con6;
65 	u32 soc_con7;
66 	u32 soc_con8;
67 	u32 soc_con9;
68 	u32 soc_con10;
69 	u32 soc_con11;
70 	u32 soc_con12;
71 	u32 soc_con13;
72 	u32 soc_con14;
73 	u32 soc_status[22];
74 	u32 reserved9[2];
75 	u32 peridmac_con[4];
76 	u32 ddrc0_con0;
77 	u32 ddrc1_con0;
78 	u32 cpu_con[5];
79 	u32 reserved10[3];
80 	u32 cpu_status0;
81 	u32 reserved11;
82 	u32 uoc0_con[5];
83 	u32 uoc1_con[5];
84 	u32 uoc2_con[4];
85 	u32 uoc3_con[2];
86 	u32 uoc4_con[2];
87 	u32 pvtm_con[3];
88 	u32 pvtm_status[3];
89 	u32 io_vsel;
90 	u32 saradc_testbit;
91 	u32 tsadc_testbit_l;
92 	u32 tsadc_testbit_h;
93 	u32 os_reg[4];
94 	u32 reserved12;
95 	u32 soc_con15;
96 	u32 soc_con16;
97 };
98 
99 struct rk3288_sgrf {
100 	u32 soc_con0;
101 	u32 soc_con1;
102 	u32 soc_con2;
103 	u32 soc_con3;
104 	u32 soc_con4;
105 	u32 soc_con5;
106 	u32 reserved1[(0x20-0x18)/4];
107 	u32 busdmac_con[2];
108 	u32 reserved2[(0x40-0x28)/4];
109 	u32 cpu_con[3];
110 	u32 reserved3[(0x50-0x4c)/4];
111 	u32 soc_con6;
112 	u32 soc_con7;
113 	u32 soc_con8;
114 	u32 soc_con9;
115 	u32 soc_con10;
116 	u32 soc_con11;
117 	u32 soc_con12;
118 	u32 soc_con13;
119 	u32 soc_con14;
120 	u32 soc_con15;
121 	u32 soc_con16;
122 	u32 soc_con17;
123 	u32 soc_con18;
124 	u32 soc_con19;
125 	u32 soc_con20;
126 	u32 soc_con21;
127 	u32 reserved4[(0x100-0x90)/4];
128 	u32 soc_status[2];
129 	u32 reserved5[(0x120-0x108)/4];
130 	u32 fast_boot_addr;
131 };
132 
133 /* GRF_GPIO1D_IOMUX */
134 enum {
135 	GPIO1D3_SHIFT		= 6,
136 	GPIO1D3_MASK		= 1,
137 	GPIO1D3_GPIO		= 0,
138 	GPIO1D3_LCDC0_DCLK,
139 
140 	GPIO1D2_SHIFT		= 4,
141 	GPIO1D2_MASK		= 1,
142 	GPIO1D2_GPIO		= 0,
143 	GPIO1D2_LCDC0_DEN,
144 
145 	GPIO1D1_SHIFT		= 2,
146 	GPIO1D1_MASK		= 1,
147 	GPIO1D1_GPIO		= 0,
148 	GPIO1D1_LCDC0_VSYNC,
149 
150 	GPIO1D0_SHIFT		= 0,
151 	GPIO1D0_MASK		= 1,
152 	GPIO1D0_GPIO		= 0,
153 	GPIO1D0_LCDC0_HSYNC,
154 };
155 
156 /* GRF_GPIO2C_IOMUX */
157 enum {
158 	GPIO2C1_SHIFT		= 2,
159 	GPIO2C1_MASK		= 1,
160 	GPIO2C1_GPIO		= 0,
161 	GPIO2C1_I2C3CAM_SDA,
162 
163 	GPIO2C0_SHIFT		= 0,
164 	GPIO2C0_MASK		= 1,
165 	GPIO2C0_GPIO		= 0,
166 	GPIO2C0_I2C3CAM_SCL,
167 };
168 
169 /* GRF_GPIO3A_IOMUX */
170 enum {
171 	GPIO3A7_SHIFT		= 14,
172 	GPIO3A7_MASK		= 3,
173 	GPIO3A7_GPIO		= 0,
174 	GPIO3A7_FLASH0_DATA7,
175 	GPIO3A7_EMMC_DATA7,
176 
177 	GPIO3A6_SHIFT		= 12,
178 	GPIO3A6_MASK		= 3,
179 	GPIO3A6_GPIO		= 0,
180 	GPIO3A6_FLASH0_DATA6,
181 	GPIO3A6_EMMC_DATA6,
182 
183 	GPIO3A5_SHIFT		= 10,
184 	GPIO3A5_MASK		= 3,
185 	GPIO3A5_GPIO		= 0,
186 	GPIO3A5_FLASH0_DATA5,
187 	GPIO3A5_EMMC_DATA5,
188 
189 	GPIO3A4_SHIFT		= 8,
190 	GPIO3A4_MASK		= 3,
191 	GPIO3A4_GPIO		= 0,
192 	GPIO3A4_FLASH0_DATA4,
193 	GPIO3A4_EMMC_DATA4,
194 
195 	GPIO3A3_SHIFT		= 6,
196 	GPIO3A3_MASK		= 3,
197 	GPIO3A3_GPIO		= 0,
198 	GPIO3A3_FLASH0_DATA3,
199 	GPIO3A3_EMMC_DATA3,
200 
201 	GPIO3A2_SHIFT		= 4,
202 	GPIO3A2_MASK		= 3,
203 	GPIO3A2_GPIO		= 0,
204 	GPIO3A2_FLASH0_DATA2,
205 	GPIO3A2_EMMC_DATA2,
206 
207 	GPIO3A1_SHIFT		= 2,
208 	GPIO3A1_MASK		= 3,
209 	GPIO3A1_GPIO		= 0,
210 	GPIO3A1_FLASH0_DATA1,
211 	GPIO3A1_EMMC_DATA1,
212 
213 	GPIO3A0_SHIFT		= 0,
214 	GPIO3A0_MASK		= 3,
215 	GPIO3A0_GPIO		= 0,
216 	GPIO3A0_FLASH0_DATA0,
217 	GPIO3A0_EMMC_DATA0,
218 };
219 
220 /* GRF_GPIO3B_IOMUX */
221 enum {
222 	GPIO3B7_SHIFT		= 14,
223 	GPIO3B7_MASK		= 1,
224 	GPIO3B7_GPIO		= 0,
225 	GPIO3B7_FLASH0_CSN1,
226 
227 	GPIO3B6_SHIFT		= 12,
228 	GPIO3B6_MASK		= 1,
229 	GPIO3B6_GPIO		= 0,
230 	GPIO3B6_FLASH0_CSN0,
231 
232 	GPIO3B5_SHIFT		= 10,
233 	GPIO3B5_MASK		= 1,
234 	GPIO3B5_GPIO		= 0,
235 	GPIO3B5_FLASH0_WRN,
236 
237 	GPIO3B4_SHIFT		= 8,
238 	GPIO3B4_MASK		= 1,
239 	GPIO3B4_GPIO		= 0,
240 	GPIO3B4_FLASH0_CLE,
241 
242 	GPIO3B3_SHIFT		= 6,
243 	GPIO3B3_MASK		= 1,
244 	GPIO3B3_GPIO		= 0,
245 	GPIO3B3_FLASH0_ALE,
246 
247 	GPIO3B2_SHIFT		= 4,
248 	GPIO3B2_MASK		= 1,
249 	GPIO3B2_GPIO		= 0,
250 	GPIO3B2_FLASH0_RDN,
251 
252 	GPIO3B1_SHIFT		= 2,
253 	GPIO3B1_MASK		= 3,
254 	GPIO3B1_GPIO		= 0,
255 	GPIO3B1_FLASH0_WP,
256 	GPIO3B1_EMMC_PWREN,
257 
258 	GPIO3B0_SHIFT		= 0,
259 	GPIO3B0_MASK		= 1,
260 	GPIO3B0_GPIO		= 0,
261 	GPIO3B0_FLASH0_RDY,
262 };
263 
264 /* GRF_GPIO3C_IOMUX */
265 enum {
266 	GPIO3C2_SHIFT		= 4,
267 	GPIO3C2_MASK		= 3,
268 	GPIO3C2_GPIO		= 0,
269 	GPIO3C2_FLASH0_DQS,
270 	GPIO3C2_EMMC_CLKOUT,
271 
272 	GPIO3C1_SHIFT		= 2,
273 	GPIO3C1_MASK		= 3,
274 	GPIO3C1_GPIO		= 0,
275 	GPIO3C1_FLASH0_CSN3,
276 	GPIO3C1_EMMC_RSTNOUT,
277 
278 	GPIO3C0_SHIFT		= 0,
279 	GPIO3C0_MASK		= 3,
280 	GPIO3C0_GPIO		= 0,
281 	GPIO3C0_FLASH0_CSN2,
282 	GPIO3C0_EMMC_CMD,
283 };
284 
285 /* GRF_GPIO3DL_IOMUX */
286 enum {
287 	GPIO3D3_SHIFT		= 12,
288 	GPIO3D3_MASK		= 7,
289 	GPIO3D3_GPIO		= 0,
290 	GPIO3D3_FLASH1_DATA3,
291 	GPIO3D3_HOST_DOUT3,
292 	GPIO3D3_MAC_RXD3,
293 	GPIO3D3_SDIO1_DATA3,
294 
295 	GPIO3D2_SHIFT		= 8,
296 	GPIO3D2_MASK		= 7,
297 	GPIO3D2_GPIO		= 0,
298 	GPIO3D2_FLASH1_DATA2,
299 	GPIO3D2_HOST_DOUT2,
300 	GPIO3D2_MAC_RXD2,
301 	GPIO3D2_SDIO1_DATA2,
302 
303 	GPIO3D1_SHIFT		= 4,
304 	GPIO3D1_MASK		= 7,
305 	GPIO3D1_GPIO		= 0,
306 	GPIO3DL1_FLASH1_DATA1,
307 	GPIO3D1_HOST_DOUT1,
308 	GPIO3D1_MAC_TXD3,
309 	GPIO3D1_SDIO1_DATA1,
310 
311 	GPIO3D0_SHIFT		= 0,
312 	GPIO3D0_MASK		= 7,
313 	GPIO3D0_GPIO		= 0,
314 	GPIO3D0_FLASH1_DATA0,
315 	GPIO3D0_HOST_DOUT0,
316 	GPIO3D0_MAC_TXD2,
317 	GPIO3D0_SDIO1_DATA0,
318 };
319 
320 /* GRF_GPIO3HL_IOMUX */
321 enum {
322 	GPIO3D7_SHIFT		= 12,
323 	GPIO3D7_MASK		= 7,
324 	GPIO3D7_GPIO		= 0,
325 	GPIO3D7_FLASH1_DATA7,
326 	GPIO3D7_HOST_DOUT7,
327 	GPIO3D7_MAC_RXD1,
328 	GPIO3D7_SDIO1_INTN,
329 
330 	GPIO3D6_SHIFT		= 8,
331 	GPIO3D6_MASK		= 7,
332 	GPIO3D6_GPIO		= 0,
333 	GPIO3D6_FLASH1_DATA6,
334 	GPIO3D6_HOST_DOUT6,
335 	GPIO3D6_MAC_RXD0,
336 	GPIO3D6_SDIO1_BKPWR,
337 
338 	GPIO3D5_SHIFT		= 4,
339 	GPIO3D5_MASK		= 7,
340 	GPIO3D5_GPIO		= 0,
341 	GPIO3D5_FLASH1_DATA5,
342 	GPIO3D5_HOST_DOUT5,
343 	GPIO3D5_MAC_TXD1,
344 	GPIO3D5_SDIO1_WRPRT,
345 
346 	GPIO3D4_SHIFT		= 0,
347 	GPIO3D4_MASK		= 7,
348 	GPIO3D4_GPIO		= 0,
349 	GPIO3D4_FLASH1_DATA4,
350 	GPIO3D4_HOST_DOUT4,
351 	GPIO3D4_MAC_TXD0,
352 	GPIO3D4_SDIO1_DETECTN,
353 };
354 
355 /* GRF_GPIO4AL_IOMUX */
356 enum {
357 	GPIO4A3_SHIFT		= 12,
358 	GPIO4A3_MASK		= 7,
359 	GPIO4A3_GPIO		= 0,
360 	GPIO4A3_FLASH1_ALE,
361 	GPIO4A3_HOST_DOUT9,
362 	GPIO4A3_MAC_CLK,
363 	GPIO4A3_FLASH0_CSN6,
364 
365 	GPIO4A2_SHIFT		= 8,
366 	GPIO4A2_MASK		= 7,
367 	GPIO4A2_GPIO		= 0,
368 	GPIO4A2_FLASH1_RDN,
369 	GPIO4A2_HOST_DOUT8,
370 	GPIO4A2_MAC_RXER,
371 	GPIO4A2_FLASH0_CSN5,
372 
373 	GPIO4A1_SHIFT		= 4,
374 	GPIO4A1_MASK		= 7,
375 	GPIO4A1_GPIO		= 0,
376 	GPIO4A1_FLASH1_WP,
377 	GPIO4A1_HOST_CKOUTN,
378 	GPIO4A1_MAC_TXDV,
379 	GPIO4A1_FLASH0_CSN4,
380 
381 	GPIO4A0_SHIFT		= 0,
382 	GPIO4A0_MASK		= 3,
383 	GPIO4A0_GPIO		= 0,
384 	GPIO4A0_FLASH1_RDY,
385 	GPIO4A0_HOST_CKOUTP,
386 	GPIO4A0_MAC_MDC,
387 };
388 
389 /* GRF_GPIO4AH_IOMUX */
390 enum {
391 	GPIO4A7_SHIFT		= 12,
392 	GPIO4A7_MASK		= 7,
393 	GPIO4A7_GPIO		= 0,
394 	GPIO4A7_FLASH1_CSN1,
395 	GPIO4A7_HOST_DOUT13,
396 	GPIO4A7_MAC_CSR,
397 	GPIO4A7_SDIO1_CLKOUT,
398 
399 	GPIO4A6_SHIFT		= 8,
400 	GPIO4A6_MASK		= 7,
401 	GPIO4A6_GPIO		= 0,
402 	GPIO4A6_FLASH1_CSN0,
403 	GPIO4A6_HOST_DOUT12,
404 	GPIO4A6_MAC_RXCLK,
405 	GPIO4A6_SDIO1_CMD,
406 
407 	GPIO4A5_SHIFT		= 4,
408 	GPIO4A5_MASK		= 3,
409 	GPIO4A5_GPIO		= 0,
410 	GPIO4A5_FLASH1_WRN,
411 	GPIO4A5_HOST_DOUT11,
412 	GPIO4A5_MAC_MDIO,
413 
414 	GPIO4A4_SHIFT		= 0,
415 	GPIO4A4_MASK		= 7,
416 	GPIO4A4_GPIO		= 0,
417 	GPIO4A4_FLASH1_CLE,
418 	GPIO4A4_HOST_DOUT10,
419 	GPIO4A4_MAC_TXEN,
420 	GPIO4A4_FLASH0_CSN7,
421 };
422 
423 /* GRF_GPIO4BL_IOMUX */
424 enum {
425 	GPIO4B1_SHIFT		= 4,
426 	GPIO4B1_MASK		= 7,
427 	GPIO4B1_GPIO		= 0,
428 	GPIO4B1_FLASH1_CSN2,
429 	GPIO4B1_HOST_DOUT15,
430 	GPIO4B1_MAC_TXCLK,
431 	GPIO4B1_SDIO1_PWREN,
432 
433 	GPIO4B0_SHIFT		= 0,
434 	GPIO4B0_MASK		= 7,
435 	GPIO4B0_GPIO		= 0,
436 	GPIO4B0_FLASH1_DQS,
437 	GPIO4B0_HOST_DOUT14,
438 	GPIO4B0_MAC_COL,
439 	GPIO4B0_FLASH1_CSN3,
440 };
441 
442 /* GRF_GPIO4C_IOMUX */
443 enum {
444 	GPIO4C7_SHIFT		= 14,
445 	GPIO4C7_MASK		= 1,
446 	GPIO4C7_GPIO		= 0,
447 	GPIO4C7_SDIO0_DATA3,
448 
449 	GPIO4C6_SHIFT		= 12,
450 	GPIO4C6_MASK		= 1,
451 	GPIO4C6_GPIO		= 0,
452 	GPIO4C6_SDIO0_DATA2,
453 
454 	GPIO4C5_SHIFT		= 10,
455 	GPIO4C5_MASK		= 1,
456 	GPIO4C5_GPIO		= 0,
457 	GPIO4C5_SDIO0_DATA1,
458 
459 	GPIO4C4_SHIFT		= 8,
460 	GPIO4C4_MASK		= 1,
461 	GPIO4C4_GPIO		= 0,
462 	GPIO4C4_SDIO0_DATA0,
463 
464 	GPIO4C3_SHIFT		= 6,
465 	GPIO4C3_MASK		= 1,
466 	GPIO4C3_GPIO		= 0,
467 	GPIO4C3_UART0BT_RTSN,
468 
469 	GPIO4C2_SHIFT		= 4,
470 	GPIO4C2_MASK		= 1,
471 	GPIO4C2_GPIO		= 0,
472 	GPIO4C2_UART0BT_CTSN,
473 
474 	GPIO4C1_SHIFT		= 2,
475 	GPIO4C1_MASK		= 1,
476 	GPIO4C1_GPIO		= 0,
477 	GPIO4C1_UART0BT_SOUT,
478 
479 	GPIO4C0_SHIFT		= 0,
480 	GPIO4C0_MASK		= 1,
481 	GPIO4C0_GPIO		= 0,
482 	GPIO4C0_UART0BT_SIN,
483 };
484 
485 /* GRF_GPIO5B_IOMUX */
486 enum {
487 	GPIO5B7_SHIFT		= 14,
488 	GPIO5B7_MASK		= 3,
489 	GPIO5B7_GPIO		= 0,
490 	GPIO5B7_SPI0_RXD,
491 	GPIO5B7_TS0_DATA7,
492 	GPIO5B7_UART4EXP_SIN,
493 
494 	GPIO5B6_SHIFT		= 12,
495 	GPIO5B6_MASK		= 3,
496 	GPIO5B6_GPIO		= 0,
497 	GPIO5B6_SPI0_TXD,
498 	GPIO5B6_TS0_DATA6,
499 	GPIO5B6_UART4EXP_SOUT,
500 
501 	GPIO5B5_SHIFT		= 10,
502 	GPIO5B5_MASK		= 3,
503 	GPIO5B5_GPIO		= 0,
504 	GPIO5B5_SPI0_CSN0,
505 	GPIO5B5_TS0_DATA5,
506 	GPIO5B5_UART4EXP_RTSN,
507 
508 	GPIO5B4_SHIFT		= 8,
509 	GPIO5B4_MASK		= 3,
510 	GPIO5B4_GPIO		= 0,
511 	GPIO5B4_SPI0_CLK,
512 	GPIO5B4_TS0_DATA4,
513 	GPIO5B4_UART4EXP_CTSN,
514 
515 	GPIO5B3_SHIFT		= 6,
516 	GPIO5B3_MASK		= 3,
517 	GPIO5B3_GPIO		= 0,
518 	GPIO5B3_UART1BB_RTSN,
519 	GPIO5B3_TS0_DATA3,
520 
521 	GPIO5B2_SHIFT		= 4,
522 	GPIO5B2_MASK		= 3,
523 	GPIO5B2_GPIO		= 0,
524 	GPIO5B2_UART1BB_CTSN,
525 	GPIO5B2_TS0_DATA2,
526 
527 	GPIO5B1_SHIFT		= 2,
528 	GPIO5B1_MASK		= 3,
529 	GPIO5B1_GPIO		= 0,
530 	GPIO5B1_UART1BB_SOUT,
531 	GPIO5B1_TS0_DATA1,
532 
533 	GPIO5B0_SHIFT		= 0,
534 	GPIO5B0_MASK		= 3,
535 	GPIO5B0_GPIO		= 0,
536 	GPIO5B0_UART1BB_SIN,
537 	GPIO5B0_TS0_DATA0,
538 };
539 
540 /* GRF_GPIO5C_IOMUX */
541 enum {
542 	GPIO5C3_SHIFT		= 6,
543 	GPIO5C3_MASK		= 1,
544 	GPIO5C3_GPIO		= 0,
545 	GPIO5C3_TS0_ERR,
546 
547 	GPIO5C2_SHIFT		= 4,
548 	GPIO5C2_MASK		= 1,
549 	GPIO5C2_GPIO		= 0,
550 	GPIO5C2_TS0_CLK,
551 
552 	GPIO5C1_SHIFT		= 2,
553 	GPIO5C1_MASK		= 1,
554 	GPIO5C1_GPIO		= 0,
555 	GPIO5C1_TS0_VALID,
556 
557 	GPIO5C0_SHIFT		= 0,
558 	GPIO5C0_MASK		= 3,
559 	GPIO5C0_GPIO		= 0,
560 	GPIO5C0_SPI0_CSN1,
561 	GPIO5C0_TS0_SYNC,
562 };
563 
564 /* GRF_GPIO6B_IOMUX */
565 enum {
566 	GPIO6B3_SHIFT		= 6,
567 	GPIO6B3_MASK		= 1,
568 	GPIO6B3_GPIO		= 0,
569 	GPIO6B3_SPDIF_TX,
570 
571 	GPIO6B2_SHIFT		= 4,
572 	GPIO6B2_MASK		= 1,
573 	GPIO6B2_GPIO		= 0,
574 	GPIO6B2_I2C1AUDIO_SCL,
575 
576 	GPIO6B1_SHIFT		= 2,
577 	GPIO6B1_MASK		= 1,
578 	GPIO6B1_GPIO		= 0,
579 	GPIO6B1_I2C1AUDIO_SDA,
580 
581 	GPIO6B0_SHIFT		= 0,
582 	GPIO6B0_MASK		= 1,
583 	GPIO6B0_GPIO		= 0,
584 	GPIO6B0_I2S_CLK,
585 };
586 
587 /* GRF_GPIO6C_IOMUX */
588 enum {
589 	GPIO6C6_SHIFT		= 12,
590 	GPIO6C6_MASK		= 1,
591 	GPIO6C6_GPIO		= 0,
592 	GPIO6C6_SDMMC0_DECTN,
593 
594 	GPIO6C5_SHIFT		= 10,
595 	GPIO6C5_MASK		= 1,
596 	GPIO6C5_GPIO		= 0,
597 	GPIO6C5_SDMMC0_CMD,
598 
599 	GPIO6C4_SHIFT		= 8,
600 	GPIO6C4_MASK		= 3,
601 	GPIO6C4_GPIO		= 0,
602 	GPIO6C4_SDMMC0_CLKOUT,
603 	GPIO6C4_JTAG_TDO,
604 
605 	GPIO6C3_SHIFT		= 6,
606 	GPIO6C3_MASK		= 3,
607 	GPIO6C3_GPIO		= 0,
608 	GPIO6C3_SDMMC0_DATA3,
609 	GPIO6C3_JTAG_TCK,
610 
611 	GPIO6C2_SHIFT		= 4,
612 	GPIO6C2_MASK		= 3,
613 	GPIO6C2_GPIO		= 0,
614 	GPIO6C2_SDMMC0_DATA2,
615 	GPIO6C2_JTAG_TDI,
616 
617 	GPIO6C1_SHIFT		= 2,
618 	GPIO6C1_MASK		= 3,
619 	GPIO6C1_GPIO		= 0,
620 	GPIO6C1_SDMMC0_DATA1,
621 	GPIO6C1_JTAG_TRSTN,
622 
623 	GPIO6C0_SHIFT		= 0,
624 	GPIO6C0_MASK		= 3,
625 	GPIO6C0_GPIO		= 0,
626 	GPIO6C0_SDMMC0_DATA0,
627 	GPIO6C0_JTAG_TMS,
628 };
629 
630 /* GRF_GPIO7A_IOMUX */
631 enum {
632 	GPIO7A7_SHIFT		= 14,
633 	GPIO7A7_MASK		= 3,
634 	GPIO7A7_GPIO		= 0,
635 	GPIO7A7_UART3GPS_SIN,
636 	GPIO7A7_GPS_MAG,
637 	GPIO7A7_HSADCT1_DATA0,
638 
639 	GPIO7A1_SHIFT		= 2,
640 	GPIO7A1_MASK		= 1,
641 	GPIO7A1_GPIO		= 0,
642 	GPIO7A1_PWM_1,
643 
644 	GPIO7A0_SHIFT		= 0,
645 	GPIO7A0_MASK		= 3,
646 	GPIO7A0_GPIO		= 0,
647 	GPIO7A0_PWM_0,
648 	GPIO7A0_VOP0_PWM,
649 	GPIO7A0_VOP1_PWM,
650 };
651 
652 /* GRF_GPIO7B_IOMUX */
653 enum {
654 	GPIO7B7_SHIFT		= 14,
655 	GPIO7B7_MASK		= 3,
656 	GPIO7B7_GPIO		= 0,
657 	GPIO7B7_ISP_SHUTTERTRIG,
658 	GPIO7B7_SPI1_TXD,
659 
660 	GPIO7B6_SHIFT		= 12,
661 	GPIO7B6_MASK		= 3,
662 	GPIO7B6_GPIO		= 0,
663 	GPIO7B6_ISP_PRELIGHTTRIG,
664 	GPIO7B6_SPI1_RXD,
665 
666 	GPIO7B5_SHIFT		= 10,
667 	GPIO7B5_MASK		= 3,
668 	GPIO7B5_GPIO		= 0,
669 	GPIO7B5_ISP_FLASHTRIGOUT,
670 	GPIO7B5_SPI1_CSN0,
671 
672 	GPIO7B4_SHIFT		= 8,
673 	GPIO7B4_MASK		= 3,
674 	GPIO7B4_GPIO		= 0,
675 	GPIO7B4_ISP_SHUTTEREN,
676 	GPIO7B4_SPI1_CLK,
677 
678 	GPIO7B3_SHIFT		= 6,
679 	GPIO7B3_MASK		= 3,
680 	GPIO7B3_GPIO		= 0,
681 	GPIO7B3_USB_DRVVBUS1,
682 	GPIO7B3_EDP_HOTPLUG,
683 
684 	GPIO7B2_SHIFT		= 4,
685 	GPIO7B2_MASK		= 3,
686 	GPIO7B2_GPIO		= 0,
687 	GPIO7B2_UART3GPS_RTSN,
688 	GPIO7B2_USB_DRVVBUS0,
689 
690 	GPIO7B1_SHIFT		= 2,
691 	GPIO7B1_MASK		= 3,
692 	GPIO7B1_GPIO		= 0,
693 	GPIO7B1_UART3GPS_CTSN,
694 	GPIO7B1_GPS_RFCLK,
695 	GPIO7B1_GPST1_CLK,
696 
697 	GPIO7B0_SHIFT		= 0,
698 	GPIO7B0_MASK		= 3,
699 	GPIO7B0_GPIO		= 0,
700 	GPIO7B0_UART3GPS_SOUT,
701 	GPIO7B0_GPS_SIG,
702 	GPIO7B0_HSADCT1_DATA1,
703 };
704 
705 /* GRF_GPIO7CL_IOMUX */
706 enum {
707 	GPIO7C3_SHIFT		= 12,
708 	GPIO7C3_MASK		= 3,
709 	GPIO7C3_GPIO		= 0,
710 	GPIO7C3_I2C5HDMI_SDA,
711 	GPIO7C3_EDPHDMII2C_SDA,
712 
713 	GPIO7C2_SHIFT		= 8,
714 	GPIO7C2_MASK		= 1,
715 	GPIO7C2_GPIO		= 0,
716 	GPIO7C2_I2C4TP_SCL,
717 
718 	GPIO7C1_SHIFT		= 4,
719 	GPIO7C1_MASK		= 1,
720 	GPIO7C1_GPIO		= 0,
721 	GPIO7C1_I2C4TP_SDA,
722 
723 	GPIO7C0_SHIFT		= 0,
724 	GPIO7C0_MASK		= 3,
725 	GPIO7C0_GPIO		= 0,
726 	GPIO7C0_ISP_FLASHTRIGIN,
727 	GPIO7C0_EDPHDMI_CECINOUTT1,
728 };
729 
730 /* GRF_GPIO7CH_IOMUX */
731 enum {
732 	GPIO7C7_SHIFT		= 12,
733 	GPIO7C7_MASK		= 7,
734 	GPIO7C7_GPIO		= 0,
735 	GPIO7C7_UART2DBG_SOUT,
736 	GPIO7C7_UART2DBG_SIROUT,
737 	GPIO7C7_PWM_3,
738 	GPIO7C7_EDPHDMI_CECINOUT,
739 
740 	GPIO7C6_SHIFT		= 8,
741 	GPIO7C6_MASK		= 3,
742 	GPIO7C6_GPIO		= 0,
743 	GPIO7C6_UART2DBG_SIN,
744 	GPIO7C6_UART2DBG_SIRIN,
745 	GPIO7C6_PWM_2,
746 
747 	GPIO7C4_SHIFT		= 0,
748 	GPIO7C4_MASK		= 3,
749 	GPIO7C4_GPIO		= 0,
750 	GPIO7C4_I2C5HDMI_SCL,
751 	GPIO7C4_EDPHDMII2C_SCL,
752 };
753 
754 /* GRF_GPIO8A_IOMUX */
755 enum {
756 	GPIO8A7_SHIFT		= 14,
757 	GPIO8A7_MASK		= 3,
758 	GPIO8A7_GPIO		= 0,
759 	GPIO8A7_SPI2_CSN0,
760 	GPIO8A7_SC_DETECT,
761 	GPIO8A7_RESERVE,
762 
763 	GPIO8A6_SHIFT		= 12,
764 	GPIO8A6_MASK		= 3,
765 	GPIO8A6_GPIO		= 0,
766 	GPIO8A6_SPI2_CLK,
767 	GPIO8A6_SC_IO,
768 	GPIO8A6_RESERVE,
769 
770 	GPIO8A5_SHIFT		= 10,
771 	GPIO8A5_MASK		= 3,
772 	GPIO8A5_GPIO		= 0,
773 	GPIO8A5_I2C2SENSOR_SCL,
774 	GPIO8A5_SC_CLK,
775 
776 	GPIO8A4_SHIFT		= 8,
777 	GPIO8A4_MASK		= 3,
778 	GPIO8A4_GPIO		= 0,
779 	GPIO8A4_I2C2SENSOR_SDA,
780 	GPIO8A4_SC_RST,
781 
782 	GPIO8A3_SHIFT		= 6,
783 	GPIO8A3_MASK		= 3,
784 	GPIO8A3_GPIO		= 0,
785 	GPIO8A3_SPI2_CSN1,
786 	GPIO8A3_SC_IOT1,
787 
788 	GPIO8A2_SHIFT		= 4,
789 	GPIO8A2_MASK		= 1,
790 	GPIO8A2_GPIO		= 0,
791 	GPIO8A2_SC_DETECTT1,
792 
793 	GPIO8A1_SHIFT		= 2,
794 	GPIO8A1_MASK		= 3,
795 	GPIO8A1_GPIO		= 0,
796 	GPIO8A1_PS2_DATA,
797 	GPIO8A1_SC_VCC33V,
798 
799 	GPIO8A0_SHIFT		= 0,
800 	GPIO8A0_MASK		= 3,
801 	GPIO8A0_GPIO		= 0,
802 	GPIO8A0_PS2_CLK,
803 	GPIO8A0_SC_VCC18V,
804 };
805 
806 /* GRF_GPIO8B_IOMUX */
807 enum {
808 	GPIO8B1_SHIFT		= 2,
809 	GPIO8B1_MASK		= 3,
810 	GPIO8B1_GPIO		= 0,
811 	GPIO8B1_SPI2_TXD,
812 	GPIO8B1_SC_CLK,
813 
814 	GPIO8B0_SHIFT		= 0,
815 	GPIO8B0_MASK		= 3,
816 	GPIO8B0_GPIO		= 0,
817 	GPIO8B0_SPI2_RXD,
818 	GPIO8B0_SC_RST,
819 };
820 
821 /* GRF_SOC_CON0 */
822 enum {
823 	PAUSE_MMC_PERI_SHIFT	= 0xf,
824 	PAUSE_MMC_PERI_MASK	= 1,
825 
826 	PAUSE_EMEM_PERI_SHIFT	= 0xe,
827 	PAUSE_EMEM_PERI_MASK	= 1,
828 
829 	PAUSE_USB_PERI_SHIFT	= 0xd,
830 	PAUSE_USB_PERI_MASK	= 1,
831 
832 	GRF_FORCE_JTAG_SHIFT	= 0xc,
833 	GRF_FORCE_JTAG_MASK	= 1,
834 
835 	GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
836 	GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
837 
838 	GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
839 	GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
840 
841 	DDR1_16BIT_EN_SHIFT	= 9,
842 	DDR1_16BIT_EN_MASK	= 1,
843 
844 	DDR0_16BIT_EN_SHIFT	= 8,
845 	DDR0_16BIT_EN_MASK	= 1,
846 
847 	VCODEC_SHIFT		= 7,
848 	VCODEC_MASK		= 1,
849 	VCODEC_SELECT_VEPU_ACLK	= 0,
850 	VCODEC_SELECT_VDPU_ACLK,
851 
852 	UPCTL1_C_ACTIVE_IN_SHIFT = 6,
853 	UPCTL1_C_ACTIVE_IN_MASK	= 1,
854 	UPCTL1_C_ACTIVE_IN_MAY	= 0,
855 	UPCTL1_C_ACTIVE_IN_WILL,
856 
857 	UPCTL0_C_ACTIVE_IN_SHIFT = 5,
858 	UPCTL0_C_ACTIVE_IN_MASK	= 1,
859 	UPCTL0_C_ACTIVE_IN_MAY	= 0,
860 	UPCTL0_C_ACTIVE_IN_WILL,
861 
862 	MSCH1_MAINDDR3_SHIFT	= 4,
863 	MSCH1_MAINDDR3_MASK	= 1,
864 	MSCH1_MAINDDR3_DDR3	= 1,
865 
866 	MSCH0_MAINDDR3_SHIFT	= 3,
867 	MSCH0_MAINDDR3_MASK	= 1,
868 	MSCH0_MAINDDR3_DDR3	= 1,
869 
870 	MSCH1_MAINPARTIALPOP_SHIFT = 2,
871 	MSCH1_MAINPARTIALPOP_MASK = 1,
872 
873 	MSCH0_MAINPARTIALPOP_SHIFT = 1,
874 	MSCH0_MAINPARTIALPOP_MASK = 1,
875 };
876 
877 /* GRF_SOC_CON1 */
878 enum {
879 	RK3288_RMII_MODE_SHIFT = 14,
880 	RK3288_RMII_MODE_MASK  = (1 << RK3288_RMII_MODE_SHIFT),
881 	RK3288_RMII_MODE       = (1 << RK3288_RMII_MODE_SHIFT),
882 
883 	RK3288_GMAC_CLK_SEL_SHIFT = 12,
884 	RK3288_GMAC_CLK_SEL_MASK  = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
885 	RK3288_GMAC_CLK_SEL_125M  = (0 << RK3288_GMAC_CLK_SEL_SHIFT),
886 	RK3288_GMAC_CLK_SEL_25M   = (3 << RK3288_GMAC_CLK_SEL_SHIFT),
887 	RK3288_GMAC_CLK_SEL_2_5M  = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
888 
889 	RK3288_RMII_CLK_SEL_SHIFT = 11,
890 	RK3288_RMII_CLK_SEL_MASK  = (1 << RK3288_RMII_CLK_SEL_SHIFT),
891 	RK3288_RMII_CLK_SEL_2_5M  = (0 << RK3288_RMII_CLK_SEL_SHIFT),
892 	RK3288_RMII_CLK_SEL_25M   = (1 << RK3288_RMII_CLK_SEL_SHIFT),
893 
894 	GMAC_SPEED_SHIFT	= 0xa,
895 	GMAC_SPEED_MASK		= 1,
896 	GMAC_SPEED_10M		= 0,
897 	GMAC_SPEED_100M,
898 
899 	GMAC_FLOWCTRL_SHIFT	= 0x9,
900 	GMAC_FLOWCTRL_MASK	= 1,
901 
902 	RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,
903 	RK3288_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
904 	RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
905 	RK3288_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
906 
907 	HOST_REMAP_SHIFT	= 0x5,
908 	HOST_REMAP_MASK		= 1
909 };
910 
911 /* GRF_SOC_CON2 */
912 enum {
913 	UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
914 	UPCTL1_LPDDR3_ODT_EN_MASK = 1,
915 	UPCTL1_LPDDR3_ODT_EN_ODT = 1,
916 
917 	UPCTL1_BST_DIABLE_SHIFT	= 0xc,
918 	UPCTL1_BST_DIABLE_MASK	= 1,
919 	UPCTL1_BST_DIABLE_DISABLE = 1,
920 
921 	LPDDR3_EN1_SHIFT	= 0xb,
922 	LPDDR3_EN1_MASK		= 1,
923 	LPDDR3_EN1_LPDDR3	= 1,
924 
925 	UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
926 	UPCTL0_LPDDR3_ODT_EN_MASK = 1,
927 	UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
928 
929 	UPCTL0_BST_DIABLE_SHIFT	= 9,
930 	UPCTL0_BST_DIABLE_MASK	= 1,
931 	UPCTL0_BST_DIABLE_DISABLE = 1,
932 
933 	LPDDR3_EN0_SHIFT	= 8,
934 	LPDDR3_EN0_MASK		= 1,
935 	LPDDR3_EN0_LPDDR3	= 1,
936 
937 	GRF_POC_FLASH0_CTRL_SHIFT = 7,
938 	GRF_POC_FLASH0_CTRL_MASK = 1,
939 	GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
940 	GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
941 
942 	SIMCARD_MUX_SHIFT	= 6,
943 	SIMCARD_MUX_MASK	= 1,
944 	SIMCARD_MUX_USE_A	= 1,
945 	SIMCARD_MUX_USE_B	= 0,
946 
947 	GRF_SPDIF_2CH_EN_SHIFT	= 1,
948 	GRF_SPDIF_2CH_EN_MASK	= 1,
949 	GRF_SPDIF_2CH_EN_8CH	= 0,
950 	GRF_SPDIF_2CH_EN_2CH,
951 
952 	PWM_SHIFT		= 0,
953 	PWM_MASK		= 1,
954 	PWM_RK			= 1,
955 	PWM_PWM			= 0,
956 };
957 
958 /* GRF_SOC_CON3 */
959 enum {
960 	RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf,
961 	RK3288_RXCLK_DLY_ENA_GMAC_MASK =
962 		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
963 	RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
964 	RK3288_RXCLK_DLY_ENA_GMAC_ENABLE =
965 		(1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT),
966 
967 	RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe,
968 	RK3288_TXCLK_DLY_ENA_GMAC_MASK =
969 		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
970 	RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
971 	RK3288_TXCLK_DLY_ENA_GMAC_ENABLE =
972 		(1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT),
973 
974 	RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
975 	RK3288_CLK_RX_DL_CFG_GMAC_MASK =
976 		(0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT),
977 
978 	RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
979 	RK3288_CLK_TX_DL_CFG_GMAC_MASK =
980 		(0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT),
981 };
982 
983 /* GRF_SOC_CON6 */
984 enum GRF_SOC_CON6 {
985 	RK3288_HDMI_EDP_SEL_SHIFT = 0xf,
986 	RK3288_HDMI_EDP_SEL_MASK =
987 		1 << RK3288_HDMI_EDP_SEL_SHIFT,
988 	RK3288_HDMI_EDP_SEL_EDP = 0,
989 	RK3288_HDMI_EDP_SEL_HDMI,
990 
991 	RK3288_DSI0_DPICOLORM_SHIFT = 0x8,
992 	RK3288_DSI0_DPICOLORM_MASK =
993 		1 << RK3288_DSI0_DPICOLORM_SHIFT,
994 
995 	RK3288_DSI0_DPISHUTDN_SHIFT = 0x7,
996 	RK3288_DSI0_DPISHUTDN_MASK =
997 		1 << RK3288_DSI0_DPISHUTDN_SHIFT,
998 
999 	RK3288_DSI0_LCDC_SEL_SHIFT = 0x6,
1000 	RK3288_DSI0_LCDC_SEL_MASK =
1001 		1 << RK3288_DSI0_LCDC_SEL_SHIFT,
1002 	RK3288_DSI0_LCDC_SEL_BIG = 0,
1003 	RK3288_DSI0_LCDC_SEL_LIT = 1,
1004 
1005 	RK3288_EDP_LCDC_SEL_SHIFT = 0x5,
1006 	RK3288_EDP_LCDC_SEL_MASK =
1007 		1 << RK3288_EDP_LCDC_SEL_SHIFT,
1008 	RK3288_EDP_LCDC_SEL_BIG = 0,
1009 	RK3288_EDP_LCDC_SEL_LIT = 1,
1010 
1011 	RK3288_HDMI_LCDC_SEL_SHIFT = 0x4,
1012 	RK3288_HDMI_LCDC_SEL_MASK =
1013 		1 << RK3288_HDMI_LCDC_SEL_SHIFT,
1014 	RK3288_HDMI_LCDC_SEL_BIG = 0,
1015 	RK3288_HDMI_LCDC_SEL_LIT = 1,
1016 
1017 	RK3288_LVDS_LCDC_SEL_SHIFT = 0x3,
1018 	RK3288_LVDS_LCDC_SEL_MASK =
1019 		1 << RK3288_LVDS_LCDC_SEL_SHIFT,
1020 	RK3288_LVDS_LCDC_SEL_BIG = 0,
1021 	RK3288_LVDS_LCDC_SEL_LIT = 1,
1022 };
1023 
1024 /* RK3288_SOC_CON8 */
1025 enum GRF_SOC_CON8 {
1026 	RK3288_DPHY_TX0_RXMODE_SHIFT = 4,
1027 	RK3288_DPHY_TX0_RXMODE_MASK =
1028 	   0xf << RK3288_DPHY_TX0_RXMODE_SHIFT,
1029 	RK3288_DPHY_TX0_RXMODE_EN = 0xf,
1030 	RK3288_DPHY_TX0_RXMODE_DIS = 0,
1031 
1032 	RK3288_DPHY_TX0_TXSTOPMODE_SHIFT = 0x8,
1033 	RK3288_DPHY_TX0_TXSTOPMODE_MASK =
1034 	   0xf << RK3288_DPHY_TX0_TXSTOPMODE_SHIFT,
1035 	RK3288_DPHY_TX0_TXSTOPMODE_EN = 0xf,
1036 	RK3288_DPHY_TX0_TXSTOPMODE_DIS = 0,
1037 
1038 	RK3288_DPHY_TX0_TURNREQUEST_SHIFT = 0,
1039 	RK3288_DPHY_TX0_TURNREQUEST_MASK =
1040 	   0xf << RK3288_DPHY_TX0_TURNREQUEST_SHIFT,
1041 	RK3288_DPHY_TX0_TURNREQUEST_EN = 0xf,
1042 	RK3288_DPHY_TX0_TURNREQUEST_DIS = 0,
1043 };
1044 
1045 /* GPIO Bias settings */
1046 enum GPIO_BIAS {
1047 	GPIO_BIAS_2MA = 0,
1048 	GPIO_BIAS_4MA,
1049 	GPIO_BIAS_8MA,
1050 	GPIO_BIAS_12MA,
1051 };
1052 
1053 #define GPIO_BIAS_MASK	0x3
1054 #define GPIO_BIAS_SHIFT(x)  ((x) * 2)
1055 
1056 enum GPIO_PU_PD {
1057 	GPIO_PULL_NORMAL = 0,
1058 	GPIO_PULL_UP,
1059 	GPIO_PULL_DOWN,
1060 	GPIO_PULL_REPEAT,
1061 };
1062 
1063 #define GPIO_PULL_MASK	0x3
1064 #define GPIO_PULL_SHIFT(x)  ((x) * 2)
1065 
1066 #endif
1067