1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SPI Flash ID's. 4 * 5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 7 */ 8 9 #include <common.h> 10 #include <spi.h> 11 #include <spi_flash.h> 12 13 #include "sf_internal.h" 14 15 /* Used when the "_ext_id" is two bytes at most */ 16 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 17 .id = { \ 18 ((_jedec_id) >> 16) & 0xff, \ 19 ((_jedec_id) >> 8) & 0xff, \ 20 (_jedec_id) & 0xff, \ 21 ((_ext_id) >> 8) & 0xff, \ 22 (_ext_id) & 0xff, \ 23 }, \ 24 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 25 .sector_size = (_sector_size), \ 26 .n_sectors = (_n_sectors), \ 27 .page_size = 256, \ 28 .flags = (_flags), 29 30 #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 31 .id = { \ 32 ((_jedec_id) >> 16) & 0xff, \ 33 ((_jedec_id) >> 8) & 0xff, \ 34 (_jedec_id) & 0xff, \ 35 ((_ext_id) >> 16) & 0xff, \ 36 ((_ext_id) >> 8) & 0xff, \ 37 (_ext_id) & 0xff, \ 38 }, \ 39 .id_len = 6, \ 40 .sector_size = (_sector_size), \ 41 .n_sectors = (_n_sectors), \ 42 .page_size = 256, \ 43 .flags = (_flags), 44 45 const struct spi_flash_info spi_flash_ids[] = { 46 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 47 {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, 48 {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, 49 {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, 50 {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, 51 {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, 52 {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, 53 {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, 54 {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, 55 {"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, 56 {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, 57 #endif 58 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 59 {"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, 60 {"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, 61 {"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, 62 {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, 63 #endif 64 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 65 {"gd25q16c", INFO(0xc84015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, 66 {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, 67 {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, 68 {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, 69 #endif 70 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 71 {"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) }, 72 {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, 73 {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, 74 {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, 75 {"is25lp256", INFO(0x9d6019, 0x0, 64 * 1024, 512, 0) }, 76 {"is25wp032", INFO(0x9d7016, 0x0, 64 * 1024, 64, RD_FULL | SECT_4K) }, 77 {"is25wp064", INFO(0x9d7017, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, 78 {"is25wp128", INFO(0x9d7018, 0x0, 64 * 1024, 256, RD_FULL | SECT_4K) }, 79 #endif 80 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 81 {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, 82 {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, 83 {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, 84 {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, 85 {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, 86 {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, 87 {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, 88 {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, 89 {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, 90 {"mx25l1633e", INFO(0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, 91 {"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, 92 {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, 93 {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, 94 {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, 95 {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, 96 {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, 97 #endif 98 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 99 {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, 100 {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, 101 {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, 102 {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, 103 {"s25fl208k", INFO(0x014014, 0x0, 64 * 1024, 16, 0) }, 104 {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) }, 105 {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, 106 {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, 107 {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, 108 {"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, 109 {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, 110 {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, 111 {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, 112 {"s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) }, 113 {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, 114 {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, 115 {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, 116 {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, 117 {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, 118 {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, 119 {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, 120 #endif 121 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 122 {"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, 123 {"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, 124 {"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, 125 {"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, 126 {"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, 127 {"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, 128 {"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, 129 {"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, 130 {"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, 131 {"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, 132 {"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, 133 {"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, 134 {"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, 135 {"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, 136 {"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, 137 {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, 138 {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, 139 {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, 140 {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 141 {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 142 {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 143 {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 144 {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 145 {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 146 {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 147 {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, 148 {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, 149 #endif 150 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 151 {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, 152 {"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, 153 {"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, 154 {"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, 155 {"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, 156 {"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, 157 {"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, 158 {"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, 159 {"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, 160 {"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, 161 {"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, 162 {"sst26wf016", INFO(0xbf2651, 0x0, 64 * 1024, 32, SECT_4K) }, 163 {"sst26wf032", INFO(0xbf2622, 0x0, 64 * 1024, 64, SECT_4K) }, 164 {"sst26wf064", INFO(0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) }, 165 #endif 166 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 167 {"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, 168 {"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, 169 {"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, 170 {"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, 171 {"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, 172 {"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, 173 {"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, 174 {"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, 175 {"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, 176 {"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, 177 {"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, 178 {"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, 179 {"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, 180 {"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, 181 {"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, 182 {"w25q16jv", INFO(0xef7015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, 183 {"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, 184 {"w25q32jv", INFO(0xef7016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, 185 {"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, 186 {"w25q64jv", INFO(0xef7017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, 187 {"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, 188 {"w25q128jv", INFO(0xef7018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, 189 {"w25q256fw", INFO(0xef6019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, 190 {"w25q256jw", INFO(0xef7019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, 191 #endif 192 #ifdef CONFIG_SPI_FLASH_XMC /* Wuhan Xinxin Semiconductor Manufacturing Corp */ 193 { "xm25qh64a", INFO(0x207017, 0x0, 64 * 1024, 128, SECT_4K | RD_DUAL | RD_QUAD) }, 194 { "xm25qh128a", INFO(0x207018, 0x0, 64 * 1024, 256, SECT_4K | RD_DUAL | RD_QUAD) }, 195 #endif 196 {}, /* Empty entry to terminate the list */ 197 /* 198 * Note: 199 * Below paired flash devices has similar spi_flash params. 200 * (s25fl129p_64k, s25fl128s_64k) 201 * (w25q80bl, w25q80bv) 202 * (w25q16cl, w25q16dv, w25q16jv) 203 * (w25q32bv, w25q32fv_spi) 204 * (w25q64cv, w25q64fv_spi) 205 * (w25q128bv, w25q128fv_spi) 206 * (w25q32dw, w25q32fv_qpi) 207 * (w25q64dw, w25q64fv_qpi) 208 * (w25q128fw, w25q128fv_qpi) 209 * (w25q256fw, w25q256fv_qpi) 210 */ 211 }; 212