1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu/int128.h"
24 #include "exec/cpu-defs.h"
25 #include "cpu-qom.h"
26
27 #define TCG_GUEST_DEFAULT_MO 0
28
29 #define TARGET_PAGE_BITS_64K 16
30 #define TARGET_PAGE_BITS_16M 24
31
32 #if defined(TARGET_PPC64)
33 #define PPC_ELF_MACHINE EM_PPC64
34 #else
35 #define PPC_ELF_MACHINE EM_PPC
36 #endif
37
38 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
39 #define PPC_BIT32(bit) (0x80000000 >> (bit))
40 #define PPC_BIT8(bit) (0x80 >> (bit))
41 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
42 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
43 PPC_BIT32(bs))
44 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
45
46 /*****************************************************************************/
47 /* Exception vectors definitions */
48 enum {
49 POWERPC_EXCP_NONE = -1,
50 /* The 64 first entries are used by the PowerPC embedded specification */
51 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
52 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
53 POWERPC_EXCP_DSI = 2, /* Data storage exception */
54 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
55 POWERPC_EXCP_EXTERNAL = 4, /* External input */
56 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
57 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
58 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
59 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
60 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
61 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
62 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
63 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
64 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
65 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
66 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
67 /* Vectors 16 to 31 are reserved */
68 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
69 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
70 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
71 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
72 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
73 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
74 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
75 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
76 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
77 /* Vectors 42 to 63 are reserved */
78 /* Exceptions defined in the PowerPC server specification */
79 POWERPC_EXCP_RESET = 64, /* System reset exception */
80 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
81 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
82 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
83 POWERPC_EXCP_TRACE = 68, /* Trace exception */
84 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
85 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
86 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
87 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
88 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
89 /* 40x specific exceptions */
90 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
91 /* 601 specific exceptions */
92 POWERPC_EXCP_IO = 75, /* IO error exception */
93 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
94 /* 602 specific exceptions */
95 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
96 /* 602/603 specific exceptions */
97 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
98 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
99 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
100 /* Exceptions available on most PowerPC */
101 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
102 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
103 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
104 POWERPC_EXCP_SMI = 84, /* System management interrupt */
105 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
106 /* 7xx/74xx specific exceptions */
107 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
108 /* 74xx specific exceptions */
109 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
110 /* 970FX specific exceptions */
111 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
112 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
113 /* Freescale embedded cores specific exceptions */
114 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
115 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
116 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
117 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
118 /* VSX Unavailable (Power ISA 2.06 and later) */
119 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
120 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
121 /* Additional ISA 2.06 and later server exceptions */
122 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
123 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
124 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
125 /* Server doorbell variants */
126 POWERPC_EXCP_SDOOR = 99,
127 POWERPC_EXCP_SDOOR_HV = 100,
128 /* ISA 3.00 additions */
129 POWERPC_EXCP_HVIRT = 101,
130 /* EOL */
131 POWERPC_EXCP_NB = 102,
132 /* QEMU exceptions: used internally during code translation */
133 POWERPC_EXCP_STOP = 0x200, /* stop translation */
134 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
135 /* QEMU exceptions: special cases we want to stop translation */
136 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
137 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
138 };
139
140 /* Exceptions error codes */
141 enum {
142 /* Exception subtypes for POWERPC_EXCP_ALIGN */
143 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
144 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
145 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
146 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
147 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
148 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
149 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
150 /* FP exceptions */
151 POWERPC_EXCP_FP = 0x10,
152 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
153 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
154 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
155 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
156 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
157 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
158 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
159 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
160 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
161 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
162 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
163 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
164 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
165 /* Invalid instruction */
166 POWERPC_EXCP_INVAL = 0x20,
167 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
168 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
169 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
170 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
171 /* Privileged instruction */
172 POWERPC_EXCP_PRIV = 0x30,
173 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
174 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
175 /* Trap */
176 POWERPC_EXCP_TRAP = 0x40,
177 };
178
179 #define PPC_INPUT(env) ((env)->bus_model)
180
181 /*****************************************************************************/
182 typedef struct opc_handler_t opc_handler_t;
183
184 /*****************************************************************************/
185 /* Types used to describe some PowerPC registers etc. */
186 typedef struct DisasContext DisasContext;
187 typedef struct ppc_spr_t ppc_spr_t;
188 typedef union ppc_tlb_t ppc_tlb_t;
189 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
190
191 /* SPR access micro-ops generations callbacks */
192 struct ppc_spr_t {
193 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
194 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
195 #if !defined(CONFIG_USER_ONLY)
196 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
197 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
198 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
199 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
200 unsigned int gdb_id;
201 #endif
202 const char *name;
203 target_ulong default_value;
204 #ifdef CONFIG_KVM
205 /*
206 * We (ab)use the fact that all the SPRs will have ids for the
207 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
208 * don't sync this
209 */
210 uint64_t one_reg_id;
211 #endif
212 };
213
214 /* VSX/Altivec registers (128 bits) */
215 typedef union _ppc_vsr_t {
216 uint8_t u8[16];
217 uint16_t u16[8];
218 uint32_t u32[4];
219 uint64_t u64[2];
220 int8_t s8[16];
221 int16_t s16[8];
222 int32_t s32[4];
223 int64_t s64[2];
224 float32 f32[4];
225 float64 f64[2];
226 float128 f128;
227 #ifdef CONFIG_INT128
228 __uint128_t u128;
229 #endif
230 Int128 s128;
231 } ppc_vsr_t;
232
233 typedef ppc_vsr_t ppc_avr_t;
234 typedef ppc_vsr_t ppc_fprp_t;
235
236 #if !defined(CONFIG_USER_ONLY)
237 /* Software TLB cache */
238 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
239 struct ppc6xx_tlb_t {
240 target_ulong pte0;
241 target_ulong pte1;
242 target_ulong EPN;
243 };
244
245 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
246 struct ppcemb_tlb_t {
247 uint64_t RPN;
248 target_ulong EPN;
249 target_ulong PID;
250 target_ulong size;
251 uint32_t prot;
252 uint32_t attr; /* Storage attributes */
253 };
254
255 typedef struct ppcmas_tlb_t {
256 uint32_t mas8;
257 uint32_t mas1;
258 uint64_t mas2;
259 uint64_t mas7_3;
260 } ppcmas_tlb_t;
261
262 union ppc_tlb_t {
263 ppc6xx_tlb_t *tlb6;
264 ppcemb_tlb_t *tlbe;
265 ppcmas_tlb_t *tlbm;
266 };
267
268 /* possible TLB variants */
269 #define TLB_NONE 0
270 #define TLB_6XX 1
271 #define TLB_EMB 2
272 #define TLB_MAS 3
273 #endif
274
275 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
276
277 typedef struct ppc_slb_t ppc_slb_t;
278 struct ppc_slb_t {
279 uint64_t esid;
280 uint64_t vsid;
281 const PPCHash64SegmentPageSizes *sps;
282 };
283
284 #define MAX_SLB_ENTRIES 64
285 #define SEGMENT_SHIFT_256M 28
286 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
287
288 #define SEGMENT_SHIFT_1T 40
289 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
290
291 typedef struct ppc_v3_pate_t {
292 uint64_t dw0;
293 uint64_t dw1;
294 } ppc_v3_pate_t;
295
296 /*****************************************************************************/
297 /* Machine state register bits definition */
298 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
299 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
300 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
301 #define MSR_HV 60 /* hypervisor state hflags */
302 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
303 #define MSR_TS1 33
304 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
305 #define MSR_CM 31 /* Computation mode for BookE hflags */
306 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
307 #define MSR_GS 28 /* guest state for BookE */
308 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
309 #define MSR_VR 25 /* altivec available x hflags */
310 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
311 #define MSR_AP 23 /* Access privilege state on 602 hflags */
312 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
313 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
314 #define MSR_KEY 19 /* key bit on 603e */
315 #define MSR_POW 18 /* Power management */
316 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
317 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
318 #define MSR_ILE 16 /* Interrupt little-endian mode */
319 #define MSR_EE 15 /* External interrupt enable */
320 #define MSR_PR 14 /* Problem state hflags */
321 #define MSR_FP 13 /* Floating point available hflags */
322 #define MSR_ME 12 /* Machine check interrupt enable */
323 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
324 #define MSR_SE 10 /* Single-step trace enable x hflags */
325 #define MSR_DWE 10 /* Debug wait enable on 405 x */
326 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
327 #define MSR_BE 9 /* Branch trace enable x hflags */
328 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
329 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
330 #define MSR_AL 7 /* AL bit on POWER */
331 #define MSR_EP 6 /* Exception prefix on 601 */
332 #define MSR_IR 5 /* Instruction relocate */
333 #define MSR_DR 4 /* Data relocate */
334 #define MSR_IS 5 /* Instruction address space (BookE) */
335 #define MSR_DS 4 /* Data address space (BookE) */
336 #define MSR_PE 3 /* Protection enable on 403 */
337 #define MSR_PX 2 /* Protection exclusive on 403 x */
338 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
339 #define MSR_RI 1 /* Recoverable interrupt 1 */
340 #define MSR_LE 0 /* Little-endian mode 1 hflags */
341
342 /* LPCR bits */
343 #define LPCR_VPM0 PPC_BIT(0)
344 #define LPCR_VPM1 PPC_BIT(1)
345 #define LPCR_ISL PPC_BIT(2)
346 #define LPCR_KBV PPC_BIT(3)
347 #define LPCR_DPFD_SHIFT (63 - 11)
348 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
349 #define LPCR_VRMASD_SHIFT (63 - 16)
350 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
351 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
352 #define LPCR_PECE_U_SHIFT (63 - 19)
353 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
354 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
355 #define LPCR_RMLS_SHIFT (63 - 37)
356 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
357 #define LPCR_ILE PPC_BIT(38)
358 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
359 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
360 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
361 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
362 #define LPCR_HR PPC_BIT(43) /* Host Radix */
363 #define LPCR_ONL PPC_BIT(45)
364 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
365 #define LPCR_P7_PECE0 PPC_BIT(49)
366 #define LPCR_P7_PECE1 PPC_BIT(50)
367 #define LPCR_P7_PECE2 PPC_BIT(51)
368 #define LPCR_P8_PECE0 PPC_BIT(47)
369 #define LPCR_P8_PECE1 PPC_BIT(48)
370 #define LPCR_P8_PECE2 PPC_BIT(49)
371 #define LPCR_P8_PECE3 PPC_BIT(50)
372 #define LPCR_P8_PECE4 PPC_BIT(51)
373 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
374 #define LPCR_PECE_L_SHIFT (63 - 51)
375 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
376 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
377 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
378 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
379 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
380 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
381 #define LPCR_MER PPC_BIT(52)
382 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
383 #define LPCR_TC PPC_BIT(54)
384 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
385 #define LPCR_LPES0 PPC_BIT(60)
386 #define LPCR_LPES1 PPC_BIT(61)
387 #define LPCR_RMI PPC_BIT(62)
388 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
389 #define LPCR_HDICE PPC_BIT(63)
390
391 /* PSSCR bits */
392 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
393 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
394
395 /* HFSCR bits */
396 #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
397 #define HFSCR_IC_MSGP 0xA
398
399 #define msr_sf ((env->msr >> MSR_SF) & 1)
400 #define msr_isf ((env->msr >> MSR_ISF) & 1)
401 #if defined(TARGET_PPC64)
402 #define msr_hv ((env->msr >> MSR_HV) & 1)
403 #else
404 #define msr_hv (0)
405 #endif
406 #define msr_cm ((env->msr >> MSR_CM) & 1)
407 #define msr_icm ((env->msr >> MSR_ICM) & 1)
408 #define msr_gs ((env->msr >> MSR_GS) & 1)
409 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
410 #define msr_vr ((env->msr >> MSR_VR) & 1)
411 #define msr_spe ((env->msr >> MSR_SPE) & 1)
412 #define msr_ap ((env->msr >> MSR_AP) & 1)
413 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
414 #define msr_sa ((env->msr >> MSR_SA) & 1)
415 #define msr_key ((env->msr >> MSR_KEY) & 1)
416 #define msr_pow ((env->msr >> MSR_POW) & 1)
417 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
418 #define msr_ce ((env->msr >> MSR_CE) & 1)
419 #define msr_ile ((env->msr >> MSR_ILE) & 1)
420 #define msr_ee ((env->msr >> MSR_EE) & 1)
421 #define msr_pr ((env->msr >> MSR_PR) & 1)
422 #define msr_fp ((env->msr >> MSR_FP) & 1)
423 #define msr_me ((env->msr >> MSR_ME) & 1)
424 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
425 #define msr_se ((env->msr >> MSR_SE) & 1)
426 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
427 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
428 #define msr_be ((env->msr >> MSR_BE) & 1)
429 #define msr_de ((env->msr >> MSR_DE) & 1)
430 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
431 #define msr_al ((env->msr >> MSR_AL) & 1)
432 #define msr_ep ((env->msr >> MSR_EP) & 1)
433 #define msr_ir ((env->msr >> MSR_IR) & 1)
434 #define msr_dr ((env->msr >> MSR_DR) & 1)
435 #define msr_is ((env->msr >> MSR_IS) & 1)
436 #define msr_ds ((env->msr >> MSR_DS) & 1)
437 #define msr_pe ((env->msr >> MSR_PE) & 1)
438 #define msr_px ((env->msr >> MSR_PX) & 1)
439 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
440 #define msr_ri ((env->msr >> MSR_RI) & 1)
441 #define msr_le ((env->msr >> MSR_LE) & 1)
442 #define msr_ts ((env->msr >> MSR_TS1) & 3)
443 #define msr_tm ((env->msr >> MSR_TM) & 1)
444
445 #define DBCR0_ICMP (1 << 27)
446 #define DBCR0_BRT (1 << 26)
447 #define DBSR_ICMP (1 << 27)
448 #define DBSR_BRT (1 << 26)
449
450 /* Hypervisor bit is more specific */
451 #if defined(TARGET_PPC64)
452 #define MSR_HVB (1ULL << MSR_HV)
453 #else
454 #define MSR_HVB (0ULL)
455 #endif
456
457 /* DSISR */
458 #define DSISR_NOPTE 0x40000000
459 /* Not permitted by access authority of encoded access authority */
460 #define DSISR_PROTFAULT 0x08000000
461 #define DSISR_ISSTORE 0x02000000
462 /* Not permitted by virtual page class key protection */
463 #define DSISR_AMR 0x00200000
464 /* Unsupported Radix Tree Configuration */
465 #define DSISR_R_BADCONFIG 0x00080000
466
467 /* SRR1 error code fields */
468
469 #define SRR1_NOPTE DSISR_NOPTE
470 /* Not permitted due to no-execute or guard bit set */
471 #define SRR1_NOEXEC_GUARD 0x10000000
472 #define SRR1_PROTFAULT DSISR_PROTFAULT
473 #define SRR1_IAMR DSISR_AMR
474
475 /* Facility Status and Control (FSCR) bits */
476 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
477 #define FSCR_TAR (63 - 55) /* Target Address Register */
478 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
479 #define FSCR_IC_MASK (0xFFULL)
480 #define FSCR_IC_POS (63 - 7)
481 #define FSCR_IC_DSCR_SPR3 2
482 #define FSCR_IC_PMU 3
483 #define FSCR_IC_BHRB 4
484 #define FSCR_IC_TM 5
485 #define FSCR_IC_EBB 7
486 #define FSCR_IC_TAR 8
487
488 /* Exception state register bits definition */
489 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
490 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
491 #define ESR_PTR PPC_BIT(38) /* Trap */
492 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
493 #define ESR_ST PPC_BIT(40) /* Store Operation */
494 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
495 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
496 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
497 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
498 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
499 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
500 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
501 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
502 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
503 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
504 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
505
506 /* Transaction EXception And Summary Register bits */
507 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
508 #define TEXASR_DISALLOWED (63 - 8)
509 #define TEXASR_NESTING_OVERFLOW (63 - 9)
510 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
511 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
512 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
513 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
514 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
515 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
516 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
517 #define TEXASR_ABORT (63 - 31)
518 #define TEXASR_SUSPENDED (63 - 32)
519 #define TEXASR_PRIVILEGE_HV (63 - 34)
520 #define TEXASR_PRIVILEGE_PR (63 - 35)
521 #define TEXASR_FAILURE_SUMMARY (63 - 36)
522 #define TEXASR_TFIAR_EXACT (63 - 37)
523 #define TEXASR_ROT (63 - 38)
524 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
525
526 enum {
527 POWERPC_FLAG_NONE = 0x00000000,
528 /* Flag for MSR bit 25 signification (VRE/SPE) */
529 POWERPC_FLAG_SPE = 0x00000001,
530 POWERPC_FLAG_VRE = 0x00000002,
531 /* Flag for MSR bit 17 signification (TGPR/CE) */
532 POWERPC_FLAG_TGPR = 0x00000004,
533 POWERPC_FLAG_CE = 0x00000008,
534 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
535 POWERPC_FLAG_SE = 0x00000010,
536 POWERPC_FLAG_DWE = 0x00000020,
537 POWERPC_FLAG_UBLE = 0x00000040,
538 /* Flag for MSR bit 9 signification (BE/DE) */
539 POWERPC_FLAG_BE = 0x00000080,
540 POWERPC_FLAG_DE = 0x00000100,
541 /* Flag for MSR bit 2 signification (PX/PMM) */
542 POWERPC_FLAG_PX = 0x00000200,
543 POWERPC_FLAG_PMM = 0x00000400,
544 /* Flag for special features */
545 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
546 POWERPC_FLAG_RTC_CLK = 0x00010000,
547 POWERPC_FLAG_BUS_CLK = 0x00020000,
548 /* Has CFAR */
549 POWERPC_FLAG_CFAR = 0x00040000,
550 /* Has VSX */
551 POWERPC_FLAG_VSX = 0x00080000,
552 /* Has Transaction Memory (ISA 2.07) */
553 POWERPC_FLAG_TM = 0x00100000,
554 };
555
556 /*****************************************************************************/
557 /* Floating point status and control register */
558 #define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
559 #define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
560 #define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
561 #define FPSCR_FX 31 /* Floating-point exception summary */
562 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
563 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
564 #define FPSCR_OX 28 /* Floating-point overflow exception */
565 #define FPSCR_UX 27 /* Floating-point underflow exception */
566 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
567 #define FPSCR_XX 25 /* Floating-point inexact exception */
568 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
569 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
570 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
571 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
572 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
573 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
574 #define FPSCR_FR 18 /* Floating-point fraction rounded */
575 #define FPSCR_FI 17 /* Floating-point fraction inexact */
576 #define FPSCR_C 16 /* Floating-point result class descriptor */
577 #define FPSCR_FL 15 /* Floating-point less than or negative */
578 #define FPSCR_FG 14 /* Floating-point greater than or negative */
579 #define FPSCR_FE 13 /* Floating-point equal or zero */
580 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
581 #define FPSCR_FPCC 12 /* Floating-point condition code */
582 #define FPSCR_FPRF 12 /* Floating-point result flags */
583 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
584 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
585 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
586 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
587 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
588 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
589 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
590 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
591 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
592 #define FPSCR_RN1 1
593 #define FPSCR_RN0 0 /* Floating-point rounding control */
594 #define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
595 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
596 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
597 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
598 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
599 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
600 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
601 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
602 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
603 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
604 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
605 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
606 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
607 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
608 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
609 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
610 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
611 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
612 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
613 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
614 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
615 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
616 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
617 #define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
618 /* Invalid operation exception summary */
619 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
620 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
621 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
622 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
623 (1 << FPSCR_VXCVI)))
624 /* exception summary */
625 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
626 /* enabled exception summary */
627 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
628 0x1F)
629
630 #define FP_DRN2 (1ull << FPSCR_DRN2)
631 #define FP_DRN1 (1ull << FPSCR_DRN1)
632 #define FP_DRN0 (1ull << FPSCR_DRN0)
633 #define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
634 #define FP_FX (1ull << FPSCR_FX)
635 #define FP_FEX (1ull << FPSCR_FEX)
636 #define FP_VX (1ull << FPSCR_VX)
637 #define FP_OX (1ull << FPSCR_OX)
638 #define FP_UX (1ull << FPSCR_UX)
639 #define FP_ZX (1ull << FPSCR_ZX)
640 #define FP_XX (1ull << FPSCR_XX)
641 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
642 #define FP_VXISI (1ull << FPSCR_VXISI)
643 #define FP_VXIDI (1ull << FPSCR_VXIDI)
644 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
645 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
646 #define FP_VXVC (1ull << FPSCR_VXVC)
647 #define FP_FR (1ull << FPSCR_FR)
648 #define FP_FI (1ull << FPSCR_FI)
649 #define FP_C (1ull << FPSCR_C)
650 #define FP_FL (1ull << FPSCR_FL)
651 #define FP_FG (1ull << FPSCR_FG)
652 #define FP_FE (1ull << FPSCR_FE)
653 #define FP_FU (1ull << FPSCR_FU)
654 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
655 #define FP_FPRF (FP_C | FP_FPCC)
656 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
657 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
658 #define FP_VXCVI (1ull << FPSCR_VXCVI)
659 #define FP_VE (1ull << FPSCR_VE)
660 #define FP_OE (1ull << FPSCR_OE)
661 #define FP_UE (1ull << FPSCR_UE)
662 #define FP_ZE (1ull << FPSCR_ZE)
663 #define FP_XE (1ull << FPSCR_XE)
664 #define FP_NI (1ull << FPSCR_NI)
665 #define FP_RN1 (1ull << FPSCR_RN1)
666 #define FP_RN0 (1ull << FPSCR_RN0)
667 #define FP_RN (FP_RN1 | FP_RN0)
668
669 #define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
670 #define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
671
672 /* the exception bits which can be cleared by mcrfs - includes FX */
673 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
674 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
675 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
676 FP_VXSQRT | FP_VXCVI)
677
678 /*****************************************************************************/
679 /* Vector status and control register */
680 #define VSCR_NJ 16 /* Vector non-java */
681 #define VSCR_SAT 0 /* Vector saturation */
682
683 /*****************************************************************************/
684 /* BookE e500 MMU registers */
685
686 #define MAS0_NV_SHIFT 0
687 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
688
689 #define MAS0_WQ_SHIFT 12
690 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
691 /* Write TLB entry regardless of reservation */
692 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
693 /* Write TLB entry only already in use */
694 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
695 /* Clear TLB entry */
696 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
697
698 #define MAS0_HES_SHIFT 14
699 #define MAS0_HES (1 << MAS0_HES_SHIFT)
700
701 #define MAS0_ESEL_SHIFT 16
702 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
703
704 #define MAS0_TLBSEL_SHIFT 28
705 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
706 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
707 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
708 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
709 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
710
711 #define MAS0_ATSEL_SHIFT 31
712 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
713 #define MAS0_ATSEL_TLB 0
714 #define MAS0_ATSEL_LRAT MAS0_ATSEL
715
716 #define MAS1_TSIZE_SHIFT 7
717 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
718
719 #define MAS1_TS_SHIFT 12
720 #define MAS1_TS (1 << MAS1_TS_SHIFT)
721
722 #define MAS1_IND_SHIFT 13
723 #define MAS1_IND (1 << MAS1_IND_SHIFT)
724
725 #define MAS1_TID_SHIFT 16
726 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
727
728 #define MAS1_IPROT_SHIFT 30
729 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
730
731 #define MAS1_VALID_SHIFT 31
732 #define MAS1_VALID 0x80000000
733
734 #define MAS2_EPN_SHIFT 12
735 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
736
737 #define MAS2_ACM_SHIFT 6
738 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
739
740 #define MAS2_VLE_SHIFT 5
741 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
742
743 #define MAS2_W_SHIFT 4
744 #define MAS2_W (1 << MAS2_W_SHIFT)
745
746 #define MAS2_I_SHIFT 3
747 #define MAS2_I (1 << MAS2_I_SHIFT)
748
749 #define MAS2_M_SHIFT 2
750 #define MAS2_M (1 << MAS2_M_SHIFT)
751
752 #define MAS2_G_SHIFT 1
753 #define MAS2_G (1 << MAS2_G_SHIFT)
754
755 #define MAS2_E_SHIFT 0
756 #define MAS2_E (1 << MAS2_E_SHIFT)
757
758 #define MAS3_RPN_SHIFT 12
759 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
760
761 #define MAS3_U0 0x00000200
762 #define MAS3_U1 0x00000100
763 #define MAS3_U2 0x00000080
764 #define MAS3_U3 0x00000040
765 #define MAS3_UX 0x00000020
766 #define MAS3_SX 0x00000010
767 #define MAS3_UW 0x00000008
768 #define MAS3_SW 0x00000004
769 #define MAS3_UR 0x00000002
770 #define MAS3_SR 0x00000001
771 #define MAS3_SPSIZE_SHIFT 1
772 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
773
774 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
775 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
776 #define MAS4_TIDSELD_MASK 0x00030000
777 #define MAS4_TIDSELD_PID0 0x00000000
778 #define MAS4_TIDSELD_PID1 0x00010000
779 #define MAS4_TIDSELD_PID2 0x00020000
780 #define MAS4_TIDSELD_PIDZ 0x00030000
781 #define MAS4_INDD 0x00008000 /* Default IND */
782 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
783 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
784 #define MAS4_ACMD 0x00000040
785 #define MAS4_VLED 0x00000020
786 #define MAS4_WD 0x00000010
787 #define MAS4_ID 0x00000008
788 #define MAS4_MD 0x00000004
789 #define MAS4_GD 0x00000002
790 #define MAS4_ED 0x00000001
791 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
792 #define MAS4_WIMGED_SHIFT 0
793
794 #define MAS5_SGS 0x80000000
795 #define MAS5_SLPID_MASK 0x00000fff
796
797 #define MAS6_SPID0 0x3fff0000
798 #define MAS6_SPID1 0x00007ffe
799 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
800 #define MAS6_SAS 0x00000001
801 #define MAS6_SPID MAS6_SPID0
802 #define MAS6_SIND 0x00000002 /* Indirect page */
803 #define MAS6_SIND_SHIFT 1
804 #define MAS6_SPID_MASK 0x3fff0000
805 #define MAS6_SPID_SHIFT 16
806 #define MAS6_ISIZE_MASK 0x00000f80
807 #define MAS6_ISIZE_SHIFT 7
808
809 #define MAS7_RPN 0xffffffff
810
811 #define MAS8_TGS 0x80000000
812 #define MAS8_VF 0x40000000
813 #define MAS8_TLBPID 0x00000fff
814
815 /* Bit definitions for MMUCFG */
816 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
817 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
818 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
819 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
820 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
821 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
822 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
823 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
824 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
825
826 /* Bit definitions for MMUCSR0 */
827 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
828 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
829 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
830 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
831 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
832 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
833 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
834 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
835 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
836 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
837
838 /* TLBnCFG encoding */
839 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
840 #define TLBnCFG_HES 0x00002000 /* HW select supported */
841 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
842 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
843 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
844 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
845 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
846 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
847 #define TLBnCFG_MINSIZE_SHIFT 20
848 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
849 #define TLBnCFG_MAXSIZE_SHIFT 16
850 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
851 #define TLBnCFG_ASSOC_SHIFT 24
852
853 /* TLBnPS encoding */
854 #define TLBnPS_4K 0x00000004
855 #define TLBnPS_8K 0x00000008
856 #define TLBnPS_16K 0x00000010
857 #define TLBnPS_32K 0x00000020
858 #define TLBnPS_64K 0x00000040
859 #define TLBnPS_128K 0x00000080
860 #define TLBnPS_256K 0x00000100
861 #define TLBnPS_512K 0x00000200
862 #define TLBnPS_1M 0x00000400
863 #define TLBnPS_2M 0x00000800
864 #define TLBnPS_4M 0x00001000
865 #define TLBnPS_8M 0x00002000
866 #define TLBnPS_16M 0x00004000
867 #define TLBnPS_32M 0x00008000
868 #define TLBnPS_64M 0x00010000
869 #define TLBnPS_128M 0x00020000
870 #define TLBnPS_256M 0x00040000
871 #define TLBnPS_512M 0x00080000
872 #define TLBnPS_1G 0x00100000
873 #define TLBnPS_2G 0x00200000
874 #define TLBnPS_4G 0x00400000
875 #define TLBnPS_8G 0x00800000
876 #define TLBnPS_16G 0x01000000
877 #define TLBnPS_32G 0x02000000
878 #define TLBnPS_64G 0x04000000
879 #define TLBnPS_128G 0x08000000
880 #define TLBnPS_256G 0x10000000
881
882 /* tlbilx action encoding */
883 #define TLBILX_T_ALL 0
884 #define TLBILX_T_TID 1
885 #define TLBILX_T_FULLMATCH 3
886 #define TLBILX_T_CLASS0 4
887 #define TLBILX_T_CLASS1 5
888 #define TLBILX_T_CLASS2 6
889 #define TLBILX_T_CLASS3 7
890
891 /* BookE 2.06 helper defines */
892
893 #define BOOKE206_FLUSH_TLB0 (1 << 0)
894 #define BOOKE206_FLUSH_TLB1 (1 << 1)
895 #define BOOKE206_FLUSH_TLB2 (1 << 2)
896 #define BOOKE206_FLUSH_TLB3 (1 << 3)
897
898 /* number of possible TLBs */
899 #define BOOKE206_MAX_TLBN 4
900
901 #define EPID_EPID_SHIFT 0x0
902 #define EPID_EPID 0xFF
903 #define EPID_ELPID_SHIFT 0x10
904 #define EPID_ELPID 0x3F0000
905 #define EPID_EGS 0x20000000
906 #define EPID_EGS_SHIFT 29
907 #define EPID_EAS 0x40000000
908 #define EPID_EAS_SHIFT 30
909 #define EPID_EPR 0x80000000
910 #define EPID_EPR_SHIFT 31
911 /* We don't support EGS and ELPID */
912 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
913
914 /*****************************************************************************/
915 /* Server and Embedded Processor Control */
916
917 #define DBELL_TYPE_SHIFT 27
918 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
919 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
920 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
921 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
922 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
923 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
924
925 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
926
927 #define DBELL_BRDCAST PPC_BIT(37)
928 #define DBELL_LPIDTAG_SHIFT 14
929 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
930 #define DBELL_PIRTAG_MASK 0x3fff
931
932 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
933
934 #define PPC_PAGE_SIZES_MAX_SZ 8
935
936 struct ppc_radix_page_info {
937 uint32_t count;
938 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
939 };
940
941 /*****************************************************************************/
942 /* The whole PowerPC CPU context */
943
944 /*
945 * PowerPC needs eight modes for different hypervisor/supervisor/guest
946 * + real/paged mode combinations. The other two modes are for
947 * external PID load/store.
948 */
949 #define PPC_TLB_EPID_LOAD 8
950 #define PPC_TLB_EPID_STORE 9
951
952 #define PPC_CPU_OPCODES_LEN 0x40
953 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
954
955 struct CPUPPCState {
956 /* Most commonly used resources during translated code execution first */
957 target_ulong gpr[32]; /* general purpose registers */
958 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
959 target_ulong lr;
960 target_ulong ctr;
961 uint32_t crf[8]; /* condition register */
962 #if defined(TARGET_PPC64)
963 target_ulong cfar;
964 #endif
965 target_ulong xer; /* XER (with SO, OV, CA split out) */
966 target_ulong so;
967 target_ulong ov;
968 target_ulong ca;
969 target_ulong ov32;
970 target_ulong ca32;
971
972 target_ulong reserve_addr; /* Reservation address */
973 target_ulong reserve_val; /* Reservation value */
974 target_ulong reserve_val2;
975
976 /* These are used in supervisor mode only */
977 target_ulong msr; /* machine state register */
978 target_ulong tgpr[4]; /* temporary general purpose registers, */
979 /* used to speed-up TLB assist handlers */
980
981 target_ulong nip; /* next instruction pointer */
982 uint64_t retxh; /* high part of 128-bit helper return */
983
984 /* when a memory exception occurs, the access type is stored here */
985 int access_type;
986
987 #if !defined(CONFIG_USER_ONLY)
988 /* MMU context, only relevant for full system emulation */
989 #if defined(TARGET_PPC64)
990 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
991 #endif
992 target_ulong sr[32]; /* segment registers */
993 uint32_t nb_BATs; /* number of BATs */
994 target_ulong DBAT[2][8];
995 target_ulong IBAT[2][8];
996 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
997 int32_t nb_tlb; /* Total number of TLB */
998 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
999 int nb_ways; /* Number of ways in the TLB set */
1000 int last_way; /* Last used way used to allocate TLB in a LRU way */
1001 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1002 int nb_pids; /* Number of available PID registers */
1003 int tlb_type; /* Type of TLB we're dealing with */
1004 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1005 target_ulong pb[4]; /* 403 dedicated access protection registers */
1006 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1007 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1008 uint32_t tlb_need_flush; /* Delayed flush needed */
1009 #define TLB_NEED_LOCAL_FLUSH 0x1
1010 #define TLB_NEED_GLOBAL_FLUSH 0x2
1011 #endif
1012
1013 /* Other registers */
1014 target_ulong spr[1024]; /* special purpose registers */
1015 ppc_spr_t spr_cb[1024];
1016 /* Vector status and control register, minus VSCR_SAT */
1017 uint32_t vscr;
1018 /* VSX registers (including FP and AVR) */
1019 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
1020 /* Non-zero if and only if VSCR_SAT should be set */
1021 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
1022 /* SPE registers */
1023 uint64_t spe_acc;
1024 uint32_t spe_fscr;
1025 /* SPE and Altivec share status as they'll never be used simultaneously */
1026 float_status vec_status;
1027 float_status fp_status; /* Floating point execution context */
1028 target_ulong fpscr; /* Floating point status and control register */
1029
1030 /* Internal devices resources */
1031 ppc_tb_t *tb_env; /* Time base and decrementer */
1032 ppc_dcr_t *dcr_env; /* Device control registers */
1033
1034 int dcache_line_size;
1035 int icache_line_size;
1036
1037 /* These resources are used during exception processing */
1038 /* CPU model definition */
1039 target_ulong msr_mask;
1040 powerpc_mmu_t mmu_model;
1041 powerpc_excp_t excp_model;
1042 powerpc_input_t bus_model;
1043 int bfd_mach;
1044 uint32_t flags;
1045 uint64_t insns_flags;
1046 uint64_t insns_flags2;
1047
1048 int error_code;
1049 uint32_t pending_interrupts;
1050 #if !defined(CONFIG_USER_ONLY)
1051 /*
1052 * This is the IRQ controller, which is implementation dependent and only
1053 * relevant when emulating a complete machine. Note that this isn't used
1054 * by recent Book3s compatible CPUs (POWER7 and newer).
1055 */
1056 uint32_t irq_input_state;
1057 void **irq_inputs;
1058
1059 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
1060 target_ulong excp_prefix;
1061 target_ulong ivor_mask;
1062 target_ulong ivpr_mask;
1063 target_ulong hreset_vector;
1064 hwaddr mpic_iack;
1065 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1066 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1067 /* instructions and SPRs are diallowed if MSR:HV is 0 */
1068 /*
1069 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1070 * special way (such as routing some resume causes to 0x100, i.e. sreset).
1071 */
1072 bool resume_as_sreset;
1073 #endif
1074
1075 /* These resources are used only in QEMU core */
1076 target_ulong hflags; /* hflags is MSR & HFLAGS_MASK */
1077 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1078 int immu_idx; /* precomputed MMU index to speed up insn accesses */
1079 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
1080
1081 /* Power management */
1082 int (*check_pow)(CPUPPCState *env);
1083
1084 #if !defined(CONFIG_USER_ONLY)
1085 void *load_info; /* holds boot loading state */
1086 #endif
1087
1088 /* booke timers */
1089
1090 /*
1091 * Specifies bit locations of the Time Base used to signal a fixed timer
1092 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
1093 *
1094 * 0 selects the least significant bit, 63 selects the most significant bit
1095 */
1096 uint8_t fit_period[4];
1097 uint8_t wdt_period[4];
1098
1099 /* Transactional memory state */
1100 target_ulong tm_gpr[32];
1101 ppc_avr_t tm_vsr[64];
1102 uint64_t tm_cr;
1103 uint64_t tm_lr;
1104 uint64_t tm_ctr;
1105 uint64_t tm_fpscr;
1106 uint64_t tm_amr;
1107 uint64_t tm_ppr;
1108 uint64_t tm_vrsave;
1109 uint32_t tm_vscr;
1110 uint64_t tm_dscr;
1111 uint64_t tm_tar;
1112 };
1113
1114 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1115 do { \
1116 env->fit_period[0] = (a_); \
1117 env->fit_period[1] = (b_); \
1118 env->fit_period[2] = (c_); \
1119 env->fit_period[3] = (d_); \
1120 } while (0)
1121
1122 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1123 do { \
1124 env->wdt_period[0] = (a_); \
1125 env->wdt_period[1] = (b_); \
1126 env->wdt_period[2] = (c_); \
1127 env->wdt_period[3] = (d_); \
1128 } while (0)
1129
1130 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1131 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1132
1133 /**
1134 * PowerPCCPU:
1135 * @env: #CPUPPCState
1136 * @vcpu_id: vCPU identifier given to KVM
1137 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1138 *
1139 * A PowerPC CPU.
1140 */
1141 struct PowerPCCPU {
1142 /*< private >*/
1143 CPUState parent_obj;
1144 /*< public >*/
1145
1146 CPUNegativeOffsetState neg;
1147 CPUPPCState env;
1148
1149 int vcpu_id;
1150 uint32_t compat_pvr;
1151 PPCVirtualHypervisor *vhyp;
1152 void *machine_data;
1153 int32_t node_id; /* NUMA node this CPU belongs to */
1154 PPCHash64Options *hash64_opts;
1155
1156 /* Those resources are used only during code translation */
1157 /* opcode handlers */
1158 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1159
1160 /* Fields related to migration compatibility hacks */
1161 bool pre_2_8_migration;
1162 target_ulong mig_msr_mask;
1163 uint64_t mig_insns_flags;
1164 uint64_t mig_insns_flags2;
1165 uint32_t mig_nb_BATs;
1166 bool pre_2_10_migration;
1167 bool pre_3_0_migration;
1168 int32_t mig_slb_nr;
1169 };
1170
1171
1172 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1173 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1174 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1175
1176 struct PPCVirtualHypervisorClass {
1177 InterfaceClass parent;
1178 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1179 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1180 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1181 hwaddr ptex, int n);
1182 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1183 const ppc_hash_pte64_t *hptes,
1184 hwaddr ptex, int n);
1185 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1186 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1187 void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1188 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1189 #ifndef CONFIG_USER_ONLY
1190 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1191 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1192 #endif
1193 };
1194
1195 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1196 #define PPC_VIRTUAL_HYPERVISOR(obj) \
1197 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1198 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1199 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1200 TYPE_PPC_VIRTUAL_HYPERVISOR)
1201 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1202 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1203 TYPE_PPC_VIRTUAL_HYPERVISOR)
1204
1205 void ppc_cpu_do_interrupt(CPUState *cpu);
1206 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1207 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
1208 void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
1209 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1210 int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1211 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
1212 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1213 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1214 #ifndef CONFIG_USER_ONLY
1215 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1216 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1217 #endif
1218 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1219 int cpuid, void *opaque);
1220 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1221 int cpuid, void *opaque);
1222 #ifndef CONFIG_USER_ONLY
1223 void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector);
1224 void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
1225 extern const VMStateDescription vmstate_ppc_cpu;
1226 #endif
1227
1228 /*****************************************************************************/
1229 void ppc_translate_init(void);
1230 /*
1231 * you can call this signal handler from your SIGBUS and SIGSEGV
1232 * signal handlers to inform the virtual CPU of exceptions. non zero
1233 * is returned if the signal was handled by the virtual CPU.
1234 */
1235 int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
1236 bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1237 MMUAccessType access_type, int mmu_idx,
1238 bool probe, uintptr_t retaddr);
1239
1240 #if !defined(CONFIG_USER_ONLY)
1241 void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
1242 void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
1243 #endif /* !defined(CONFIG_USER_ONLY) */
1244 void ppc_store_msr(CPUPPCState *env, target_ulong value);
1245
1246 void ppc_cpu_list(void);
1247
1248 /* Time-base and decrementer management */
1249 #ifndef NO_CPU_IO_DEFS
1250 uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1251 uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1252 void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1253 void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1254 uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1255 uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1256 void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1257 void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
1258 uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1259 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
1260 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1261 target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1262 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1263 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1264 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
1265 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
1266 uint64_t cpu_ppc_load_purr(CPUPPCState *env);
1267 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
1268 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1269 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
1270 #if !defined(CONFIG_USER_ONLY)
1271 void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1272 void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1273 target_ulong load_40x_pit(CPUPPCState *env);
1274 void store_40x_pit(CPUPPCState *env, target_ulong val);
1275 void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1276 void store_40x_sler(CPUPPCState *env, uint32_t val);
1277 void store_booke_tcr(CPUPPCState *env, target_ulong val);
1278 void store_booke_tsr(CPUPPCState *env, target_ulong val);
1279 void ppc_tlb_invalidate_all(CPUPPCState *env);
1280 void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
1281 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1282 #endif
1283 #endif
1284
1285 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1286 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1287 const char *caller, uint32_t cause);
1288
ppc_dump_gpr(CPUPPCState * env,int gprn)1289 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1290 {
1291 uint64_t gprv;
1292
1293 gprv = env->gpr[gprn];
1294 if (env->flags & POWERPC_FLAG_SPE) {
1295 /*
1296 * If the CPU implements the SPE extension, we have to get the
1297 * high bits of the GPR from the gprh storage area
1298 */
1299 gprv &= 0xFFFFFFFFULL;
1300 gprv |= (uint64_t)env->gprh[gprn] << 32;
1301 }
1302
1303 return gprv;
1304 }
1305
1306 /* Device control registers */
1307 int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1308 int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1309
1310 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1311 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1312 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1313
1314 #define cpu_signal_handler cpu_ppc_signal_handler
1315 #define cpu_list ppc_cpu_list
1316
1317 /* MMU modes definitions */
1318 #define MMU_USER_IDX 0
cpu_mmu_index(CPUPPCState * env,bool ifetch)1319 static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
1320 {
1321 return ifetch ? env->immu_idx : env->dmmu_idx;
1322 }
1323
1324 /* Compatibility modes */
1325 #if defined(TARGET_PPC64)
1326 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1327 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1328 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1329 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1330
1331 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1332
1333 #if !defined(CONFIG_USER_ONLY)
1334 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1335 #endif
1336 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1337 void ppc_compat_add_property(Object *obj, const char *name,
1338 uint32_t *compat_pvr, const char *basedesc,
1339 Error **errp);
1340 #endif /* defined(TARGET_PPC64) */
1341
1342 typedef CPUPPCState CPUArchState;
1343 typedef PowerPCCPU ArchCPU;
1344
1345 #include "exec/cpu-all.h"
1346
1347 /*****************************************************************************/
1348 /* CRF definitions */
1349 #define CRF_LT_BIT 3
1350 #define CRF_GT_BIT 2
1351 #define CRF_EQ_BIT 1
1352 #define CRF_SO_BIT 0
1353 #define CRF_LT (1 << CRF_LT_BIT)
1354 #define CRF_GT (1 << CRF_GT_BIT)
1355 #define CRF_EQ (1 << CRF_EQ_BIT)
1356 #define CRF_SO (1 << CRF_SO_BIT)
1357 /* For SPE extensions */
1358 #define CRF_CH (1 << CRF_LT_BIT)
1359 #define CRF_CL (1 << CRF_GT_BIT)
1360 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1361 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1362
1363 /* XER definitions */
1364 #define XER_SO 31
1365 #define XER_OV 30
1366 #define XER_CA 29
1367 #define XER_OV32 19
1368 #define XER_CA32 18
1369 #define XER_CMP 8
1370 #define XER_BC 0
1371 #define xer_so (env->so)
1372 #define xer_ov (env->ov)
1373 #define xer_ca (env->ca)
1374 #define xer_ov32 (env->ov)
1375 #define xer_ca32 (env->ca)
1376 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1377 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1378
1379 /* SPR definitions */
1380 #define SPR_MQ (0x000)
1381 #define SPR_XER (0x001)
1382 #define SPR_601_VRTCU (0x004)
1383 #define SPR_601_VRTCL (0x005)
1384 #define SPR_601_UDECR (0x006)
1385 #define SPR_LR (0x008)
1386 #define SPR_CTR (0x009)
1387 #define SPR_UAMR (0x00D)
1388 #define SPR_DSCR (0x011)
1389 #define SPR_DSISR (0x012)
1390 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1391 #define SPR_601_RTCU (0x014)
1392 #define SPR_601_RTCL (0x015)
1393 #define SPR_DECR (0x016)
1394 #define SPR_SDR1 (0x019)
1395 #define SPR_SRR0 (0x01A)
1396 #define SPR_SRR1 (0x01B)
1397 #define SPR_CFAR (0x01C)
1398 #define SPR_AMR (0x01D)
1399 #define SPR_ACOP (0x01F)
1400 #define SPR_BOOKE_PID (0x030)
1401 #define SPR_BOOKS_PID (0x030)
1402 #define SPR_BOOKE_DECAR (0x036)
1403 #define SPR_BOOKE_CSRR0 (0x03A)
1404 #define SPR_BOOKE_CSRR1 (0x03B)
1405 #define SPR_BOOKE_DEAR (0x03D)
1406 #define SPR_IAMR (0x03D)
1407 #define SPR_BOOKE_ESR (0x03E)
1408 #define SPR_BOOKE_IVPR (0x03F)
1409 #define SPR_MPC_EIE (0x050)
1410 #define SPR_MPC_EID (0x051)
1411 #define SPR_MPC_NRI (0x052)
1412 #define SPR_TFHAR (0x080)
1413 #define SPR_TFIAR (0x081)
1414 #define SPR_TEXASR (0x082)
1415 #define SPR_TEXASRU (0x083)
1416 #define SPR_UCTRL (0x088)
1417 #define SPR_TIDR (0x090)
1418 #define SPR_MPC_CMPA (0x090)
1419 #define SPR_MPC_CMPB (0x091)
1420 #define SPR_MPC_CMPC (0x092)
1421 #define SPR_MPC_CMPD (0x093)
1422 #define SPR_MPC_ECR (0x094)
1423 #define SPR_MPC_DER (0x095)
1424 #define SPR_MPC_COUNTA (0x096)
1425 #define SPR_MPC_COUNTB (0x097)
1426 #define SPR_CTRL (0x098)
1427 #define SPR_MPC_CMPE (0x098)
1428 #define SPR_MPC_CMPF (0x099)
1429 #define SPR_FSCR (0x099)
1430 #define SPR_MPC_CMPG (0x09A)
1431 #define SPR_MPC_CMPH (0x09B)
1432 #define SPR_MPC_LCTRL1 (0x09C)
1433 #define SPR_MPC_LCTRL2 (0x09D)
1434 #define SPR_UAMOR (0x09D)
1435 #define SPR_MPC_ICTRL (0x09E)
1436 #define SPR_MPC_BAR (0x09F)
1437 #define SPR_PSPB (0x09F)
1438 #define SPR_DPDES (0x0B0)
1439 #define SPR_DAWR (0x0B4)
1440 #define SPR_RPR (0x0BA)
1441 #define SPR_CIABR (0x0BB)
1442 #define SPR_DAWRX (0x0BC)
1443 #define SPR_HFSCR (0x0BE)
1444 #define SPR_VRSAVE (0x100)
1445 #define SPR_USPRG0 (0x100)
1446 #define SPR_USPRG1 (0x101)
1447 #define SPR_USPRG2 (0x102)
1448 #define SPR_USPRG3 (0x103)
1449 #define SPR_USPRG4 (0x104)
1450 #define SPR_USPRG5 (0x105)
1451 #define SPR_USPRG6 (0x106)
1452 #define SPR_USPRG7 (0x107)
1453 #define SPR_VTBL (0x10C)
1454 #define SPR_VTBU (0x10D)
1455 #define SPR_SPRG0 (0x110)
1456 #define SPR_SPRG1 (0x111)
1457 #define SPR_SPRG2 (0x112)
1458 #define SPR_SPRG3 (0x113)
1459 #define SPR_SPRG4 (0x114)
1460 #define SPR_SCOMC (0x114)
1461 #define SPR_SPRG5 (0x115)
1462 #define SPR_SCOMD (0x115)
1463 #define SPR_SPRG6 (0x116)
1464 #define SPR_SPRG7 (0x117)
1465 #define SPR_ASR (0x118)
1466 #define SPR_EAR (0x11A)
1467 #define SPR_TBL (0x11C)
1468 #define SPR_TBU (0x11D)
1469 #define SPR_TBU40 (0x11E)
1470 #define SPR_SVR (0x11E)
1471 #define SPR_BOOKE_PIR (0x11E)
1472 #define SPR_PVR (0x11F)
1473 #define SPR_HSPRG0 (0x130)
1474 #define SPR_BOOKE_DBSR (0x130)
1475 #define SPR_HSPRG1 (0x131)
1476 #define SPR_HDSISR (0x132)
1477 #define SPR_HDAR (0x133)
1478 #define SPR_BOOKE_EPCR (0x133)
1479 #define SPR_SPURR (0x134)
1480 #define SPR_BOOKE_DBCR0 (0x134)
1481 #define SPR_IBCR (0x135)
1482 #define SPR_PURR (0x135)
1483 #define SPR_BOOKE_DBCR1 (0x135)
1484 #define SPR_DBCR (0x136)
1485 #define SPR_HDEC (0x136)
1486 #define SPR_BOOKE_DBCR2 (0x136)
1487 #define SPR_HIOR (0x137)
1488 #define SPR_MBAR (0x137)
1489 #define SPR_RMOR (0x138)
1490 #define SPR_BOOKE_IAC1 (0x138)
1491 #define SPR_HRMOR (0x139)
1492 #define SPR_BOOKE_IAC2 (0x139)
1493 #define SPR_HSRR0 (0x13A)
1494 #define SPR_BOOKE_IAC3 (0x13A)
1495 #define SPR_HSRR1 (0x13B)
1496 #define SPR_BOOKE_IAC4 (0x13B)
1497 #define SPR_BOOKE_DAC1 (0x13C)
1498 #define SPR_MMCRH (0x13C)
1499 #define SPR_DABR2 (0x13D)
1500 #define SPR_BOOKE_DAC2 (0x13D)
1501 #define SPR_TFMR (0x13D)
1502 #define SPR_BOOKE_DVC1 (0x13E)
1503 #define SPR_LPCR (0x13E)
1504 #define SPR_BOOKE_DVC2 (0x13F)
1505 #define SPR_LPIDR (0x13F)
1506 #define SPR_BOOKE_TSR (0x150)
1507 #define SPR_HMER (0x150)
1508 #define SPR_HMEER (0x151)
1509 #define SPR_PCR (0x152)
1510 #define SPR_BOOKE_LPIDR (0x152)
1511 #define SPR_BOOKE_TCR (0x154)
1512 #define SPR_BOOKE_TLB0PS (0x158)
1513 #define SPR_BOOKE_TLB1PS (0x159)
1514 #define SPR_BOOKE_TLB2PS (0x15A)
1515 #define SPR_BOOKE_TLB3PS (0x15B)
1516 #define SPR_AMOR (0x15D)
1517 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1518 #define SPR_BOOKE_IVOR0 (0x190)
1519 #define SPR_BOOKE_IVOR1 (0x191)
1520 #define SPR_BOOKE_IVOR2 (0x192)
1521 #define SPR_BOOKE_IVOR3 (0x193)
1522 #define SPR_BOOKE_IVOR4 (0x194)
1523 #define SPR_BOOKE_IVOR5 (0x195)
1524 #define SPR_BOOKE_IVOR6 (0x196)
1525 #define SPR_BOOKE_IVOR7 (0x197)
1526 #define SPR_BOOKE_IVOR8 (0x198)
1527 #define SPR_BOOKE_IVOR9 (0x199)
1528 #define SPR_BOOKE_IVOR10 (0x19A)
1529 #define SPR_BOOKE_IVOR11 (0x19B)
1530 #define SPR_BOOKE_IVOR12 (0x19C)
1531 #define SPR_BOOKE_IVOR13 (0x19D)
1532 #define SPR_BOOKE_IVOR14 (0x19E)
1533 #define SPR_BOOKE_IVOR15 (0x19F)
1534 #define SPR_BOOKE_IVOR38 (0x1B0)
1535 #define SPR_BOOKE_IVOR39 (0x1B1)
1536 #define SPR_BOOKE_IVOR40 (0x1B2)
1537 #define SPR_BOOKE_IVOR41 (0x1B3)
1538 #define SPR_BOOKE_IVOR42 (0x1B4)
1539 #define SPR_BOOKE_GIVOR2 (0x1B8)
1540 #define SPR_BOOKE_GIVOR3 (0x1B9)
1541 #define SPR_BOOKE_GIVOR4 (0x1BA)
1542 #define SPR_BOOKE_GIVOR8 (0x1BB)
1543 #define SPR_BOOKE_GIVOR13 (0x1BC)
1544 #define SPR_BOOKE_GIVOR14 (0x1BD)
1545 #define SPR_TIR (0x1BE)
1546 #define SPR_PTCR (0x1D0)
1547 #define SPR_BOOKE_SPEFSCR (0x200)
1548 #define SPR_Exxx_BBEAR (0x201)
1549 #define SPR_Exxx_BBTAR (0x202)
1550 #define SPR_Exxx_L1CFG0 (0x203)
1551 #define SPR_Exxx_L1CFG1 (0x204)
1552 #define SPR_Exxx_NPIDR (0x205)
1553 #define SPR_ATBL (0x20E)
1554 #define SPR_ATBU (0x20F)
1555 #define SPR_IBAT0U (0x210)
1556 #define SPR_BOOKE_IVOR32 (0x210)
1557 #define SPR_RCPU_MI_GRA (0x210)
1558 #define SPR_IBAT0L (0x211)
1559 #define SPR_BOOKE_IVOR33 (0x211)
1560 #define SPR_IBAT1U (0x212)
1561 #define SPR_BOOKE_IVOR34 (0x212)
1562 #define SPR_IBAT1L (0x213)
1563 #define SPR_BOOKE_IVOR35 (0x213)
1564 #define SPR_IBAT2U (0x214)
1565 #define SPR_BOOKE_IVOR36 (0x214)
1566 #define SPR_IBAT2L (0x215)
1567 #define SPR_BOOKE_IVOR37 (0x215)
1568 #define SPR_IBAT3U (0x216)
1569 #define SPR_IBAT3L (0x217)
1570 #define SPR_DBAT0U (0x218)
1571 #define SPR_RCPU_L2U_GRA (0x218)
1572 #define SPR_DBAT0L (0x219)
1573 #define SPR_DBAT1U (0x21A)
1574 #define SPR_DBAT1L (0x21B)
1575 #define SPR_DBAT2U (0x21C)
1576 #define SPR_DBAT2L (0x21D)
1577 #define SPR_DBAT3U (0x21E)
1578 #define SPR_DBAT3L (0x21F)
1579 #define SPR_IBAT4U (0x230)
1580 #define SPR_RPCU_BBCMCR (0x230)
1581 #define SPR_MPC_IC_CST (0x230)
1582 #define SPR_Exxx_CTXCR (0x230)
1583 #define SPR_IBAT4L (0x231)
1584 #define SPR_MPC_IC_ADR (0x231)
1585 #define SPR_Exxx_DBCR3 (0x231)
1586 #define SPR_IBAT5U (0x232)
1587 #define SPR_MPC_IC_DAT (0x232)
1588 #define SPR_Exxx_DBCNT (0x232)
1589 #define SPR_IBAT5L (0x233)
1590 #define SPR_IBAT6U (0x234)
1591 #define SPR_IBAT6L (0x235)
1592 #define SPR_IBAT7U (0x236)
1593 #define SPR_IBAT7L (0x237)
1594 #define SPR_DBAT4U (0x238)
1595 #define SPR_RCPU_L2U_MCR (0x238)
1596 #define SPR_MPC_DC_CST (0x238)
1597 #define SPR_Exxx_ALTCTXCR (0x238)
1598 #define SPR_DBAT4L (0x239)
1599 #define SPR_MPC_DC_ADR (0x239)
1600 #define SPR_DBAT5U (0x23A)
1601 #define SPR_BOOKE_MCSRR0 (0x23A)
1602 #define SPR_MPC_DC_DAT (0x23A)
1603 #define SPR_DBAT5L (0x23B)
1604 #define SPR_BOOKE_MCSRR1 (0x23B)
1605 #define SPR_DBAT6U (0x23C)
1606 #define SPR_BOOKE_MCSR (0x23C)
1607 #define SPR_DBAT6L (0x23D)
1608 #define SPR_Exxx_MCAR (0x23D)
1609 #define SPR_DBAT7U (0x23E)
1610 #define SPR_BOOKE_DSRR0 (0x23E)
1611 #define SPR_DBAT7L (0x23F)
1612 #define SPR_BOOKE_DSRR1 (0x23F)
1613 #define SPR_BOOKE_SPRG8 (0x25C)
1614 #define SPR_BOOKE_SPRG9 (0x25D)
1615 #define SPR_BOOKE_MAS0 (0x270)
1616 #define SPR_BOOKE_MAS1 (0x271)
1617 #define SPR_BOOKE_MAS2 (0x272)
1618 #define SPR_BOOKE_MAS3 (0x273)
1619 #define SPR_BOOKE_MAS4 (0x274)
1620 #define SPR_BOOKE_MAS5 (0x275)
1621 #define SPR_BOOKE_MAS6 (0x276)
1622 #define SPR_BOOKE_PID1 (0x279)
1623 #define SPR_BOOKE_PID2 (0x27A)
1624 #define SPR_MPC_DPDR (0x280)
1625 #define SPR_MPC_IMMR (0x288)
1626 #define SPR_BOOKE_TLB0CFG (0x2B0)
1627 #define SPR_BOOKE_TLB1CFG (0x2B1)
1628 #define SPR_BOOKE_TLB2CFG (0x2B2)
1629 #define SPR_BOOKE_TLB3CFG (0x2B3)
1630 #define SPR_BOOKE_EPR (0x2BE)
1631 #define SPR_PERF0 (0x300)
1632 #define SPR_RCPU_MI_RBA0 (0x300)
1633 #define SPR_MPC_MI_CTR (0x300)
1634 #define SPR_POWER_USIER (0x300)
1635 #define SPR_PERF1 (0x301)
1636 #define SPR_RCPU_MI_RBA1 (0x301)
1637 #define SPR_POWER_UMMCR2 (0x301)
1638 #define SPR_PERF2 (0x302)
1639 #define SPR_RCPU_MI_RBA2 (0x302)
1640 #define SPR_MPC_MI_AP (0x302)
1641 #define SPR_POWER_UMMCRA (0x302)
1642 #define SPR_PERF3 (0x303)
1643 #define SPR_RCPU_MI_RBA3 (0x303)
1644 #define SPR_MPC_MI_EPN (0x303)
1645 #define SPR_POWER_UPMC1 (0x303)
1646 #define SPR_PERF4 (0x304)
1647 #define SPR_POWER_UPMC2 (0x304)
1648 #define SPR_PERF5 (0x305)
1649 #define SPR_MPC_MI_TWC (0x305)
1650 #define SPR_POWER_UPMC3 (0x305)
1651 #define SPR_PERF6 (0x306)
1652 #define SPR_MPC_MI_RPN (0x306)
1653 #define SPR_POWER_UPMC4 (0x306)
1654 #define SPR_PERF7 (0x307)
1655 #define SPR_POWER_UPMC5 (0x307)
1656 #define SPR_PERF8 (0x308)
1657 #define SPR_RCPU_L2U_RBA0 (0x308)
1658 #define SPR_MPC_MD_CTR (0x308)
1659 #define SPR_POWER_UPMC6 (0x308)
1660 #define SPR_PERF9 (0x309)
1661 #define SPR_RCPU_L2U_RBA1 (0x309)
1662 #define SPR_MPC_MD_CASID (0x309)
1663 #define SPR_970_UPMC7 (0X309)
1664 #define SPR_PERFA (0x30A)
1665 #define SPR_RCPU_L2U_RBA2 (0x30A)
1666 #define SPR_MPC_MD_AP (0x30A)
1667 #define SPR_970_UPMC8 (0X30A)
1668 #define SPR_PERFB (0x30B)
1669 #define SPR_RCPU_L2U_RBA3 (0x30B)
1670 #define SPR_MPC_MD_EPN (0x30B)
1671 #define SPR_POWER_UMMCR0 (0X30B)
1672 #define SPR_PERFC (0x30C)
1673 #define SPR_MPC_MD_TWB (0x30C)
1674 #define SPR_POWER_USIAR (0X30C)
1675 #define SPR_PERFD (0x30D)
1676 #define SPR_MPC_MD_TWC (0x30D)
1677 #define SPR_POWER_USDAR (0X30D)
1678 #define SPR_PERFE (0x30E)
1679 #define SPR_MPC_MD_RPN (0x30E)
1680 #define SPR_POWER_UMMCR1 (0X30E)
1681 #define SPR_PERFF (0x30F)
1682 #define SPR_MPC_MD_TW (0x30F)
1683 #define SPR_UPERF0 (0x310)
1684 #define SPR_POWER_SIER (0x310)
1685 #define SPR_UPERF1 (0x311)
1686 #define SPR_POWER_MMCR2 (0x311)
1687 #define SPR_UPERF2 (0x312)
1688 #define SPR_POWER_MMCRA (0X312)
1689 #define SPR_UPERF3 (0x313)
1690 #define SPR_POWER_PMC1 (0X313)
1691 #define SPR_UPERF4 (0x314)
1692 #define SPR_POWER_PMC2 (0X314)
1693 #define SPR_UPERF5 (0x315)
1694 #define SPR_POWER_PMC3 (0X315)
1695 #define SPR_UPERF6 (0x316)
1696 #define SPR_POWER_PMC4 (0X316)
1697 #define SPR_UPERF7 (0x317)
1698 #define SPR_POWER_PMC5 (0X317)
1699 #define SPR_UPERF8 (0x318)
1700 #define SPR_POWER_PMC6 (0X318)
1701 #define SPR_UPERF9 (0x319)
1702 #define SPR_970_PMC7 (0X319)
1703 #define SPR_UPERFA (0x31A)
1704 #define SPR_970_PMC8 (0X31A)
1705 #define SPR_UPERFB (0x31B)
1706 #define SPR_POWER_MMCR0 (0X31B)
1707 #define SPR_UPERFC (0x31C)
1708 #define SPR_POWER_SIAR (0X31C)
1709 #define SPR_UPERFD (0x31D)
1710 #define SPR_POWER_SDAR (0X31D)
1711 #define SPR_UPERFE (0x31E)
1712 #define SPR_POWER_MMCR1 (0X31E)
1713 #define SPR_UPERFF (0x31F)
1714 #define SPR_RCPU_MI_RA0 (0x320)
1715 #define SPR_MPC_MI_DBCAM (0x320)
1716 #define SPR_BESCRS (0x320)
1717 #define SPR_RCPU_MI_RA1 (0x321)
1718 #define SPR_MPC_MI_DBRAM0 (0x321)
1719 #define SPR_BESCRSU (0x321)
1720 #define SPR_RCPU_MI_RA2 (0x322)
1721 #define SPR_MPC_MI_DBRAM1 (0x322)
1722 #define SPR_BESCRR (0x322)
1723 #define SPR_RCPU_MI_RA3 (0x323)
1724 #define SPR_BESCRRU (0x323)
1725 #define SPR_EBBHR (0x324)
1726 #define SPR_EBBRR (0x325)
1727 #define SPR_BESCR (0x326)
1728 #define SPR_RCPU_L2U_RA0 (0x328)
1729 #define SPR_MPC_MD_DBCAM (0x328)
1730 #define SPR_RCPU_L2U_RA1 (0x329)
1731 #define SPR_MPC_MD_DBRAM0 (0x329)
1732 #define SPR_RCPU_L2U_RA2 (0x32A)
1733 #define SPR_MPC_MD_DBRAM1 (0x32A)
1734 #define SPR_RCPU_L2U_RA3 (0x32B)
1735 #define SPR_TAR (0x32F)
1736 #define SPR_ASDR (0x330)
1737 #define SPR_IC (0x350)
1738 #define SPR_VTB (0x351)
1739 #define SPR_MMCRC (0x353)
1740 #define SPR_PSSCR (0x357)
1741 #define SPR_440_INV0 (0x370)
1742 #define SPR_440_INV1 (0x371)
1743 #define SPR_440_INV2 (0x372)
1744 #define SPR_440_INV3 (0x373)
1745 #define SPR_440_ITV0 (0x374)
1746 #define SPR_440_ITV1 (0x375)
1747 #define SPR_440_ITV2 (0x376)
1748 #define SPR_440_ITV3 (0x377)
1749 #define SPR_440_CCR1 (0x378)
1750 #define SPR_TACR (0x378)
1751 #define SPR_TCSCR (0x379)
1752 #define SPR_CSIGR (0x37a)
1753 #define SPR_DCRIPR (0x37B)
1754 #define SPR_POWER_SPMC1 (0x37C)
1755 #define SPR_POWER_SPMC2 (0x37D)
1756 #define SPR_POWER_MMCRS (0x37E)
1757 #define SPR_WORT (0x37F)
1758 #define SPR_PPR (0x380)
1759 #define SPR_750_GQR0 (0x390)
1760 #define SPR_440_DNV0 (0x390)
1761 #define SPR_750_GQR1 (0x391)
1762 #define SPR_440_DNV1 (0x391)
1763 #define SPR_750_GQR2 (0x392)
1764 #define SPR_440_DNV2 (0x392)
1765 #define SPR_750_GQR3 (0x393)
1766 #define SPR_440_DNV3 (0x393)
1767 #define SPR_750_GQR4 (0x394)
1768 #define SPR_440_DTV0 (0x394)
1769 #define SPR_750_GQR5 (0x395)
1770 #define SPR_440_DTV1 (0x395)
1771 #define SPR_750_GQR6 (0x396)
1772 #define SPR_440_DTV2 (0x396)
1773 #define SPR_750_GQR7 (0x397)
1774 #define SPR_440_DTV3 (0x397)
1775 #define SPR_750_THRM4 (0x398)
1776 #define SPR_750CL_HID2 (0x398)
1777 #define SPR_440_DVLIM (0x398)
1778 #define SPR_750_WPAR (0x399)
1779 #define SPR_440_IVLIM (0x399)
1780 #define SPR_TSCR (0x399)
1781 #define SPR_750_DMAU (0x39A)
1782 #define SPR_750_DMAL (0x39B)
1783 #define SPR_440_RSTCFG (0x39B)
1784 #define SPR_BOOKE_DCDBTRL (0x39C)
1785 #define SPR_BOOKE_DCDBTRH (0x39D)
1786 #define SPR_BOOKE_ICDBTRL (0x39E)
1787 #define SPR_BOOKE_ICDBTRH (0x39F)
1788 #define SPR_74XX_UMMCR2 (0x3A0)
1789 #define SPR_7XX_UPMC5 (0x3A1)
1790 #define SPR_7XX_UPMC6 (0x3A2)
1791 #define SPR_UBAMR (0x3A7)
1792 #define SPR_7XX_UMMCR0 (0x3A8)
1793 #define SPR_7XX_UPMC1 (0x3A9)
1794 #define SPR_7XX_UPMC2 (0x3AA)
1795 #define SPR_7XX_USIAR (0x3AB)
1796 #define SPR_7XX_UMMCR1 (0x3AC)
1797 #define SPR_7XX_UPMC3 (0x3AD)
1798 #define SPR_7XX_UPMC4 (0x3AE)
1799 #define SPR_USDA (0x3AF)
1800 #define SPR_40x_ZPR (0x3B0)
1801 #define SPR_BOOKE_MAS7 (0x3B0)
1802 #define SPR_74XX_MMCR2 (0x3B0)
1803 #define SPR_7XX_PMC5 (0x3B1)
1804 #define SPR_40x_PID (0x3B1)
1805 #define SPR_7XX_PMC6 (0x3B2)
1806 #define SPR_440_MMUCR (0x3B2)
1807 #define SPR_4xx_CCR0 (0x3B3)
1808 #define SPR_BOOKE_EPLC (0x3B3)
1809 #define SPR_405_IAC3 (0x3B4)
1810 #define SPR_BOOKE_EPSC (0x3B4)
1811 #define SPR_405_IAC4 (0x3B5)
1812 #define SPR_405_DVC1 (0x3B6)
1813 #define SPR_405_DVC2 (0x3B7)
1814 #define SPR_BAMR (0x3B7)
1815 #define SPR_7XX_MMCR0 (0x3B8)
1816 #define SPR_7XX_PMC1 (0x3B9)
1817 #define SPR_40x_SGR (0x3B9)
1818 #define SPR_7XX_PMC2 (0x3BA)
1819 #define SPR_40x_DCWR (0x3BA)
1820 #define SPR_7XX_SIAR (0x3BB)
1821 #define SPR_405_SLER (0x3BB)
1822 #define SPR_7XX_MMCR1 (0x3BC)
1823 #define SPR_405_SU0R (0x3BC)
1824 #define SPR_401_SKR (0x3BC)
1825 #define SPR_7XX_PMC3 (0x3BD)
1826 #define SPR_405_DBCR1 (0x3BD)
1827 #define SPR_7XX_PMC4 (0x3BE)
1828 #define SPR_SDA (0x3BF)
1829 #define SPR_403_VTBL (0x3CC)
1830 #define SPR_403_VTBU (0x3CD)
1831 #define SPR_DMISS (0x3D0)
1832 #define SPR_DCMP (0x3D1)
1833 #define SPR_HASH1 (0x3D2)
1834 #define SPR_HASH2 (0x3D3)
1835 #define SPR_BOOKE_ICDBDR (0x3D3)
1836 #define SPR_TLBMISS (0x3D4)
1837 #define SPR_IMISS (0x3D4)
1838 #define SPR_40x_ESR (0x3D4)
1839 #define SPR_PTEHI (0x3D5)
1840 #define SPR_ICMP (0x3D5)
1841 #define SPR_40x_DEAR (0x3D5)
1842 #define SPR_PTELO (0x3D6)
1843 #define SPR_RPA (0x3D6)
1844 #define SPR_40x_EVPR (0x3D6)
1845 #define SPR_L3PM (0x3D7)
1846 #define SPR_403_CDBCR (0x3D7)
1847 #define SPR_L3ITCR0 (0x3D8)
1848 #define SPR_TCR (0x3D8)
1849 #define SPR_40x_TSR (0x3D8)
1850 #define SPR_IBR (0x3DA)
1851 #define SPR_40x_TCR (0x3DA)
1852 #define SPR_ESASRR (0x3DB)
1853 #define SPR_40x_PIT (0x3DB)
1854 #define SPR_403_TBL (0x3DC)
1855 #define SPR_403_TBU (0x3DD)
1856 #define SPR_SEBR (0x3DE)
1857 #define SPR_40x_SRR2 (0x3DE)
1858 #define SPR_SER (0x3DF)
1859 #define SPR_40x_SRR3 (0x3DF)
1860 #define SPR_L3OHCR (0x3E8)
1861 #define SPR_L3ITCR1 (0x3E9)
1862 #define SPR_L3ITCR2 (0x3EA)
1863 #define SPR_L3ITCR3 (0x3EB)
1864 #define SPR_HID0 (0x3F0)
1865 #define SPR_40x_DBSR (0x3F0)
1866 #define SPR_HID1 (0x3F1)
1867 #define SPR_IABR (0x3F2)
1868 #define SPR_40x_DBCR0 (0x3F2)
1869 #define SPR_601_HID2 (0x3F2)
1870 #define SPR_Exxx_L1CSR0 (0x3F2)
1871 #define SPR_ICTRL (0x3F3)
1872 #define SPR_HID2 (0x3F3)
1873 #define SPR_750CL_HID4 (0x3F3)
1874 #define SPR_Exxx_L1CSR1 (0x3F3)
1875 #define SPR_440_DBDR (0x3F3)
1876 #define SPR_LDSTDB (0x3F4)
1877 #define SPR_750_TDCL (0x3F4)
1878 #define SPR_40x_IAC1 (0x3F4)
1879 #define SPR_MMUCSR0 (0x3F4)
1880 #define SPR_970_HID4 (0x3F4)
1881 #define SPR_DABR (0x3F5)
1882 #define DABR_MASK (~(target_ulong)0x7)
1883 #define SPR_Exxx_BUCSR (0x3F5)
1884 #define SPR_40x_IAC2 (0x3F5)
1885 #define SPR_601_HID5 (0x3F5)
1886 #define SPR_40x_DAC1 (0x3F6)
1887 #define SPR_MSSCR0 (0x3F6)
1888 #define SPR_970_HID5 (0x3F6)
1889 #define SPR_MSSSR0 (0x3F7)
1890 #define SPR_MSSCR1 (0x3F7)
1891 #define SPR_DABRX (0x3F7)
1892 #define SPR_40x_DAC2 (0x3F7)
1893 #define SPR_MMUCFG (0x3F7)
1894 #define SPR_LDSTCR (0x3F8)
1895 #define SPR_L2PMCR (0x3F8)
1896 #define SPR_750FX_HID2 (0x3F8)
1897 #define SPR_Exxx_L1FINV0 (0x3F8)
1898 #define SPR_L2CR (0x3F9)
1899 #define SPR_L3CR (0x3FA)
1900 #define SPR_750_TDCH (0x3FA)
1901 #define SPR_IABR2 (0x3FA)
1902 #define SPR_40x_DCCR (0x3FA)
1903 #define SPR_ICTC (0x3FB)
1904 #define SPR_40x_ICCR (0x3FB)
1905 #define SPR_THRM1 (0x3FC)
1906 #define SPR_403_PBL1 (0x3FC)
1907 #define SPR_SP (0x3FD)
1908 #define SPR_THRM2 (0x3FD)
1909 #define SPR_403_PBU1 (0x3FD)
1910 #define SPR_604_HID13 (0x3FD)
1911 #define SPR_LT (0x3FE)
1912 #define SPR_THRM3 (0x3FE)
1913 #define SPR_RCPU_FPECR (0x3FE)
1914 #define SPR_403_PBL2 (0x3FE)
1915 #define SPR_PIR (0x3FF)
1916 #define SPR_403_PBU2 (0x3FF)
1917 #define SPR_601_HID15 (0x3FF)
1918 #define SPR_604_HID15 (0x3FF)
1919 #define SPR_E500_SVR (0x3FF)
1920
1921 /* Disable MAS Interrupt Updates for Hypervisor */
1922 #define EPCR_DMIUH (1 << 22)
1923 /* Disable Guest TLB Management Instructions */
1924 #define EPCR_DGTMI (1 << 23)
1925 /* Guest Interrupt Computation Mode */
1926 #define EPCR_GICM (1 << 24)
1927 /* Interrupt Computation Mode */
1928 #define EPCR_ICM (1 << 25)
1929 /* Disable Embedded Hypervisor Debug */
1930 #define EPCR_DUVD (1 << 26)
1931 /* Instruction Storage Interrupt Directed to Guest State */
1932 #define EPCR_ISIGS (1 << 27)
1933 /* Data Storage Interrupt Directed to Guest State */
1934 #define EPCR_DSIGS (1 << 28)
1935 /* Instruction TLB Error Interrupt Directed to Guest State */
1936 #define EPCR_ITLBGS (1 << 29)
1937 /* Data TLB Error Interrupt Directed to Guest State */
1938 #define EPCR_DTLBGS (1 << 30)
1939 /* External Input Interrupt Directed to Guest State */
1940 #define EPCR_EXTGS (1 << 31)
1941
1942 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1943 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1944 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1945 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1946 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1947
1948 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1949 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1950 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1951 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1952 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1953
1954 /* HID0 bits */
1955 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1956 #define HID0_DOZE (1 << 23) /* pre-2.06 */
1957 #define HID0_NAP (1 << 22) /* pre-2.06 */
1958 #define HID0_HILE PPC_BIT(19) /* POWER8 */
1959 #define HID0_POWER9_HILE PPC_BIT(4)
1960
1961 /*****************************************************************************/
1962 /* PowerPC Instructions types definitions */
1963 enum {
1964 PPC_NONE = 0x0000000000000000ULL,
1965 /* PowerPC base instructions set */
1966 PPC_INSNS_BASE = 0x0000000000000001ULL,
1967 /* integer operations instructions */
1968 #define PPC_INTEGER PPC_INSNS_BASE
1969 /* flow control instructions */
1970 #define PPC_FLOW PPC_INSNS_BASE
1971 /* virtual memory instructions */
1972 #define PPC_MEM PPC_INSNS_BASE
1973 /* ld/st with reservation instructions */
1974 #define PPC_RES PPC_INSNS_BASE
1975 /* spr/msr access instructions */
1976 #define PPC_MISC PPC_INSNS_BASE
1977 /* Deprecated instruction sets */
1978 /* Original POWER instruction set */
1979 PPC_POWER = 0x0000000000000002ULL,
1980 /* POWER2 instruction set extension */
1981 PPC_POWER2 = 0x0000000000000004ULL,
1982 /* Power RTC support */
1983 PPC_POWER_RTC = 0x0000000000000008ULL,
1984 /* Power-to-PowerPC bridge (601) */
1985 PPC_POWER_BR = 0x0000000000000010ULL,
1986 /* 64 bits PowerPC instruction set */
1987 PPC_64B = 0x0000000000000020ULL,
1988 /* New 64 bits extensions (PowerPC 2.0x) */
1989 PPC_64BX = 0x0000000000000040ULL,
1990 /* 64 bits hypervisor extensions */
1991 PPC_64H = 0x0000000000000080ULL,
1992 /* New wait instruction (PowerPC 2.0x) */
1993 PPC_WAIT = 0x0000000000000100ULL,
1994 /* Time base mftb instruction */
1995 PPC_MFTB = 0x0000000000000200ULL,
1996
1997 /* Fixed-point unit extensions */
1998 /* PowerPC 602 specific */
1999 PPC_602_SPEC = 0x0000000000000400ULL,
2000 /* isel instruction */
2001 PPC_ISEL = 0x0000000000000800ULL,
2002 /* popcntb instruction */
2003 PPC_POPCNTB = 0x0000000000001000ULL,
2004 /* string load / store */
2005 PPC_STRING = 0x0000000000002000ULL,
2006 /* real mode cache inhibited load / store */
2007 PPC_CILDST = 0x0000000000004000ULL,
2008
2009 /* Floating-point unit extensions */
2010 /* Optional floating point instructions */
2011 PPC_FLOAT = 0x0000000000010000ULL,
2012 /* New floating-point extensions (PowerPC 2.0x) */
2013 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2014 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2015 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2016 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2017 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2018 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2019 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2020
2021 /* Vector/SIMD extensions */
2022 /* Altivec support */
2023 PPC_ALTIVEC = 0x0000000001000000ULL,
2024 /* PowerPC 2.03 SPE extension */
2025 PPC_SPE = 0x0000000002000000ULL,
2026 /* PowerPC 2.03 SPE single-precision floating-point extension */
2027 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2028 /* PowerPC 2.03 SPE double-precision floating-point extension */
2029 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2030
2031 /* Optional memory control instructions */
2032 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2033 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2034 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2035 /* sync instruction */
2036 PPC_MEM_SYNC = 0x0000000080000000ULL,
2037 /* eieio instruction */
2038 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2039
2040 /* Cache control instructions */
2041 PPC_CACHE = 0x0000000200000000ULL,
2042 /* icbi instruction */
2043 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2044 /* dcbz instruction */
2045 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2046 /* dcba instruction */
2047 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2048 /* Freescale cache locking instructions */
2049 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2050
2051 /* MMU related extensions */
2052 /* external control instructions */
2053 PPC_EXTERN = 0x0000010000000000ULL,
2054 /* segment register access instructions */
2055 PPC_SEGMENT = 0x0000020000000000ULL,
2056 /* PowerPC 6xx TLB management instructions */
2057 PPC_6xx_TLB = 0x0000040000000000ULL,
2058 /* PowerPC 74xx TLB management instructions */
2059 PPC_74xx_TLB = 0x0000080000000000ULL,
2060 /* PowerPC 40x TLB management instructions */
2061 PPC_40x_TLB = 0x0000100000000000ULL,
2062 /* segment register access instructions for PowerPC 64 "bridge" */
2063 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2064 /* SLB management */
2065 PPC_SLBI = 0x0000400000000000ULL,
2066
2067 /* Embedded PowerPC dedicated instructions */
2068 PPC_WRTEE = 0x0001000000000000ULL,
2069 /* PowerPC 40x exception model */
2070 PPC_40x_EXCP = 0x0002000000000000ULL,
2071 /* PowerPC 405 Mac instructions */
2072 PPC_405_MAC = 0x0004000000000000ULL,
2073 /* PowerPC 440 specific instructions */
2074 PPC_440_SPEC = 0x0008000000000000ULL,
2075 /* BookE (embedded) PowerPC specification */
2076 PPC_BOOKE = 0x0010000000000000ULL,
2077 /* mfapidi instruction */
2078 PPC_MFAPIDI = 0x0020000000000000ULL,
2079 /* tlbiva instruction */
2080 PPC_TLBIVA = 0x0040000000000000ULL,
2081 /* tlbivax instruction */
2082 PPC_TLBIVAX = 0x0080000000000000ULL,
2083 /* PowerPC 4xx dedicated instructions */
2084 PPC_4xx_COMMON = 0x0100000000000000ULL,
2085 /* PowerPC 40x ibct instructions */
2086 PPC_40x_ICBT = 0x0200000000000000ULL,
2087 /* rfmci is not implemented in all BookE PowerPC */
2088 PPC_RFMCI = 0x0400000000000000ULL,
2089 /* rfdi instruction */
2090 PPC_RFDI = 0x0800000000000000ULL,
2091 /* DCR accesses */
2092 PPC_DCR = 0x1000000000000000ULL,
2093 /* DCR extended accesse */
2094 PPC_DCRX = 0x2000000000000000ULL,
2095 /* user-mode DCR access, implemented in PowerPC 460 */
2096 PPC_DCRUX = 0x4000000000000000ULL,
2097 /* popcntw and popcntd instructions */
2098 PPC_POPCNTWD = 0x8000000000000000ULL,
2099
2100 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2101 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2102 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2103 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2104 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2105 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2106 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2107 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2108 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2109 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2110 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2111 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2112 | PPC_CACHE | PPC_CACHE_ICBI \
2113 | PPC_CACHE_DCBZ \
2114 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2115 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2116 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2117 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2118 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2119 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2120 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2121 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2122 | PPC_POPCNTWD | PPC_CILDST)
2123
2124 /* extended type values */
2125
2126 /* BookE 2.06 PowerPC specification */
2127 PPC2_BOOKE206 = 0x0000000000000001ULL,
2128 /* VSX (extensions to Altivec / VMX) */
2129 PPC2_VSX = 0x0000000000000002ULL,
2130 /* Decimal Floating Point (DFP) */
2131 PPC2_DFP = 0x0000000000000004ULL,
2132 /* Embedded.Processor Control */
2133 PPC2_PRCNTL = 0x0000000000000008ULL,
2134 /* Byte-reversed, indexed, double-word load and store */
2135 PPC2_DBRX = 0x0000000000000010ULL,
2136 /* Book I 2.05 PowerPC specification */
2137 PPC2_ISA205 = 0x0000000000000020ULL,
2138 /* VSX additions in ISA 2.07 */
2139 PPC2_VSX207 = 0x0000000000000040ULL,
2140 /* ISA 2.06B bpermd */
2141 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2142 /* ISA 2.06B divide extended variants */
2143 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2144 /* ISA 2.06B larx/stcx. instructions */
2145 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2146 /* ISA 2.06B floating point integer conversion */
2147 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2148 /* ISA 2.06B floating point test instructions */
2149 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2150 /* ISA 2.07 bctar instruction */
2151 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2152 /* ISA 2.07 load/store quadword */
2153 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2154 /* ISA 2.07 Altivec */
2155 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2156 /* PowerISA 2.07 Book3s specification */
2157 PPC2_ISA207S = 0x0000000000008000ULL,
2158 /* Double precision floating point conversion for signed integer 64 */
2159 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2160 /* Transactional Memory (ISA 2.07, Book II) */
2161 PPC2_TM = 0x0000000000020000ULL,
2162 /* Server PM instructgions (ISA 2.06, Book III) */
2163 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2164 /* POWER ISA 3.0 */
2165 PPC2_ISA300 = 0x0000000000080000ULL,
2166
2167 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2168 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2169 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2170 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2171 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2172 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2173 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2174 PPC2_ISA300)
2175 };
2176
2177 /*****************************************************************************/
2178 /*
2179 * Memory access type :
2180 * may be needed for precise access rights control and precise exceptions.
2181 */
2182 enum {
2183 /* 1 bit to define user level / supervisor access */
2184 ACCESS_USER = 0x00,
2185 ACCESS_SUPER = 0x01,
2186 /* Type of instruction that generated the access */
2187 ACCESS_CODE = 0x10, /* Code fetch access */
2188 ACCESS_INT = 0x20, /* Integer load/store access */
2189 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2190 ACCESS_RES = 0x40, /* load/store with reservation */
2191 ACCESS_EXT = 0x50, /* external access */
2192 ACCESS_CACHE = 0x60, /* Cache manipulation */
2193 };
2194
2195 /*
2196 * Hardware interrupt sources:
2197 * all those exception can be raised simulteaneously
2198 */
2199 /* Input pins definitions */
2200 enum {
2201 /* 6xx bus input pins */
2202 PPC6xx_INPUT_HRESET = 0,
2203 PPC6xx_INPUT_SRESET = 1,
2204 PPC6xx_INPUT_CKSTP_IN = 2,
2205 PPC6xx_INPUT_MCP = 3,
2206 PPC6xx_INPUT_SMI = 4,
2207 PPC6xx_INPUT_INT = 5,
2208 PPC6xx_INPUT_TBEN = 6,
2209 PPC6xx_INPUT_WAKEUP = 7,
2210 PPC6xx_INPUT_NB,
2211 };
2212
2213 enum {
2214 /* Embedded PowerPC input pins */
2215 PPCBookE_INPUT_HRESET = 0,
2216 PPCBookE_INPUT_SRESET = 1,
2217 PPCBookE_INPUT_CKSTP_IN = 2,
2218 PPCBookE_INPUT_MCP = 3,
2219 PPCBookE_INPUT_SMI = 4,
2220 PPCBookE_INPUT_INT = 5,
2221 PPCBookE_INPUT_CINT = 6,
2222 PPCBookE_INPUT_NB,
2223 };
2224
2225 enum {
2226 /* PowerPC E500 input pins */
2227 PPCE500_INPUT_RESET_CORE = 0,
2228 PPCE500_INPUT_MCK = 1,
2229 PPCE500_INPUT_CINT = 3,
2230 PPCE500_INPUT_INT = 4,
2231 PPCE500_INPUT_DEBUG = 6,
2232 PPCE500_INPUT_NB,
2233 };
2234
2235 enum {
2236 /* PowerPC 40x input pins */
2237 PPC40x_INPUT_RESET_CORE = 0,
2238 PPC40x_INPUT_RESET_CHIP = 1,
2239 PPC40x_INPUT_RESET_SYS = 2,
2240 PPC40x_INPUT_CINT = 3,
2241 PPC40x_INPUT_INT = 4,
2242 PPC40x_INPUT_HALT = 5,
2243 PPC40x_INPUT_DEBUG = 6,
2244 PPC40x_INPUT_NB,
2245 };
2246
2247 enum {
2248 /* RCPU input pins */
2249 PPCRCPU_INPUT_PORESET = 0,
2250 PPCRCPU_INPUT_HRESET = 1,
2251 PPCRCPU_INPUT_SRESET = 2,
2252 PPCRCPU_INPUT_IRQ0 = 3,
2253 PPCRCPU_INPUT_IRQ1 = 4,
2254 PPCRCPU_INPUT_IRQ2 = 5,
2255 PPCRCPU_INPUT_IRQ3 = 6,
2256 PPCRCPU_INPUT_IRQ4 = 7,
2257 PPCRCPU_INPUT_IRQ5 = 8,
2258 PPCRCPU_INPUT_IRQ6 = 9,
2259 PPCRCPU_INPUT_IRQ7 = 10,
2260 PPCRCPU_INPUT_NB,
2261 };
2262
2263 #if defined(TARGET_PPC64)
2264 enum {
2265 /* PowerPC 970 input pins */
2266 PPC970_INPUT_HRESET = 0,
2267 PPC970_INPUT_SRESET = 1,
2268 PPC970_INPUT_CKSTP = 2,
2269 PPC970_INPUT_TBEN = 3,
2270 PPC970_INPUT_MCP = 4,
2271 PPC970_INPUT_INT = 5,
2272 PPC970_INPUT_THINT = 6,
2273 PPC970_INPUT_NB,
2274 };
2275
2276 enum {
2277 /* POWER7 input pins */
2278 POWER7_INPUT_INT = 0,
2279 /*
2280 * POWER7 probably has other inputs, but we don't care about them
2281 * for any existing machine. We can wire these up when we need
2282 * them
2283 */
2284 POWER7_INPUT_NB,
2285 };
2286
2287 enum {
2288 /* POWER9 input pins */
2289 POWER9_INPUT_INT = 0,
2290 POWER9_INPUT_HINT = 1,
2291 POWER9_INPUT_NB,
2292 };
2293 #endif
2294
2295 /* Hardware exceptions definitions */
2296 enum {
2297 /* External hardware exception sources */
2298 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2299 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2300 PPC_INTERRUPT_MCK, /* Machine check exception */
2301 PPC_INTERRUPT_EXT, /* External interrupt */
2302 PPC_INTERRUPT_SMI, /* System management interrupt */
2303 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2304 PPC_INTERRUPT_DEBUG, /* External debug exception */
2305 PPC_INTERRUPT_THERM, /* Thermal exception */
2306 /* Internal hardware exception sources */
2307 PPC_INTERRUPT_DECR, /* Decrementer exception */
2308 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2309 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2310 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2311 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2312 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2313 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2314 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2315 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2316 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
2317 PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
2318 };
2319
2320 /* Processor Compatibility mask (PCR) */
2321 enum {
2322 PCR_COMPAT_2_05 = PPC_BIT(62),
2323 PCR_COMPAT_2_06 = PPC_BIT(61),
2324 PCR_COMPAT_2_07 = PPC_BIT(60),
2325 PCR_COMPAT_3_00 = PPC_BIT(59),
2326 PCR_COMPAT_3_10 = PPC_BIT(58),
2327 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2328 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2329 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2330 };
2331
2332 /* HMER/HMEER */
2333 enum {
2334 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2335 HMER_PROC_RECV_DONE = PPC_BIT(2),
2336 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2337 HMER_TFAC_ERROR = PPC_BIT(4),
2338 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2339 HMER_XSCOM_FAIL = PPC_BIT(8),
2340 HMER_XSCOM_DONE = PPC_BIT(9),
2341 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2342 HMER_WARN_RISE = PPC_BIT(14),
2343 HMER_WARN_FALL = PPC_BIT(15),
2344 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2345 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2346 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2347 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2348 };
2349
2350 /* Alternate Interrupt Location (AIL) */
2351 enum {
2352 AIL_NONE = 0,
2353 AIL_RESERVED = 1,
2354 AIL_0001_8000 = 2,
2355 AIL_C000_0000_0000_4000 = 3,
2356 };
2357
2358 /*****************************************************************************/
2359
2360 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2361 target_ulong cpu_read_xer(CPUPPCState *env);
2362 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2363
2364 /*
2365 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2366 * have PPC_SEGMENT_64B.
2367 */
2368 #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2369
cpu_get_tb_cpu_state(CPUPPCState * env,target_ulong * pc,target_ulong * cs_base,uint32_t * flags)2370 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2371 target_ulong *cs_base, uint32_t *flags)
2372 {
2373 *pc = env->nip;
2374 *cs_base = 0;
2375 *flags = env->hflags;
2376 }
2377
2378 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2379 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2380 uintptr_t raddr);
2381 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2382 uint32_t error_code);
2383 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2384 uint32_t error_code, uintptr_t raddr);
2385
2386 #if !defined(CONFIG_USER_ONLY)
booke206_tlbm_id(CPUPPCState * env,ppcmas_tlb_t * tlbm)2387 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2388 {
2389 uintptr_t tlbml = (uintptr_t)tlbm;
2390 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2391
2392 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2393 }
2394
booke206_tlb_size(CPUPPCState * env,int tlbn)2395 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2396 {
2397 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2398 int r = tlbncfg & TLBnCFG_N_ENTRY;
2399 return r;
2400 }
2401
booke206_tlb_ways(CPUPPCState * env,int tlbn)2402 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2403 {
2404 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2405 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2406 return r;
2407 }
2408
booke206_tlbm_to_tlbn(CPUPPCState * env,ppcmas_tlb_t * tlbm)2409 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2410 {
2411 int id = booke206_tlbm_id(env, tlbm);
2412 int end = 0;
2413 int i;
2414
2415 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2416 end += booke206_tlb_size(env, i);
2417 if (id < end) {
2418 return i;
2419 }
2420 }
2421
2422 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
2423 return 0;
2424 }
2425
booke206_tlbm_to_way(CPUPPCState * env,ppcmas_tlb_t * tlb)2426 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2427 {
2428 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2429 int tlbid = booke206_tlbm_id(env, tlb);
2430 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2431 }
2432
booke206_get_tlbm(CPUPPCState * env,const int tlbn,target_ulong ea,int way)2433 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2434 target_ulong ea, int way)
2435 {
2436 int r;
2437 uint32_t ways = booke206_tlb_ways(env, tlbn);
2438 int ways_bits = ctz32(ways);
2439 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2440 int i;
2441
2442 way &= ways - 1;
2443 ea >>= MAS2_EPN_SHIFT;
2444 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2445 r = (ea << ways_bits) | way;
2446
2447 if (r >= booke206_tlb_size(env, tlbn)) {
2448 return NULL;
2449 }
2450
2451 /* bump up to tlbn index */
2452 for (i = 0; i < tlbn; i++) {
2453 r += booke206_tlb_size(env, i);
2454 }
2455
2456 return &env->tlb.tlbm[r];
2457 }
2458
2459 /* returns bitmap of supported page sizes for a given TLB */
booke206_tlbnps(CPUPPCState * env,const int tlbn)2460 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2461 {
2462 uint32_t ret = 0;
2463
2464 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2465 /* MAV2 */
2466 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2467 } else {
2468 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2469 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2470 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2471 int i;
2472 for (i = min; i <= max; i++) {
2473 ret |= (1 << (i << 1));
2474 }
2475 }
2476
2477 return ret;
2478 }
2479
booke206_fixed_size_tlbn(CPUPPCState * env,const int tlbn,ppcmas_tlb_t * tlb)2480 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2481 ppcmas_tlb_t *tlb)
2482 {
2483 uint8_t i;
2484 int32_t tsize = -1;
2485
2486 for (i = 0; i < 32; i++) {
2487 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2488 if (tsize == -1) {
2489 tsize = i;
2490 } else {
2491 return;
2492 }
2493 }
2494 }
2495
2496 /* TLBnPS unimplemented? Odd.. */
2497 assert(tsize != -1);
2498 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2499 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2500 }
2501
2502 #endif
2503
msr_is_64bit(CPUPPCState * env,target_ulong msr)2504 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2505 {
2506 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2507 return msr & (1ULL << MSR_CM);
2508 }
2509
2510 return msr & (1ULL << MSR_SF);
2511 }
2512
2513 /**
2514 * Check whether register rx is in the range between start and
2515 * start + nregs (as needed by the LSWX and LSWI instructions)
2516 */
lsw_reg_in_range(int start,int nregs,int rx)2517 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2518 {
2519 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2520 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2521 }
2522
2523 /* Accessors for FP, VMX and VSX registers */
2524 #if defined(HOST_WORDS_BIGENDIAN)
2525 #define VsrB(i) u8[i]
2526 #define VsrSB(i) s8[i]
2527 #define VsrH(i) u16[i]
2528 #define VsrSH(i) s16[i]
2529 #define VsrW(i) u32[i]
2530 #define VsrSW(i) s32[i]
2531 #define VsrD(i) u64[i]
2532 #define VsrSD(i) s64[i]
2533 #else
2534 #define VsrB(i) u8[15 - (i)]
2535 #define VsrSB(i) s8[15 - (i)]
2536 #define VsrH(i) u16[7 - (i)]
2537 #define VsrSH(i) s16[7 - (i)]
2538 #define VsrW(i) u32[3 - (i)]
2539 #define VsrSW(i) s32[3 - (i)]
2540 #define VsrD(i) u64[1 - (i)]
2541 #define VsrSD(i) s64[1 - (i)]
2542 #endif
2543
vsr64_offset(int i,bool high)2544 static inline int vsr64_offset(int i, bool high)
2545 {
2546 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
2547 }
2548
vsr_full_offset(int i)2549 static inline int vsr_full_offset(int i)
2550 {
2551 return offsetof(CPUPPCState, vsr[i].u64[0]);
2552 }
2553
fpr_offset(int i)2554 static inline int fpr_offset(int i)
2555 {
2556 return vsr64_offset(i, true);
2557 }
2558
cpu_fpr_ptr(CPUPPCState * env,int i)2559 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
2560 {
2561 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
2562 }
2563
cpu_vsrl_ptr(CPUPPCState * env,int i)2564 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2565 {
2566 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
2567 }
2568
avr64_offset(int i,bool high)2569 static inline long avr64_offset(int i, bool high)
2570 {
2571 return vsr64_offset(i + 32, high);
2572 }
2573
avr_full_offset(int i)2574 static inline int avr_full_offset(int i)
2575 {
2576 return vsr_full_offset(i + 32);
2577 }
2578
cpu_avr_ptr(CPUPPCState * env,int i)2579 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2580 {
2581 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
2582 }
2583
2584 void dump_mmu(CPUPPCState *env);
2585
2586 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2587 #endif /* PPC_CPU_H */
2588