1 /*
2 * (C) Copyright 2004, Freescale, Inc
3 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25 /*
26 * Minimal serial functions needed to use one of the PSC ports
27 * as serial console interface.
28 */
29
30 #include <common.h>
31 #include <mpc8220.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define PSC_BASE MMAP_PSC1
36
37 #if defined(CONFIG_PSC_CONSOLE)
serial_init(void)38 int serial_init (void)
39 {
40 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
41 u32 counter;
42
43 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
44 psc->cr = 0;
45 psc->ipcr_acr = 0;
46 psc->isr_imr = 0;
47
48 /* write to CSR: RX/TX baud rate from timers */
49 psc->sr_csr = 0xdd000000;
50
51 psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;
52
53 /* Setting up BaudRate */
54 counter = ((gd->bus_clk / gd->baudrate)) >> 5;
55 counter++;
56
57 /* write to CTUR: divide counter upper byte */
58 psc->ctur = ((counter & 0xff00) << 16);
59 /* write to CTLR: divide counter lower byte */
60 psc->ctlr = ((counter & 0x00ff) << 24);
61
62 psc->cr = PSC_CR_RST_RX_CMD;
63 psc->cr = PSC_CR_RST_TX_CMD;
64 psc->cr = PSC_CR_RST_ERR_STS_CMD;
65 psc->cr = PSC_CR_RST_BRK_INT_CMD;
66 psc->cr = PSC_CR_RST_MR_PTR_CMD;
67
68 psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
69 return (0);
70 }
71
serial_putc(const char c)72 void serial_putc (const char c)
73 {
74 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
75
76 if (c == '\n')
77 serial_putc ('\r');
78
79 /* Wait for last character to go. */
80 while (!(psc->sr_csr & PSC_SR_TXRDY));
81
82 psc->xmitbuf[0] = c;
83 }
84
serial_puts(const char * s)85 void serial_puts (const char *s)
86 {
87 while (*s) {
88 serial_putc (*s++);
89 }
90 }
91
serial_getc(void)92 int serial_getc (void)
93 {
94 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
95
96 /* Wait for a character to arrive. */
97 while (!(psc->sr_csr & PSC_SR_RXRDY));
98 return psc->xmitbuf[2];
99 }
100
serial_tstc(void)101 int serial_tstc (void)
102 {
103 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
104
105 return (psc->sr_csr & PSC_SR_RXRDY);
106 }
107
serial_setbrg(void)108 void serial_setbrg (void)
109 {
110 volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
111 u32 counter;
112
113 counter = ((gd->bus_clk / gd->baudrate)) >> 5;
114 counter++;
115
116 /* write to CTUR: divide counter upper byte */
117 psc->ctur = ((counter & 0xff00) << 16);
118 /* write to CTLR: divide counter lower byte */
119 psc->ctlr = ((counter & 0x00ff) << 24);
120
121 psc->cr = PSC_CR_RST_RX_CMD;
122 psc->cr = PSC_CR_RST_TX_CMD;
123
124 psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
125 }
126 #endif /* CONFIG_PSC_CONSOLE */
127