1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "exec/memory.h"
5 #include "sysemu/dma.h"
6
7 /* PCI includes legacy ISA access. */
8 #include "hw/isa/isa.h"
9
10 #include "hw/pci/pcie.h"
11
12 extern bool pci_available;
13
14 /* PCI bus */
15
16 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
17 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
21 #define PCI_BUS_MAX 256
22 #define PCI_DEVFN_MAX 256
23 #define PCI_SLOT_MAX 32
24 #define PCI_FUNC_MAX 8
25
26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
27 #include "hw/pci/pci_ids.h"
28
29 /* QEMU-specific Vendor and Device ID definitions */
30
31 /* IBM (0x1014) */
32 #define PCI_DEVICE_ID_IBM_440GX 0x027f
33 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
34
35 /* Hitachi (0x1054) */
36 #define PCI_VENDOR_ID_HITACHI 0x1054
37 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
38
39 /* Apple (0x106b) */
40 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
44 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
45
46 /* Realtek (0x10ec) */
47 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
48
49 /* Xilinx (0x10ee) */
50 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
51
52 /* Marvell (0x11ab) */
53 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
54
55 /* QEMU/Bochs VGA (0x1234) */
56 #define PCI_VENDOR_ID_QEMU 0x1234
57 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
58 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112
59
60 /* VMWare (0x15ad) */
61 #define PCI_VENDOR_ID_VMWARE 0x15ad
62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
69
70 /* Intel (0x8086) */
71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
72 #define PCI_DEVICE_ID_INTEL_82557 0x1229
73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
74
75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
78 #define PCI_SUBDEVICE_ID_QEMU 0x1100
79
80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
88 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
89
90 #define PCI_VENDOR_ID_REDHAT 0x1b36
91 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
92 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
93 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
94 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
95 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
96 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
97 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
98 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
99 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
100 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
101 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
102 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
103 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
104 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
105 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
106 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
107
108 #define FMT_PCIBUS PRIx64
109
110 typedef uint64_t pcibus_t;
111
112 struct PCIHostDeviceAddress {
113 unsigned int domain;
114 unsigned int bus;
115 unsigned int slot;
116 unsigned int function;
117 };
118
119 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
120 uint32_t address, uint32_t data, int len);
121 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
122 uint32_t address, int len);
123 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
124 pcibus_t addr, pcibus_t size, int type);
125 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
126
127 typedef struct PCIIORegion {
128 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
129 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
130 pcibus_t size;
131 uint8_t type;
132 MemoryRegion *memory;
133 MemoryRegion *address_space;
134 } PCIIORegion;
135
136 #define PCI_ROM_SLOT 6
137 #define PCI_NUM_REGIONS 7
138
139 enum {
140 QEMU_PCI_VGA_MEM,
141 QEMU_PCI_VGA_IO_LO,
142 QEMU_PCI_VGA_IO_HI,
143 QEMU_PCI_VGA_NUM_REGIONS,
144 };
145
146 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
147 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
148 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
149 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
150 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
151 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
152
153 #include "hw/pci/pci_regs.h"
154
155 /* PCI HEADER_TYPE */
156 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
157
158 /* Size of the standard PCI config header */
159 #define PCI_CONFIG_HEADER_SIZE 0x40
160 /* Size of the standard PCI config space */
161 #define PCI_CONFIG_SPACE_SIZE 0x100
162 /* Size of the standard PCIe config space: 4KB */
163 #define PCIE_CONFIG_SPACE_SIZE 0x1000
164
165 #define PCI_NUM_PINS 4 /* A-D */
166
167 /* Bits in cap_present field. */
168 enum {
169 QEMU_PCI_CAP_MSI = 0x1,
170 QEMU_PCI_CAP_MSIX = 0x2,
171 QEMU_PCI_CAP_EXPRESS = 0x4,
172
173 /* multifunction capable device */
174 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
175 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
176
177 /* command register SERR bit enabled */
178 #define QEMU_PCI_CAP_SERR_BITNR 4
179 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
180 /* Standard hot plug controller. */
181 #define QEMU_PCI_SHPC_BITNR 5
182 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
183 #define QEMU_PCI_SLOTID_BITNR 6
184 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
185 /* PCI Express capability - Power Controller Present */
186 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
187 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
188 /* Link active status in endpoint capability is always set */
189 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
190 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
191 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
192 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
193 };
194
195 #define TYPE_PCI_DEVICE "pci-device"
196 #define PCI_DEVICE(obj) \
197 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
198 #define PCI_DEVICE_CLASS(klass) \
199 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
200 #define PCI_DEVICE_GET_CLASS(obj) \
201 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
202
203 /* Implemented by devices that can be plugged on PCI Express buses */
204 #define INTERFACE_PCIE_DEVICE "pci-express-device"
205
206 /* Implemented by devices that can be plugged on Conventional PCI buses */
207 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
208
209 typedef struct PCIINTxRoute {
210 enum {
211 PCI_INTX_ENABLED,
212 PCI_INTX_INVERTED,
213 PCI_INTX_DISABLED,
214 } mode;
215 int irq;
216 } PCIINTxRoute;
217
218 typedef struct PCIDeviceClass {
219 DeviceClass parent_class;
220
221 void (*realize)(PCIDevice *dev, Error **errp);
222 PCIUnregisterFunc *exit;
223 PCIConfigReadFunc *config_read;
224 PCIConfigWriteFunc *config_write;
225
226 uint16_t vendor_id;
227 uint16_t device_id;
228 uint8_t revision;
229 uint16_t class_id;
230 uint16_t subsystem_vendor_id; /* only for header type = 0 */
231 uint16_t subsystem_id; /* only for header type = 0 */
232
233 /*
234 * pci-to-pci bridge or normal device.
235 * This doesn't mean pci host switch.
236 * When card bus bridge is supported, this would be enhanced.
237 */
238 bool is_bridge;
239
240 /* rom bar */
241 const char *romfile;
242 } PCIDeviceClass;
243
244 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
245 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
246 MSIMessage msg);
247 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
248 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
249 unsigned int vector_start,
250 unsigned int vector_end);
251
252 enum PCIReqIDType {
253 PCI_REQ_ID_INVALID = 0,
254 PCI_REQ_ID_BDF,
255 PCI_REQ_ID_SECONDARY_BUS,
256 PCI_REQ_ID_MAX,
257 };
258 typedef enum PCIReqIDType PCIReqIDType;
259
260 struct PCIReqIDCache {
261 PCIDevice *dev;
262 PCIReqIDType type;
263 };
264 typedef struct PCIReqIDCache PCIReqIDCache;
265
266 struct PCIDevice {
267 DeviceState qdev;
268 bool partially_hotplugged;
269
270 /* PCI config space */
271 uint8_t *config;
272
273 /* Used to enable config checks on load. Note that writable bits are
274 * never checked even if set in cmask. */
275 uint8_t *cmask;
276
277 /* Used to implement R/W bytes */
278 uint8_t *wmask;
279
280 /* Used to implement RW1C(Write 1 to Clear) bytes */
281 uint8_t *w1cmask;
282
283 /* Used to allocate config space for capabilities. */
284 uint8_t *used;
285
286 /* the following fields are read only */
287 int32_t devfn;
288 /* Cached device to fetch requester ID from, to avoid the PCI
289 * tree walking every time we invoke PCI request (e.g.,
290 * MSI). For conventional PCI root complex, this field is
291 * meaningless. */
292 PCIReqIDCache requester_id_cache;
293 char name[64];
294 PCIIORegion io_regions[PCI_NUM_REGIONS];
295 AddressSpace bus_master_as;
296 MemoryRegion bus_master_container_region;
297 MemoryRegion bus_master_enable_region;
298
299 /* do not access the following fields */
300 PCIConfigReadFunc *config_read;
301 PCIConfigWriteFunc *config_write;
302
303 /* Legacy PCI VGA regions */
304 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
305 bool has_vga;
306
307 /* Current IRQ levels. Used internally by the generic PCI code. */
308 uint8_t irq_state;
309
310 /* Capability bits */
311 uint32_t cap_present;
312
313 /* Offset of MSI-X capability in config space */
314 uint8_t msix_cap;
315
316 /* MSI-X entries */
317 int msix_entries_nr;
318
319 /* Space to store MSIX table & pending bit array */
320 uint8_t *msix_table;
321 uint8_t *msix_pba;
322 /* MemoryRegion container for msix exclusive BAR setup */
323 MemoryRegion msix_exclusive_bar;
324 /* Memory Regions for MSIX table and pending bit entries. */
325 MemoryRegion msix_table_mmio;
326 MemoryRegion msix_pba_mmio;
327 /* Reference-count for entries actually in use by driver. */
328 unsigned *msix_entry_used;
329 /* MSIX function mask set or MSIX disabled */
330 bool msix_function_masked;
331 /* Version id needed for VMState */
332 int32_t version_id;
333
334 /* Offset of MSI capability in config space */
335 uint8_t msi_cap;
336
337 /* PCI Express */
338 PCIExpressDevice exp;
339
340 /* SHPC */
341 SHPCDevice *shpc;
342
343 /* Location of option rom */
344 char *romfile;
345 bool has_rom;
346 MemoryRegion rom;
347 uint32_t rom_bar;
348
349 /* INTx routing notifier */
350 PCIINTxRoutingNotifier intx_routing_notifier;
351
352 /* MSI-X notifiers */
353 MSIVectorUseNotifier msix_vector_use_notifier;
354 MSIVectorReleaseNotifier msix_vector_release_notifier;
355 MSIVectorPollNotifier msix_vector_poll_notifier;
356
357 /* ID of standby device in net_failover pair */
358 char *failover_pair_id;
359 };
360
361 void pci_register_bar(PCIDevice *pci_dev, int region_num,
362 uint8_t attr, MemoryRegion *memory);
363 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
364 MemoryRegion *io_lo, MemoryRegion *io_hi);
365 void pci_unregister_vga(PCIDevice *pci_dev);
366 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
367
368 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
369 uint8_t offset, uint8_t size,
370 Error **errp);
371
372 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
373
374 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
375
376
377 uint32_t pci_default_read_config(PCIDevice *d,
378 uint32_t address, int len);
379 void pci_default_write_config(PCIDevice *d,
380 uint32_t address, uint32_t val, int len);
381 void pci_device_save(PCIDevice *s, QEMUFile *f);
382 int pci_device_load(PCIDevice *s, QEMUFile *f);
383 MemoryRegion *pci_address_space(PCIDevice *dev);
384 MemoryRegion *pci_address_space_io(PCIDevice *dev);
385
386 /*
387 * Should not normally be used by devices. For use by sPAPR target
388 * where QEMU emulates firmware.
389 */
390 int pci_bar(PCIDevice *d, int reg);
391
392 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
393 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
394 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
395
396 #define TYPE_PCI_BUS "PCI"
397 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
398 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
399 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
400 #define TYPE_PCIE_BUS "PCIE"
401
402 bool pci_bus_is_express(PCIBus *bus);
403
404 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
405 const char *name,
406 MemoryRegion *address_space_mem,
407 MemoryRegion *address_space_io,
408 uint8_t devfn_min, const char *typename);
409 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
410 MemoryRegion *address_space_mem,
411 MemoryRegion *address_space_io,
412 uint8_t devfn_min, const char *typename);
413 void pci_root_bus_cleanup(PCIBus *bus);
414 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
415 void *irq_opaque, int nirq);
416 void pci_bus_irqs_cleanup(PCIBus *bus);
417 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
418 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
pci_swizzle(int slot,int pin)419 static inline int pci_swizzle(int slot, int pin)
420 {
421 return (slot + pin) % PCI_NUM_PINS;
422 }
423 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
424 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
425 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
426 void *irq_opaque,
427 MemoryRegion *address_space_mem,
428 MemoryRegion *address_space_io,
429 uint8_t devfn_min, int nirq,
430 const char *typename);
431 void pci_unregister_root_bus(PCIBus *bus);
432 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
433 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
434 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
435 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
436 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
437 PCIINTxRoutingNotifier notifier);
438 void pci_device_reset(PCIDevice *dev);
439
440 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
441 const char *default_model,
442 const char *default_devaddr);
443
444 PCIDevice *pci_vga_init(PCIBus *bus);
445
pci_get_bus(const PCIDevice * dev)446 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
447 {
448 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
449 }
450 int pci_bus_num(PCIBus *s);
pci_dev_bus_num(const PCIDevice * dev)451 static inline int pci_dev_bus_num(const PCIDevice *dev)
452 {
453 return pci_bus_num(pci_get_bus(dev));
454 }
455
456 int pci_bus_numa_node(PCIBus *bus);
457 void pci_for_each_device(PCIBus *bus, int bus_num,
458 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
459 void *opaque);
460 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
461 void (*fn)(PCIBus *bus, PCIDevice *d,
462 void *opaque),
463 void *opaque);
464 void pci_for_each_bus_depth_first(PCIBus *bus,
465 void *(*begin)(PCIBus *bus, void *parent_state),
466 void (*end)(PCIBus *bus, void *state),
467 void *parent_state);
468 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
469
470 /* Use this wrapper when specific scan order is not required. */
471 static inline
pci_for_each_bus(PCIBus * bus,void (* fn)(PCIBus * bus,void * opaque),void * opaque)472 void pci_for_each_bus(PCIBus *bus,
473 void (*fn)(PCIBus *bus, void *opaque),
474 void *opaque)
475 {
476 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
477 }
478
479 PCIBus *pci_device_root_bus(const PCIDevice *d);
480 const char *pci_root_bus_path(PCIDevice *dev);
481 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
482 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
483 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
484
485 void pci_device_deassert_intx(PCIDevice *dev);
486
487 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
488
489 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
490 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
491
492 static inline void
pci_set_byte(uint8_t * config,uint8_t val)493 pci_set_byte(uint8_t *config, uint8_t val)
494 {
495 *config = val;
496 }
497
498 static inline uint8_t
pci_get_byte(const uint8_t * config)499 pci_get_byte(const uint8_t *config)
500 {
501 return *config;
502 }
503
504 static inline void
pci_set_word(uint8_t * config,uint16_t val)505 pci_set_word(uint8_t *config, uint16_t val)
506 {
507 stw_le_p(config, val);
508 }
509
510 static inline uint16_t
pci_get_word(const uint8_t * config)511 pci_get_word(const uint8_t *config)
512 {
513 return lduw_le_p(config);
514 }
515
516 static inline void
pci_set_long(uint8_t * config,uint32_t val)517 pci_set_long(uint8_t *config, uint32_t val)
518 {
519 stl_le_p(config, val);
520 }
521
522 static inline uint32_t
pci_get_long(const uint8_t * config)523 pci_get_long(const uint8_t *config)
524 {
525 return ldl_le_p(config);
526 }
527
528 /*
529 * PCI capabilities and/or their fields
530 * are generally DWORD aligned only so
531 * mechanism used by pci_set/get_quad()
532 * must be tolerant to unaligned pointers
533 *
534 */
535 static inline void
pci_set_quad(uint8_t * config,uint64_t val)536 pci_set_quad(uint8_t *config, uint64_t val)
537 {
538 stq_le_p(config, val);
539 }
540
541 static inline uint64_t
pci_get_quad(const uint8_t * config)542 pci_get_quad(const uint8_t *config)
543 {
544 return ldq_le_p(config);
545 }
546
547 static inline void
pci_config_set_vendor_id(uint8_t * pci_config,uint16_t val)548 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
549 {
550 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
551 }
552
553 static inline void
pci_config_set_device_id(uint8_t * pci_config,uint16_t val)554 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
555 {
556 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
557 }
558
559 static inline void
pci_config_set_revision(uint8_t * pci_config,uint8_t val)560 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
561 {
562 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
563 }
564
565 static inline void
pci_config_set_class(uint8_t * pci_config,uint16_t val)566 pci_config_set_class(uint8_t *pci_config, uint16_t val)
567 {
568 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
569 }
570
571 static inline void
pci_config_set_prog_interface(uint8_t * pci_config,uint8_t val)572 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
573 {
574 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
575 }
576
577 static inline void
pci_config_set_interrupt_pin(uint8_t * pci_config,uint8_t val)578 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
579 {
580 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
581 }
582
583 /*
584 * helper functions to do bit mask operation on configuration space.
585 * Just to set bit, use test-and-set and discard returned value.
586 * Just to clear bit, use test-and-clear and discard returned value.
587 * NOTE: They aren't atomic.
588 */
589 static inline uint8_t
pci_byte_test_and_clear_mask(uint8_t * config,uint8_t mask)590 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
591 {
592 uint8_t val = pci_get_byte(config);
593 pci_set_byte(config, val & ~mask);
594 return val & mask;
595 }
596
597 static inline uint8_t
pci_byte_test_and_set_mask(uint8_t * config,uint8_t mask)598 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
599 {
600 uint8_t val = pci_get_byte(config);
601 pci_set_byte(config, val | mask);
602 return val & mask;
603 }
604
605 static inline uint16_t
pci_word_test_and_clear_mask(uint8_t * config,uint16_t mask)606 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
607 {
608 uint16_t val = pci_get_word(config);
609 pci_set_word(config, val & ~mask);
610 return val & mask;
611 }
612
613 static inline uint16_t
pci_word_test_and_set_mask(uint8_t * config,uint16_t mask)614 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
615 {
616 uint16_t val = pci_get_word(config);
617 pci_set_word(config, val | mask);
618 return val & mask;
619 }
620
621 static inline uint32_t
pci_long_test_and_clear_mask(uint8_t * config,uint32_t mask)622 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
623 {
624 uint32_t val = pci_get_long(config);
625 pci_set_long(config, val & ~mask);
626 return val & mask;
627 }
628
629 static inline uint32_t
pci_long_test_and_set_mask(uint8_t * config,uint32_t mask)630 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
631 {
632 uint32_t val = pci_get_long(config);
633 pci_set_long(config, val | mask);
634 return val & mask;
635 }
636
637 static inline uint64_t
pci_quad_test_and_clear_mask(uint8_t * config,uint64_t mask)638 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
639 {
640 uint64_t val = pci_get_quad(config);
641 pci_set_quad(config, val & ~mask);
642 return val & mask;
643 }
644
645 static inline uint64_t
pci_quad_test_and_set_mask(uint8_t * config,uint64_t mask)646 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
647 {
648 uint64_t val = pci_get_quad(config);
649 pci_set_quad(config, val | mask);
650 return val & mask;
651 }
652
653 /* Access a register specified by a mask */
654 static inline void
pci_set_byte_by_mask(uint8_t * config,uint8_t mask,uint8_t reg)655 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
656 {
657 uint8_t val = pci_get_byte(config);
658 uint8_t rval = reg << ctz32(mask);
659 pci_set_byte(config, (~mask & val) | (mask & rval));
660 }
661
662 static inline uint8_t
pci_get_byte_by_mask(uint8_t * config,uint8_t mask)663 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
664 {
665 uint8_t val = pci_get_byte(config);
666 return (val & mask) >> ctz32(mask);
667 }
668
669 static inline void
pci_set_word_by_mask(uint8_t * config,uint16_t mask,uint16_t reg)670 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
671 {
672 uint16_t val = pci_get_word(config);
673 uint16_t rval = reg << ctz32(mask);
674 pci_set_word(config, (~mask & val) | (mask & rval));
675 }
676
677 static inline uint16_t
pci_get_word_by_mask(uint8_t * config,uint16_t mask)678 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
679 {
680 uint16_t val = pci_get_word(config);
681 return (val & mask) >> ctz32(mask);
682 }
683
684 static inline void
pci_set_long_by_mask(uint8_t * config,uint32_t mask,uint32_t reg)685 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
686 {
687 uint32_t val = pci_get_long(config);
688 uint32_t rval = reg << ctz32(mask);
689 pci_set_long(config, (~mask & val) | (mask & rval));
690 }
691
692 static inline uint32_t
pci_get_long_by_mask(uint8_t * config,uint32_t mask)693 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
694 {
695 uint32_t val = pci_get_long(config);
696 return (val & mask) >> ctz32(mask);
697 }
698
699 static inline void
pci_set_quad_by_mask(uint8_t * config,uint64_t mask,uint64_t reg)700 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
701 {
702 uint64_t val = pci_get_quad(config);
703 uint64_t rval = reg << ctz32(mask);
704 pci_set_quad(config, (~mask & val) | (mask & rval));
705 }
706
707 static inline uint64_t
pci_get_quad_by_mask(uint8_t * config,uint64_t mask)708 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
709 {
710 uint64_t val = pci_get_quad(config);
711 return (val & mask) >> ctz32(mask);
712 }
713
714 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
715 const char *name);
716 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
717 bool multifunction,
718 const char *name);
719 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
720 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
721
722 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
723
724 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
725 void pci_set_irq(PCIDevice *pci_dev, int level);
726
pci_irq_assert(PCIDevice * pci_dev)727 static inline void pci_irq_assert(PCIDevice *pci_dev)
728 {
729 pci_set_irq(pci_dev, 1);
730 }
731
pci_irq_deassert(PCIDevice * pci_dev)732 static inline void pci_irq_deassert(PCIDevice *pci_dev)
733 {
734 pci_set_irq(pci_dev, 0);
735 }
736
737 /*
738 * FIXME: PCI does not work this way.
739 * All the callers to this method should be fixed.
740 */
pci_irq_pulse(PCIDevice * pci_dev)741 static inline void pci_irq_pulse(PCIDevice *pci_dev)
742 {
743 pci_irq_assert(pci_dev);
744 pci_irq_deassert(pci_dev);
745 }
746
pci_is_express(const PCIDevice * d)747 static inline int pci_is_express(const PCIDevice *d)
748 {
749 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
750 }
751
pci_is_express_downstream_port(const PCIDevice * d)752 static inline int pci_is_express_downstream_port(const PCIDevice *d)
753 {
754 uint8_t type;
755
756 if (!pci_is_express(d) || !d->exp.exp_cap) {
757 return 0;
758 }
759
760 type = pcie_cap_get_type(d);
761
762 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
763 }
764
pci_config_size(const PCIDevice * d)765 static inline uint32_t pci_config_size(const PCIDevice *d)
766 {
767 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
768 }
769
pci_get_bdf(PCIDevice * dev)770 static inline uint16_t pci_get_bdf(PCIDevice *dev)
771 {
772 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
773 }
774
775 uint16_t pci_requester_id(PCIDevice *dev);
776
777 /* DMA access functions */
pci_get_address_space(PCIDevice * dev)778 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
779 {
780 return &dev->bus_master_as;
781 }
782
pci_dma_rw(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len,DMADirection dir)783 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
784 void *buf, dma_addr_t len, DMADirection dir)
785 {
786 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
787 return 0;
788 }
789
pci_dma_read(PCIDevice * dev,dma_addr_t addr,void * buf,dma_addr_t len)790 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
791 void *buf, dma_addr_t len)
792 {
793 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
794 }
795
pci_dma_write(PCIDevice * dev,dma_addr_t addr,const void * buf,dma_addr_t len)796 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
797 const void *buf, dma_addr_t len)
798 {
799 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
800 }
801
802 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
803 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
804 dma_addr_t addr) \
805 { \
806 return ld##_l##_dma(pci_get_address_space(dev), addr); \
807 } \
808 static inline void st##_s##_pci_dma(PCIDevice *dev, \
809 dma_addr_t addr, uint##_bits##_t val) \
810 { \
811 st##_s##_dma(pci_get_address_space(dev), addr, val); \
812 }
813
814 PCI_DMA_DEFINE_LDST(ub, b, 8);
815 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
816 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
817 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
818 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
819 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
820 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
821
822 #undef PCI_DMA_DEFINE_LDST
823
pci_dma_map(PCIDevice * dev,dma_addr_t addr,dma_addr_t * plen,DMADirection dir)824 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
825 dma_addr_t *plen, DMADirection dir)
826 {
827 void *buf;
828
829 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
830 return buf;
831 }
832
pci_dma_unmap(PCIDevice * dev,void * buffer,dma_addr_t len,DMADirection dir,dma_addr_t access_len)833 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
834 DMADirection dir, dma_addr_t access_len)
835 {
836 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
837 }
838
pci_dma_sglist_init(QEMUSGList * qsg,PCIDevice * dev,int alloc_hint)839 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
840 int alloc_hint)
841 {
842 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
843 }
844
845 extern const VMStateDescription vmstate_pci_device;
846
847 #define VMSTATE_PCI_DEVICE(_field, _state) { \
848 .name = (stringify(_field)), \
849 .size = sizeof(PCIDevice), \
850 .vmsd = &vmstate_pci_device, \
851 .flags = VMS_STRUCT, \
852 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
853 }
854
855 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
856 .name = (stringify(_field)), \
857 .size = sizeof(PCIDevice), \
858 .vmsd = &vmstate_pci_device, \
859 .flags = VMS_STRUCT|VMS_POINTER, \
860 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
861 }
862
863 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
864
865 #endif
866