1 /** @file 2 The definition for VTD register. 3 It is defined in "Intel VT for Direct IO Architecture Specification". 4 5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef __VTD_REG_H__ 11 #define __VTD_REG_H__ 12 13 #pragma pack(1) 14 15 // 16 // Translation Structure Formats 17 // 18 #define VTD_ROOT_ENTRY_NUMBER 256 19 #define VTD_CONTEXT_ENTRY_NUMBER 256 20 21 typedef union { 22 struct { 23 UINT32 Present:1; 24 UINT32 Reserved_1:11; 25 UINT32 ContextTablePointerLo:20; 26 UINT32 ContextTablePointerHi:32; 27 28 UINT64 Reserved_64; 29 } Bits; 30 struct { 31 UINT64 Uint64Lo; 32 UINT64 Uint64Hi; 33 } Uint128; 34 } VTD_ROOT_ENTRY; 35 36 typedef union { 37 struct { 38 UINT32 LowerPresent:1; 39 UINT32 Reserved_1:11; 40 UINT32 LowerContextTablePointerLo:20; 41 UINT32 LowerContextTablePointerHi:32; 42 43 UINT32 UpperPresent:1; 44 UINT32 Reserved_65:11; 45 UINT32 UpperContextTablePointerLo:20; 46 UINT32 UpperContextTablePointerHi:32; 47 } Bits; 48 struct { 49 UINT64 Uint64Lo; 50 UINT64 Uint64Hi; 51 } Uint128; 52 } VTD_EXT_ROOT_ENTRY; 53 54 typedef union { 55 struct { 56 UINT32 Present:1; 57 UINT32 FaultProcessingDisable:1; 58 UINT32 TranslationType:2; 59 UINT32 Reserved_4:8; 60 UINT32 SecondLevelPageTranslationPointerLo:20; 61 UINT32 SecondLevelPageTranslationPointerHi:32; 62 63 UINT32 AddressWidth:3; 64 UINT32 Ignored_67:4; 65 UINT32 Reserved_71:1; 66 UINT32 DomainIdentifier:16; 67 UINT32 Reserved_88:8; 68 UINT32 Reserved_96:32; 69 } Bits; 70 struct { 71 UINT64 Uint64Lo; 72 UINT64 Uint64Hi; 73 } Uint128; 74 } VTD_CONTEXT_ENTRY; 75 76 typedef union { 77 struct { 78 UINT32 Present:1; 79 UINT32 FaultProcessingDisable:1; 80 UINT32 TranslationType:3; 81 UINT32 ExtendedMemoryType:3; 82 UINT32 DeferredInvalidateEnable:1; 83 UINT32 PageRequestEnable:1; 84 UINT32 NestedTranslationEnable:1; 85 UINT32 PASIDEnable:1; 86 UINT32 SecondLevelPageTranslationPointerLo:20; 87 UINT32 SecondLevelPageTranslationPointerHi:32; 88 89 UINT32 AddressWidth:3; 90 UINT32 PageGlobalEnable:1; 91 UINT32 NoExecuteEnable:1; 92 UINT32 WriteProtectEnable:1; 93 UINT32 CacheDisable:1; 94 UINT32 ExtendedMemoryTypeEnable:1; 95 UINT32 DomainIdentifier:16; 96 UINT32 SupervisorModeExecuteProtection:1; 97 UINT32 ExtendedAccessedFlagEnable:1; 98 UINT32 ExecuteRequestsEnable:1; 99 UINT32 SecondLevelExecuteEnable:1; 100 UINT32 Reserved_92:4; 101 UINT32 PageAttributeTable0:3; 102 UINT32 Reserved_Pat0:1; 103 UINT32 PageAttributeTable1:3; 104 UINT32 Reserved_Pat1:1; 105 UINT32 PageAttributeTable2:3; 106 UINT32 Reserved_Pat2:1; 107 UINT32 PageAttributeTable3:3; 108 UINT32 Reserved_Pat3:1; 109 UINT32 PageAttributeTable4:3; 110 UINT32 Reserved_Pat4:1; 111 UINT32 PageAttributeTable5:3; 112 UINT32 Reserved_Pat5:1; 113 UINT32 PageAttributeTable6:3; 114 UINT32 Reserved_Pat6:1; 115 UINT32 PageAttributeTable7:3; 116 UINT32 Reserved_Pat7:1; 117 118 UINT32 PASIDTableSize:4; 119 UINT32 Reserved_132:8; 120 UINT32 PASIDTablePointerLo:20; 121 UINT32 PASIDTablePointerHi:32; 122 123 UINT32 Reserved_192:12; 124 UINT32 PASIDStateTablePointerLo:20; 125 UINT32 PASIDStateTablePointerHi:32; 126 } Bits; 127 struct { 128 UINT64 Uint64_1; 129 UINT64 Uint64_2; 130 UINT64 Uint64_3; 131 UINT64 Uint64_4; 132 } Uint256; 133 } VTD_EXT_CONTEXT_ENTRY; 134 135 typedef union { 136 struct { 137 UINT32 Present:1; 138 UINT32 Reserved_1:2; 139 UINT32 PageLevelCacheDisable:1; 140 UINT32 PageLevelWriteThrough:1; 141 UINT32 Reserved_5:6; 142 UINT32 SupervisorRequestsEnable:1; 143 UINT32 FirstLevelPageTranslationPointerLo:20; 144 UINT32 FirstLevelPageTranslationPointerHi:32; 145 } Bits; 146 UINT64 Uint64; 147 } VTD_PASID_ENTRY; 148 149 typedef union { 150 struct { 151 UINT32 Reserved_0:32; 152 UINT32 ActiveReferenceCount:16; 153 UINT32 Reserved_48:15; 154 UINT32 DeferredInvalidate:1; 155 } Bits; 156 UINT64 Uint64; 157 } VTD_PASID_STATE_ENTRY; 158 159 typedef union { 160 struct { 161 UINT32 Present:1; 162 UINT32 ReadWrite:1; 163 UINT32 UserSupervisor:1; 164 UINT32 PageLevelWriteThrough:1; 165 UINT32 PageLevelCacheDisable:1; 166 UINT32 Accessed:1; 167 UINT32 Dirty:1; 168 UINT32 PageSize:1; // It is PageAttribute:1 for 4K page entry 169 UINT32 Global:1; 170 UINT32 Ignored_9:1; 171 UINT32 ExtendedAccessed:1; 172 UINT32 Ignored_11:1; 173 // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M page entry 174 UINT32 AddressLo:20; 175 UINT32 AddressHi:20; 176 UINT32 Ignored_52:11; 177 UINT32 ExecuteDisable:1; 178 } Bits; 179 UINT64 Uint64; 180 } VTD_FIRST_LEVEL_PAGING_ENTRY; 181 182 typedef union { 183 struct { 184 UINT32 Read:1; 185 UINT32 Write:1; 186 UINT32 Execute:1; 187 UINT32 ExtendedMemoryType:3; 188 UINT32 IgnorePAT:1; 189 UINT32 PageSize:1; 190 UINT32 Ignored_8:3; 191 UINT32 Snoop:1; 192 UINT32 AddressLo:20; 193 UINT32 AddressHi:20; 194 UINT32 Ignored_52:10; 195 UINT32 TransientMapping:1; 196 UINT32 Ignored_63:1; 197 } Bits; 198 UINT64 Uint64; 199 } VTD_SECOND_LEVEL_PAGING_ENTRY; 200 201 // 202 // Register Descriptions 203 // 204 #define R_VER_REG 0x00 205 #define R_CAP_REG 0x08 206 #define B_CAP_REG_RWBF BIT4 207 #define R_ECAP_REG 0x10 208 #define R_GCMD_REG 0x18 209 #define B_GMCD_REG_WBF BIT27 210 #define B_GMCD_REG_SRTP BIT30 211 #define B_GMCD_REG_TE BIT31 212 #define R_GSTS_REG 0x1C 213 #define B_GSTS_REG_WBF BIT27 214 #define B_GSTS_REG_RTPS BIT30 215 #define B_GSTS_REG_TE BIT31 216 #define R_RTADDR_REG 0x20 217 #define R_CCMD_REG 0x28 218 #define B_CCMD_REG_CIRG_MASK (BIT62|BIT61) 219 #define V_CCMD_REG_CIRG_GLOBAL BIT61 220 #define V_CCMD_REG_CIRG_DOMAIN BIT62 221 #define V_CCMD_REG_CIRG_DEVICE (BIT62|BIT61) 222 #define B_CCMD_REG_ICC BIT63 223 #define R_FSTS_REG 0x34 224 #define R_FECTL_REG 0x38 225 #define R_FEDATA_REG 0x3C 226 #define R_FEADDR_REG 0x40 227 #define R_FEUADDR_REG 0x44 228 #define R_AFLOG_REG 0x58 229 230 #define R_IVA_REG 0x00 // + IRO 231 #define B_IVA_REG_AM_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5) 232 #define B_IVA_REG_AM_4K 0 // 1 page 233 #define B_IVA_REG_AM_2M 9 // 2M page 234 #define B_IVA_REG_IH BIT6 235 #define R_IOTLB_REG 0x08 // + IRO 236 #define B_IOTLB_REG_IIRG_MASK (BIT61|BIT60) 237 #define V_IOTLB_REG_IIRG_GLOBAL BIT60 238 #define V_IOTLB_REG_IIRG_DOMAIN BIT61 239 #define V_IOTLB_REG_IIRG_PAGE (BIT61|BIT60) 240 #define B_IOTLB_REG_IVT BIT63 241 242 #define R_FRCD_REG 0x00 // + FRO 243 244 #define R_PMEN_ENABLE_REG 0x64 245 #define R_PMEN_LOW_BASE_REG 0x68 246 #define R_PMEN_LOW_LIMITE_REG 0x6C 247 #define R_PMEN_HIGH_BASE_REG 0x70 248 #define R_PMEN_HIGH_LIMITE_REG 0x78 249 250 typedef union { 251 struct { 252 UINT8 ND:3; // Number of domains supported 253 UINT8 AFL:1; // Advanced Fault Logging 254 UINT8 RWBF:1; // Required Write-Buffer Flushing 255 UINT8 PLMR:1; // Protected Low-Memory Region 256 UINT8 PHMR:1; // Protected High-Memory Region 257 UINT8 CM:1; // Caching Mode 258 259 UINT8 SAGAW:5; // Supported Adjusted Guest Address Widths 260 UINT8 Rsvd_13:3; 261 262 UINT8 MGAW:6; // Maximum Guest Address Width 263 UINT8 ZLR:1; // Zero Length Read 264 UINT8 Rsvd_23:1; 265 266 UINT16 FRO:10; // Fault-recording Register offset 267 UINT16 SLLPS:4; // Second Level Large Page Support 268 UINT16 Rsvd_38:1; 269 UINT16 PSI:1; // Page Selective Invalidation 270 271 UINT8 NFR:8; // Number of Fault-recording Registers 272 273 UINT8 MAMV:6; // Maximum Address Mask Value 274 UINT8 DWD:1; // Write Draining 275 UINT8 DRD:1; // Read Draining 276 277 UINT8 FL1GP:1; // First Level 1-GByte Page Support 278 UINT8 Rsvd_57:2; 279 UINT8 PI:1; // Posted Interrupts Support 280 UINT8 Rsvd_60:4; 281 } Bits; 282 UINT64 Uint64; 283 } VTD_CAP_REG; 284 285 typedef union { 286 struct { 287 UINT8 C:1; // Page-walk Coherency 288 UINT8 QI:1; // Queued Invalidation support 289 UINT8 DT:1; // Device-TLB support 290 UINT8 IR:1; // Interrupt Remapping support 291 UINT8 EIM:1; // Extended Interrupt Mode 292 UINT8 Rsvd_5:1; 293 UINT8 PT:1; // Pass Through 294 UINT8 SC:1; // Snoop Control 295 296 UINT16 IRO:10; // IOTLB Register Offset 297 UINT16 Rsvd_18:2; 298 UINT16 MHMV:4; // Maximum Handle Mask Value 299 300 UINT8 ECS:1; // Extended Context Support 301 UINT8 MTS:1; // Memory Type Support 302 UINT8 NEST:1; // Nested Translation Support 303 UINT8 DIS:1; // Deferred Invalidate Support 304 UINT8 PASID:1; // Process Address Space ID Support 305 UINT8 PRS:1; // Page Request Support 306 UINT8 ERS:1; // Execute Request Support 307 UINT8 SRS:1; // Supervisor Request Support 308 309 UINT32 Rsvd_32:1; 310 UINT32 NWFS:1; // No Write Flag Support 311 UINT32 EAFS:1; // Extended Accessed Flag Support 312 UINT32 PSS:5; // PASID Size Supported 313 UINT32 Rsvd_40:24; 314 } Bits; 315 UINT64 Uint64; 316 } VTD_ECAP_REG; 317 318 typedef union { 319 struct { 320 UINT32 Rsvd_0:12; 321 UINT32 FILo:20; // FaultInfo 322 UINT32 FIHi:32; // FaultInfo 323 324 UINT32 SID:16; // Source Identifier 325 UINT32 Rsvd_80:13; 326 UINT32 PRIV:1; // Privilege Mode Requested 327 UINT32 EXE:1; // Execute Permission Requested 328 UINT32 PP:1; // PASID Present 329 330 UINT32 FR:8; // Fault Reason 331 UINT32 PV:20; // PASID Value 332 UINT32 AT:2; // Address Type 333 UINT32 T:1; // Type (0: Write, 1: Read) 334 UINT32 F:1; // Fault 335 } Bits; 336 UINT64 Uint64[2]; 337 } VTD_FRCD_REG; 338 339 typedef union { 340 struct { 341 UINT8 Function:3; 342 UINT8 Device:5; 343 UINT8 Bus; 344 } Bits; 345 struct { 346 UINT8 ContextIndex; 347 UINT8 RootIndex; 348 } Index; 349 UINT16 Uint16; 350 } VTD_SOURCE_ID; 351 352 #pragma pack() 353 354 #endif 355 356