1 /* Copyright 2013-2019 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #include <skiboot.h>
17 #include <io.h>
18 #include <timebase.h>
19 #include <pci.h>
20 #include <pci-virt.h>
21 #include <interrupts.h>
22 #include <npu2.h>
23 #include <npu2-regs.h>
24 #include <xscom.h>
25
26 /* Set in npu2.c if there is an nvram override for the zcal settings on this
27 * machine */
28 int nv_zcal_nominal = -1;
29
30 /* PHY Registers. The documentation for the PHY training is written in
31 * terms of bits within an actual register so we use that
32 * representation here. */
33 struct npu2_phy_reg {
34 uint64_t offset;
35 uint64_t start;
36 uint64_t len;
37 };
38
39 /*
40 * Currently unused, but documented here:
41 static struct npu2_phy_reg NPU2_PHY_RX_DATA_DAC_SPARE_MODE = {0x000, 63, 64};
42 static struct npu2_phy_reg NPU2_PHY_RX_DAC_CNTL6 = {0x00c, 63, 64};
43 static struct npu2_phy_reg NPU2_PHY_RX_DAC_CNTL5 = {0x028, 63, 64};
44 static struct npu2_phy_reg NPU2_PHY_RX_DAC_CNTL9 = {0x030, 63, 64};
45 static struct npu2_phy_reg NPU2_PHY_RX_DAC_CNTL5_EO = {0x00a, 63, 64};
46 static struct npu2_phy_reg NPU2_PHY_RX_DAC_CNTL4 = {0x026, 63, 64};
47 */
48 static struct npu2_phy_reg NPU2_PHY_RX_RUN_LANE = {0x0c8, 48, 1};
49 static struct npu2_phy_reg NPU2_PHY_RX_IORESET = {0x096, 63, 1};
50 static struct npu2_phy_reg NPU2_PHY_TX_IORESET = {0x113, 48, 1};
51 static struct npu2_phy_reg NPU2_PHY_RX_PR_RESET = {0x096, 62, 1};
52 static struct npu2_phy_reg NPU2_PHY_RX_LANE_ANA_PDWN = {0x002, 54, 1};
53 static struct npu2_phy_reg NPU2_PHY_RX_LANE_DIG_PDWN = {0x088, 48, 1};
54 static struct npu2_phy_reg NPU2_PHY_RX_PR_IQ_RES_SEL = {0x004, 59, 3};
55 static struct npu2_phy_reg NPU2_PHY_RX_PR_PHASE_STEP = {0x08a, 60, 4};
56 static struct npu2_phy_reg NPU2_PHY_TX_LANE_PDWN = {0x101, 48, 1};
57 static struct npu2_phy_reg NPU2_PHY_RX_RUN_DCCAL = {0x0c8, 49, 1};
58 static struct npu2_phy_reg NPU2_PHY_RX_DCCAL_DONE = {0x0ca, 49, 1};
59 static struct npu2_phy_reg NPU2_PHY_RX_LANE_BUSY = {0x0ca, 50, 1};
60 static struct npu2_phy_reg NPU2_PHY_RX_B_BANK_CONTROLS = {0x002, 58, 6};
61 static struct npu2_phy_reg NPU2_PHY_TX_UNLOAD_CLK_DISABLE = {0x103, 56, 1};
62 static struct npu2_phy_reg NPU2_PHY_TX_FIFO_INIT = {0x105, 53, 1};
63 static struct npu2_phy_reg NPU2_PHY_TX_RXCAL = {0x103, 57, 1};
64 static struct npu2_phy_reg NPU2_PHY_RX_INIT_DONE = {0x0ca, 48, 1};
65 static struct npu2_phy_reg NPU2_PHY_RX_PR_EDGE_TRACK_CNTL = {0x092, 48, 2};
66 static struct npu2_phy_reg NPU2_PHY_RX_PR_BUMP_SL_1UI = {0x092, 57, 1};
67 static struct npu2_phy_reg NPU2_PHY_RX_PR_FW_OFF = {0x08a, 56, 1};
68 static struct npu2_phy_reg NPU2_PHY_RX_PR_FW_INERTIA_AMT = {0x08a, 57, 3};
69 static struct npu2_phy_reg NPU2_PHY_RX_CFG_LTE_MC = {0x000, 60, 4};
70 static struct npu2_phy_reg NPU2_PHY_RX_A_INTEG_COARSE_GAIN = {0x00a, 48, 4};
71 static struct npu2_phy_reg NPU2_PHY_RX_B_INTEG_COARSE_GAIN = {0x026, 48, 4};
72 static struct npu2_phy_reg NPU2_PHY_RX_E_INTEG_COARSE_GAIN = {0x030, 48, 4};
73
74 /* These registers are per-PHY, not per lane */
75 static struct npu2_phy_reg NPU2_PHY_RX_SPEED_SELECT = {0x262, 51, 2};
76 static struct npu2_phy_reg NPU2_PHY_RX_AC_COUPLED = {0x262, 53, 1};
77 static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_SWO_EN = {0x3c9, 48, 1};
78 static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_REQ = {0x3c1, 49, 1};
79 static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_DONE = {0x3c1, 50, 1};
80 static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_ERROR = {0x3c1, 51, 1};
81 static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_N = {0x3c3, 48, 9};
82 static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_P = {0x3c5, 48, 9};
83 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_PRE_EN = {0x34d, 51, 5};
84 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_PRE_SELECT = {0x34d, 56, 5};
85 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_PRE_EN = {0x34f, 51, 5};
86 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_PRE_SELECT = {0x34f, 56, 5};
87 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_POST_EN = {0x361, 49, 7};
88 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_POST_SELECT = {0x361, 56, 7};
89 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_POST_EN = {0x363, 49, 7};
90 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_POST_SELECT = {0x363, 56, 7};
91 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_MARGINPU_EN = {0x351, 48, 8};
92 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_MARGINPU_EN = {0x353, 48, 8};
93 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_MARGINPD_EN = {0x351, 56, 8};
94 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_MARGINPD_EN = {0x353, 56, 8};
95 static struct npu2_phy_reg NPU2_PHY_TX_MARGINPU_SELECT = {0x355, 48, 8};
96 static struct npu2_phy_reg NPU2_PHY_TX_MARGINPD_SELECT = {0x355, 56, 8};
97 static struct npu2_phy_reg NPU2_PHY_TX_PSEG_MAIN_EN = {0x357, 51, 7};
98 static struct npu2_phy_reg NPU2_PHY_TX_NSEG_MAIN_EN = {0x359, 51, 7};
99 /* Currently unused, but documented here
100 static struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH = {0x24e, 54, 8};
101 static struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH_LANE = {0x24e, 49, 5};
102 static struct npu2_phy_reg NPU2_PHY_RX_HIST_MIN_EYE_WIDTH_VALID= {0x24e, 48, 1};
103 */
104 static struct npu2_phy_reg NPU2_PHY_RX_RC_ENABLE_AUTO_RECAL = {0x25c, 51, 1};
105
106 static struct npu2_phy_reg NPU2_PHY_RX_CLKDIST_PDWN = {0x204, 48, 3};
107 static struct npu2_phy_reg NPU2_PHY_RX_IREF_PDWN = {0x230, 54, 1};
108 static struct npu2_phy_reg NPU2_PHY_TX_CLKDIST_PDWN = {0x305, 48, 3};
109 static struct npu2_phy_reg NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN = {0x2e0, 60, 1};
110 static struct npu2_phy_reg NPU2_PHY_TX_DRV_DATA_PATTERN_GCRMSG = {0x309, 50, 4};
111
112 #define NPU2_PHY_REG(scom_base, reg, lane) \
113 SETFIELD(PPC_BITMASK(27, 31), ((reg)->offset << 42) | scom_base, lane)
114
115 #define NPU2_MAX_PHY_LANE 23
116
117 /* This is a bit of a gross hack but it does the job */
118 #define FOR_EACH_LANE(ndev, lane) \
119 for (lane = 0; lane <= NPU2_MAX_PHY_LANE; lane++) \
120 if (!(ndev->lane_mask & (1 << (NPU2_MAX_PHY_LANE - lane)))) \
121 continue; \
122 else
123
124 typedef uint32_t (*step)(struct npu2_dev *);
125
126 struct procedure {
127 const char *name;
128 step steps[];
129 };
130
131 #define DEFINE_PROCEDURE(NAME, STEPS...) \
132 static struct procedure procedure_##NAME = \
133 {.name = #NAME, .steps = {NAME, ##STEPS}}
134
135 #define PROCEDURE_INPROGRESS (1 << 31)
136 #define PROCEDURE_COMPLETE (1 << 30)
137 #define PROCEDURE_NEXT (1 << 29)
138 #define PROCEDURE_FAILED 2
139 #define PROCEDURE_ABORTED 3
140 #define PROCEDURE_UNSUPPORTED 4
141
142 /* Mask defining which status bits we want to expose */
143 #define PROCEDURE_STATUS_MASK 0xc000000f
144
phy_write_lane(struct npu2_dev * ndev,struct npu2_phy_reg * reg,int lane,uint64_t val)145 static void phy_write_lane(struct npu2_dev *ndev, struct npu2_phy_reg *reg, int lane, uint64_t val)
146 {
147 uint64_t old_val, reg_addr;
148 int rc;
149 uint64_t mask = PPC_BITMASK(reg->start, reg->start + reg->len - 1);
150
151 /* Check to make sure we're not trying to specify a lane to a
152 * non-per-lane register */
153 if (lane >= 0)
154 assert(reg->offset < 0x200);
155 else
156 assert(reg->offset >= 0x200);
157
158 reg_addr = NPU2_PHY_REG(ndev->pl_xscom_base, reg, lane);
159 rc = xscom_read(ndev->npu->chip_id, reg_addr, &old_val);
160 if (rc)
161 NPU2DEVERR(ndev, "error %d reading scom 0x%llx\n", rc, reg_addr);
162 val = SETFIELD(mask, old_val, val);
163 rc = xscom_write(ndev->npu->chip_id, reg_addr, val);
164 if (rc)
165 NPU2DEVERR(ndev, "error %d writing scom 0x%llx\n", rc, reg_addr);
166 }
167
phy_read_lane(struct npu2_dev * ndev,struct npu2_phy_reg * reg,int lane)168 static uint64_t phy_read_lane(struct npu2_dev *ndev, struct npu2_phy_reg *reg, int lane)
169 {
170 uint64_t val, reg_addr;
171 int rc;
172 uint64_t mask = PPC_BITMASK(reg->start, reg->start + reg->len - 1);
173
174 /* Check to make sure we're not trying to specify a lane to a
175 * non-per-lane register */
176 if (lane >= 0)
177 assert(reg->offset < 0x200);
178 else
179 assert(reg->offset >= 0x200);
180
181 reg_addr = NPU2_PHY_REG(ndev->pl_xscom_base, reg, lane);
182 rc = xscom_read(ndev->npu->chip_id, reg_addr, &val);
183 if (rc)
184 NPU2DEVERR(ndev, "error %d reading scom 0x%llx\n", rc, reg_addr);
185
186 return GETFIELD(mask, val);
187 }
188
189 #define phy_write(ndev, reg, val) phy_write_lane(ndev, reg, -1, val)
190 #define phy_read(ndev, reg) phy_read_lane(ndev, reg, -1)
191
stop(struct npu2_dev * npu_dev __unused)192 static uint32_t stop(struct npu2_dev *npu_dev __unused)
193 {
194 return PROCEDURE_COMPLETE | PROCEDURE_ABORTED;
195 }
196 DEFINE_PROCEDURE(stop);
197
nop(struct npu2_dev * npu_dev __unused)198 static uint32_t nop(struct npu2_dev *npu_dev __unused)
199 {
200 return PROCEDURE_COMPLETE;
201 }
202 DEFINE_PROCEDURE(nop);
203
204 /*
205 * Return the obus (0 or 1) of a device
206 *
207 * Using the brick index is dangerous, because it varies for a link
208 * depending on the mode (opencapi or nvlink)
209 */
obus_index(struct npu2_dev * ndev)210 static int obus_index(struct npu2_dev *ndev)
211 {
212 if ((ndev->pl_xscom_base & 0x3F000000) == 0x09000000)
213 return 0;
214 else
215 return 1;
216 }
217
218 /*
219 * Return the brick number (0-2) within an obus chiplet.
220 * Only valid for nvlink devices
221 */
obus_brick_index(struct npu2_dev * ndev)222 static int obus_brick_index(struct npu2_dev *ndev)
223 {
224 int index = ndev->brick_index % 3;
225
226 assert(ndev->type != NPU2_DEV_TYPE_OPENCAPI);
227 /* On the second obus chiplet, index is reversed */
228 if ((ndev->pl_xscom_base & 0x3F000000) != 0x09000000)
229 return 2 - index;
230
231 return index;
232 }
233
set_iovalid(struct npu2_dev * ndev,bool raise)234 static void set_iovalid(struct npu2_dev *ndev, bool raise)
235 {
236 uint64_t addr, val, mask;
237 int rc;
238
239 if (ndev->type == NPU2_DEV_TYPE_OPENCAPI)
240 return;
241
242 addr = (ndev->pl_xscom_base & 0x3F000000) | 0x9;
243 mask = PPC_BIT(6 + obus_brick_index(ndev));
244 val = raise ? mask : 0;
245
246 rc = xscom_write_mask(ndev->npu->chip_id, addr, val, mask);
247 if (rc)
248 NPU2DEVERR(ndev, "error %d writing scom 0x%llx\n", rc, addr);
249 }
250
poll_fence_status(struct npu2_dev * ndev,uint64_t val)251 static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val)
252 {
253 uint64_t fs;
254 int i;
255
256 for (i = 0; i < 4096; i++) {
257 fs = npu2_read(ndev->npu, NPU2_NTL_CQ_FENCE_STATUS(ndev));
258 if ((fs & 0xc000000000000000UL) == val)
259 return true;
260 }
261
262 NPU2DEVERR(ndev, "NPU2_NTL_CQ_FENCE_STATUS timeout (0x%llx)\n", val);
263 return false;
264 }
265
266 /* Procedure 1.2.1 - Reset NPU/NDL */
reset_ntl(struct npu2_dev * ndev)267 uint32_t reset_ntl(struct npu2_dev *ndev)
268 {
269 uint64_t val;
270 int lane;
271
272 set_iovalid(ndev, true);
273
274 /* Power on clocks */
275 phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0);
276 phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1);
277 phy_write(ndev, &NPU2_PHY_TX_CLKDIST_PDWN, 0);
278 phy_write(ndev, &NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN, 0);
279
280 FOR_EACH_LANE(ndev, lane) {
281 phy_write_lane(ndev, &NPU2_PHY_RX_LANE_ANA_PDWN, lane, 0);
282 phy_write_lane(ndev, &NPU2_PHY_RX_LANE_DIG_PDWN, lane, 0);
283 phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
284 }
285
286 /* Clear fence state for the brick */
287 val = npu2_read(ndev->npu, NPU2_MISC_FENCE_STATE);
288 if (val & PPC_BIT(ndev->brick_index)) {
289 NPU2DEVINF(ndev, "Clearing brick fence\n");
290 val = PPC_BIT(ndev->brick_index);
291 npu2_write(ndev->npu, NPU2_MISC_FENCE_STATE, val);
292 }
293
294 /* Write PRI */
295 val = SETFIELD(PPC_BITMASK(0,1), 0ull, obus_brick_index(ndev));
296 npu2_write_mask(ndev->npu, NPU2_NTL_PRI_CFG(ndev), val, -1ULL);
297
298 val = NPU2_NTL_MISC_CFG2_NDL_RX_PARITY_ENA;
299 npu2_write_mask(ndev->npu, NPU2_NTL_MISC_CFG2(ndev), 0ull, val);
300
301 /* NTL Reset */
302 val = npu2_read(ndev->npu, NPU2_NTL_MISC_CFG1(ndev));
303 val |= PPC_BIT(8) | PPC_BIT(9);
304 npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val);
305
306 if (!poll_fence_status(ndev, 0xc000000000000000UL))
307 return PROCEDURE_COMPLETE | PROCEDURE_FAILED;
308
309 return PROCEDURE_NEXT;
310 }
311
reset_ndl(struct npu2_dev * ndev)312 static uint32_t reset_ndl(struct npu2_dev *ndev)
313 {
314 uint64_t val;
315
316 val = npu2_read_4b(ndev->npu, NPU2_NTL_DL_CONTROL(ndev));
317 val |= PPC_BIT32(0) | PPC_BIT32(1);
318 npu2_write_4b(ndev->npu, NPU2_NTL_DL_CONTROL(ndev), val);
319
320 val = npu2_read_4b(ndev->npu, NPU2_NTL_DL_CONTROL(ndev));
321 val &= ~(PPC_BIT32(0) | PPC_BIT32(1));
322 npu2_write_4b(ndev->npu, NPU2_NTL_DL_CONTROL(ndev), val);
323
324 val = PPC_BIT32(0);
325 npu2_write_4b(ndev->npu, NPU2_NTL_DL_CONFIG(ndev), val);
326
327 return PROCEDURE_NEXT;
328 }
329
reset_ntl_release(struct npu2_dev * ndev)330 static uint32_t reset_ntl_release(struct npu2_dev *ndev)
331 {
332 uint64_t val;
333 uint64_t npu2_fir;
334 uint64_t npu2_fir_addr;
335 int i;
336
337 /* Clear FIR bits */
338 npu2_fir_addr = NPU2_FIR_REGISTER_0;
339 npu2_fir = 0;
340
341 for (i = 0; i < NPU2_TOTAL_FIR_REGISTERS; i++) {
342 xscom_write(ndev->npu->chip_id, npu2_fir_addr, npu2_fir);
343 npu2_fir_addr += NPU2_FIR_OFFSET;
344
345 }
346
347 val = npu2_read(ndev->npu, NPU2_NTL_MISC_CFG1(ndev));
348 val &= 0xFFBFFFFFFFFFFFFFUL;
349 npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val);
350
351 if (!poll_fence_status(ndev, 0x8000000000000000UL))
352 return PROCEDURE_COMPLETE | PROCEDURE_FAILED;
353
354 return PROCEDURE_NEXT;
355 }
356
reset_ntl_finish(struct npu2_dev * ndev)357 static uint32_t reset_ntl_finish(struct npu2_dev *ndev)
358 {
359 /* Credit Setup */
360 npu2_write(ndev->npu, NPU2_NTL_CRED_HDR_CREDIT_TX(ndev), 0x0200000000000000UL);
361 npu2_write(ndev->npu, NPU2_NTL_PRB_HDR_CREDIT_TX(ndev), 0x0200000000000000UL);
362 npu2_write(ndev->npu, NPU2_NTL_ATR_HDR_CREDIT_TX(ndev), 0x0200000000000000UL);
363 npu2_write(ndev->npu, NPU2_NTL_RSP_HDR_CREDIT_TX(ndev), 0x0200000000000000UL);
364 npu2_write(ndev->npu, NPU2_NTL_CRED_DATA_CREDIT_TX(ndev), 0x1000000000000000UL);
365 npu2_write(ndev->npu, NPU2_NTL_RSP_DATA_CREDIT_TX(ndev), 0x1000000000000000UL);
366 npu2_write(ndev->npu, NPU2_NTL_CRED_HDR_CREDIT_RX(ndev), 0x0000BE0000000000UL);
367 npu2_write(ndev->npu, NPU2_NTL_DBD_HDR_CREDIT_RX(ndev), 0x0000640000000000UL);
368 npu2_write(ndev->npu, NPU2_NTL_ATSD_HDR_CREDIT_RX(ndev), 0x0000200000000000UL);
369 npu2_write(ndev->npu, NPU2_NTL_RSP_HDR_CREDIT_RX(ndev), 0x0000BE0000000000UL);
370 npu2_write(ndev->npu, NPU2_NTL_CRED_DATA_CREDIT_RX(ndev), 0x0001000000000000UL);
371 npu2_write(ndev->npu, NPU2_NTL_RSP_DATA_CREDIT_RX(ndev), 0x0001000000000000UL);
372
373 npu2_set_link_flag(ndev, NPU2_DEV_DL_RESET);
374
375 return PROCEDURE_COMPLETE;
376 }
377 DEFINE_PROCEDURE(reset_ntl, reset_ndl, reset_ntl_release, reset_ntl_finish);
378
379 /* Procedure 1.2.2 - Reset I/O PHY Lanes */
phy_reset(struct npu2_dev * ndev)380 static uint32_t phy_reset(struct npu2_dev *ndev)
381 {
382 int lane;
383
384 set_iovalid(ndev, false);
385
386 /* Power on clocks */
387 phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0);
388 phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1);
389 phy_write(ndev, &NPU2_PHY_TX_CLKDIST_PDWN, 0);
390 phy_write(ndev, &NPU2_PHY_RX_CTL_DATASM_CLKDIST_PDWN, 0);
391
392 FOR_EACH_LANE(ndev, lane)
393 phy_write_lane(ndev, &NPU2_PHY_RX_RUN_LANE, lane, 0);
394
395 return PROCEDURE_NEXT;
396 }
397
phy_reset_wait(struct npu2_dev * ndev)398 static uint32_t phy_reset_wait(struct npu2_dev *ndev)
399 {
400 int lane;
401
402 /* Wait for all lanes to become inactive */
403 FOR_EACH_LANE(ndev, lane)
404 if (phy_read_lane(ndev, &NPU2_PHY_RX_LANE_BUSY, lane))
405 return PROCEDURE_INPROGRESS;
406
407 FOR_EACH_LANE(ndev, lane) {
408 /* Set lane in reset */
409 phy_write_lane(ndev, &NPU2_PHY_RX_IORESET, lane, 1);
410 phy_write_lane(ndev, &NPU2_PHY_TX_IORESET, lane, 1);
411
412 /* Release lane from reset */
413 phy_write_lane(ndev, &NPU2_PHY_RX_IORESET, lane, 0);
414 phy_write_lane(ndev, &NPU2_PHY_TX_IORESET, lane, 0);
415
416 /* Reset the phase rotator */
417 phy_write_lane(ndev, &NPU2_PHY_RX_PR_RESET, lane, 1);
418 phy_write_lane(ndev, &NPU2_PHY_RX_PR_RESET, lane, 0);
419 }
420
421 return PROCEDURE_NEXT;
422 }
423
424 /* Procedure 1.2.3 - Initialise I/O PHY Registers */
phy_reset_complete(struct npu2_dev * ndev)425 static uint32_t phy_reset_complete(struct npu2_dev *ndev)
426 {
427 int lane;
428
429 if (ndev->type == NPU2_DEV_TYPE_OPENCAPI) {
430 phy_write(ndev, &NPU2_PHY_RX_AC_COUPLED, 1);
431
432 switch (ndev->link_speed) {
433 case 20000000000UL:
434 prlog(PR_INFO, "OCAPI: Link speed set at 20Gb/s\n");
435 phy_write(ndev, &NPU2_PHY_RX_SPEED_SELECT, 1);
436 break;
437 case 25000000000UL:
438 case 25781250000UL:
439 prlog(PR_INFO, "OCAPI: Link speed set at 25.xGb/s\n");
440 phy_write(ndev, &NPU2_PHY_RX_SPEED_SELECT, 0);
441 break;
442 default:
443 prlog(PR_CRIT, "OCAPI: Invalid link speed!\n");
444 assert(false);
445 }
446 }
447
448 FOR_EACH_LANE(ndev, lane) {
449 phy_write_lane(ndev, &NPU2_PHY_RX_LANE_ANA_PDWN, lane, 0);
450 phy_write_lane(ndev, &NPU2_PHY_RX_LANE_DIG_PDWN, lane, 0);
451 phy_write_lane(ndev, &NPU2_PHY_RX_PR_IQ_RES_SEL, lane, 0x7);
452 phy_write_lane(ndev, &NPU2_PHY_RX_PR_PHASE_STEP, lane, 0xc);
453 phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0);
454 phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_INERTIA_AMT, lane, 4);
455 phy_write_lane(ndev, &NPU2_PHY_RX_CFG_LTE_MC, lane, 3);
456 phy_write_lane(ndev, &NPU2_PHY_RX_A_INTEG_COARSE_GAIN, lane, 11);
457 phy_write_lane(ndev, &NPU2_PHY_RX_B_INTEG_COARSE_GAIN, lane, 11);
458 phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11);
459 }
460
461 set_iovalid(ndev, true);
462
463 return PROCEDURE_COMPLETE;
464 }
465 DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete);
466
467 /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */
phy_tx_zcal(struct npu2_dev * ndev)468 static uint32_t phy_tx_zcal(struct npu2_dev *ndev)
469 {
470 if (ndev->npu->tx_zcal_complete[obus_index(ndev)])
471 return PROCEDURE_COMPLETE;
472
473 /* Turn off SW enable and enable zcal state machine */
474 phy_write(ndev, &NPU2_PHY_TX_ZCAL_SWO_EN, 0);
475
476 /* Start impedance calibration state machine */
477 phy_write(ndev, &NPU2_PHY_TX_ZCAL_REQ, 1);
478
479 return PROCEDURE_NEXT;
480 }
481
phy_tx_zcal_wait(struct npu2_dev * ndev)482 static uint32_t phy_tx_zcal_wait(struct npu2_dev *ndev)
483 {
484 int done, error;
485
486 done = phy_read(ndev, &NPU2_PHY_TX_ZCAL_DONE);
487 error = phy_read(ndev, &NPU2_PHY_TX_ZCAL_ERROR);
488
489 /* We have never seen this in the field and it is not expected.
490 * Therefore it's best to error out which will complain loudly. Nominal
491 * vaules may be set in nvram to ignore this error. */
492 if (error && nv_zcal_nominal < 0) {
493 NPU2DEVERR(ndev, "ZCAL failed. Nominal values may be used by"
494 " setting nvram variable nv_zcal_override = 50\n");
495 NPU2DEVERR(ndev, "However this may impact link performance\n");
496 return PROCEDURE_COMPLETE | PROCEDURE_FAILED;
497 }
498
499 if (!done)
500 return PROCEDURE_INPROGRESS;
501
502 return PROCEDURE_NEXT;
503 }
504
505 #define MARGIN_RATIO (0)
506 #define FFE_PRE_COEFF (0)
507 #define FFE_POST_COEFF (0)
508
509 #define PRE_WIDTH (5)
510 #define POST_WIDTH (7)
511 #define MAIN_WIDTH (7)
512 #define ZCAL_MIN (16 * 2)
513 #define ZCAL_MAX (33 * 2)
514 #define PRECURSOR_X2_MAX (4 * 2 + 1)
515 #define POSTCURSOR_X2_MAX (6 * 2 + 1)
516 #define MARGIN_X2_MAX (8 * 2)
517 #define MAIN_X2_MAX ((6 * 2) + 1)
518 #define TOTAL_X2_MAX (PRECURSOR_X2_MAX + POSTCURSOR_X2_MAX + 2*MARGIN_X2_MAX + MAIN_X2_MAX)
519
therm(uint32_t dec)520 static uint32_t therm(uint32_t dec)
521 {
522 return ((0x1 << dec) - 1);
523 }
524
therm_with_half(uint32_t dec,uint8_t width)525 static uint32_t therm_with_half(uint32_t dec, uint8_t width)
526 {
527 /* If the LSB of the 2r equivalent is on, then we need to set the 2r bit (MSB) */
528 uint32_t half_on = ( dec & 0x1 ) << ( width - 1 );
529
530 /* Shift the 2r equivalent to a 1r value and convert to a thermometer code. */
531 uint32_t x1_equiv = ((1 << (dec >> 1 )) - 1);
532
533 /* Combine 1r equivalent thermometer code + the 2r MSB value. */
534 return half_on | x1_equiv;
535 }
536
phy_tx_zcal_calculate(struct npu2_dev * ndev)537 static uint32_t phy_tx_zcal_calculate(struct npu2_dev *ndev)
538 {
539 int p_value, n_value;
540 uint32_t zcal_n;
541 uint32_t zcal_p;
542 uint32_t p_main_enable = MAIN_X2_MAX;
543 uint32_t p_margin_pu_enable = MARGIN_X2_MAX;
544 uint32_t p_margin_pd_enable = MARGIN_X2_MAX;
545 uint32_t p_precursor_select;
546 uint32_t p_postcursor_select;
547 uint32_t margin_pu_select;
548 uint32_t n_main_enable = MAIN_X2_MAX;
549 uint32_t n_margin_pu_enable = MARGIN_X2_MAX;
550 uint32_t n_margin_pd_enable = MARGIN_X2_MAX;
551 uint32_t n_precursor_select;
552 uint32_t n_postcursor_select;
553 uint32_t margin_pd_select;
554 uint32_t margin_select;
555
556 if (nv_zcal_nominal < 0) {
557 /* Convert the value from 8R to 2R by / 4 */
558 zcal_n = phy_read(ndev, &NPU2_PHY_TX_ZCAL_N) / 4;
559 zcal_p = phy_read(ndev, &NPU2_PHY_TX_ZCAL_P) / 4;
560 } else {
561 zcal_n = zcal_p = nv_zcal_nominal;
562 NPU2DEVINF(ndev, "Using nominal values for zcal, performance may be impacted\n");
563 }
564
565 /* Again, if the hardware detects an unexpected condition it's
566 * better just to fail loudly. */
567 if ((zcal_n < ZCAL_MIN) || (zcal_n > ZCAL_MAX) ||
568 (zcal_p < ZCAL_MIN) || (zcal_p > ZCAL_MAX))
569 return PROCEDURE_COMPLETE | PROCEDURE_FAILED;
570
571 p_value = zcal_p - TOTAL_X2_MAX;
572 p_precursor_select = (p_value * FFE_PRE_COEFF)/128;
573 p_postcursor_select = (p_value * FFE_POST_COEFF)/128;
574 margin_pu_select = (p_value * MARGIN_RATIO)/256;
575
576 if (p_value % 2) {
577 p_main_enable--;
578 p_value++;
579 }
580
581 while (p_value < 0) {
582 if (p_main_enable > 1) {
583 p_main_enable -= 2;
584 } else if ((p_margin_pu_enable + p_margin_pd_enable) > 0) {
585 if (p_margin_pu_enable == p_margin_pd_enable)
586 p_margin_pd_enable -= 2;
587 else
588 p_margin_pu_enable -= 2;
589 }
590 p_value += 2;
591 }
592
593 n_value = zcal_n - TOTAL_X2_MAX;
594 n_precursor_select = (n_value * FFE_PRE_COEFF)/128;
595 n_postcursor_select = (n_value * FFE_POST_COEFF)/128;
596 margin_pd_select = (p_value * MARGIN_RATIO)/256;
597
598 if (n_value % 2) {
599 n_main_enable--;
600 n_value++;
601 }
602
603 while (n_value < 0) {
604 if (n_main_enable > 1) {
605 n_main_enable -= 2;
606 } else if ((n_margin_pu_enable + n_margin_pd_enable) > 0) {
607 if (n_margin_pu_enable == n_margin_pd_enable)
608 n_margin_pd_enable -= 2;
609 else
610 n_margin_pu_enable -= 2;
611 }
612 n_value += 2;
613 }
614
615 margin_select = therm((margin_pu_select + 1)/2) &
616 therm((margin_pd_select + 1)/2) &
617 therm((p_margin_pu_enable + 1)/2) &
618 therm((p_margin_pd_enable + 1)/2) &
619 therm((n_margin_pu_enable + 1)/2) &
620 therm((n_margin_pd_enable + 1)/2);
621
622 phy_write(ndev, &NPU2_PHY_TX_PSEG_PRE_EN, therm_with_half(PRECURSOR_X2_MAX, PRE_WIDTH));
623 phy_write(ndev, &NPU2_PHY_TX_PSEG_PRE_SELECT, therm_with_half(p_precursor_select, PRE_WIDTH));
624 phy_write(ndev, &NPU2_PHY_TX_PSEG_POST_EN, therm_with_half(POSTCURSOR_X2_MAX, POST_WIDTH));
625 phy_write(ndev, &NPU2_PHY_TX_PSEG_POST_SELECT, therm_with_half(p_postcursor_select, POST_WIDTH));
626 phy_write(ndev, &NPU2_PHY_TX_PSEG_MARGINPU_EN, therm((p_margin_pu_enable + 1)/2));
627 phy_write(ndev, &NPU2_PHY_TX_PSEG_MARGINPD_EN, therm((p_margin_pd_enable + 1)/2));
628 phy_write(ndev, &NPU2_PHY_TX_PSEG_MAIN_EN, therm_with_half(p_main_enable, MAIN_WIDTH));
629
630 phy_write(ndev, &NPU2_PHY_TX_NSEG_PRE_EN, therm_with_half(PRECURSOR_X2_MAX, PRE_WIDTH));
631 phy_write(ndev, &NPU2_PHY_TX_NSEG_PRE_SELECT, therm_with_half(n_precursor_select, PRE_WIDTH));
632 phy_write(ndev, &NPU2_PHY_TX_NSEG_POST_EN, therm_with_half(POSTCURSOR_X2_MAX, POST_WIDTH));
633 phy_write(ndev, &NPU2_PHY_TX_NSEG_POST_SELECT, therm_with_half(n_postcursor_select, POST_WIDTH));
634 phy_write(ndev, &NPU2_PHY_TX_NSEG_MARGINPU_EN, therm((n_margin_pu_enable + 1)/2));
635 phy_write(ndev, &NPU2_PHY_TX_NSEG_MARGINPD_EN, therm((n_margin_pd_enable + 1)/2));
636 phy_write(ndev, &NPU2_PHY_TX_NSEG_MAIN_EN, therm_with_half(n_main_enable, MAIN_WIDTH));
637
638 phy_write(ndev, &NPU2_PHY_TX_MARGINPU_SELECT, therm(margin_select + 1)/2);
639 phy_write(ndev, &NPU2_PHY_TX_MARGINPD_SELECT, therm(margin_select + 1)/2);
640
641 ndev->npu->tx_zcal_complete[obus_index(ndev)] = 1;
642 return PROCEDURE_COMPLETE;
643 }
644 DEFINE_PROCEDURE(phy_tx_zcal, phy_tx_zcal_wait, phy_tx_zcal_calculate);
645
646 /* Procedure 1.2.8 - Enable Downstream Link Training */
phy_enable_tx_rxcal(struct npu2_dev * ndev)647 static uint32_t phy_enable_tx_rxcal(struct npu2_dev *ndev)
648 {
649 int lane;
650
651 FOR_EACH_LANE(ndev, lane)
652 phy_write_lane(ndev, &NPU2_PHY_TX_RXCAL, lane, 1);
653
654 return PROCEDURE_COMPLETE;
655 }
656 DEFINE_PROCEDURE(phy_enable_tx_rxcal);
657
658 /* Procedure 1.2.9 - Disable Downstream Link Training */
phy_disable_tx_rxcal(struct npu2_dev * ndev)659 static uint32_t phy_disable_tx_rxcal(struct npu2_dev *ndev)
660 {
661 int lane;
662
663 FOR_EACH_LANE(ndev, lane)
664 phy_write_lane(ndev, &NPU2_PHY_TX_RXCAL, lane, 0);
665
666 return PROCEDURE_COMPLETE;
667 }
668 DEFINE_PROCEDURE(phy_disable_tx_rxcal);
669
670 /* Procedure 1.2.4 - I/O PHY DC Calibration */
phy_rx_dccal(struct npu2_dev * ndev)671 static uint32_t phy_rx_dccal(struct npu2_dev *ndev)
672 {
673 int lane;
674
675 set_iovalid(ndev, false);
676
677 FOR_EACH_LANE(ndev, lane)
678 phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1);
679
680 FOR_EACH_LANE(ndev, lane)
681 phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 1);
682
683 return PROCEDURE_NEXT;
684 }
685
phy_rx_dccal_complete(struct npu2_dev * ndev)686 static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev)
687 {
688 int lane;
689
690 FOR_EACH_LANE(ndev, lane)
691 if (!phy_read_lane(ndev, &NPU2_PHY_RX_DCCAL_DONE, lane))
692 return PROCEDURE_INPROGRESS;
693
694 FOR_EACH_LANE(ndev, lane)
695 phy_write_lane(ndev, &NPU2_PHY_RX_RUN_DCCAL, lane, 0);
696
697 FOR_EACH_LANE(ndev, lane) {
698 phy_write_lane(ndev, &NPU2_PHY_RX_B_BANK_CONTROLS, lane, 0);
699 phy_write_lane(ndev, &NPU2_PHY_RX_PR_EDGE_TRACK_CNTL, lane, 0);
700 phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0);
701 }
702
703 set_iovalid(ndev, true);
704
705 return PROCEDURE_NEXT;
706 }
707
phy_rx_clock_sel(struct npu2_dev * ndev)708 static uint32_t phy_rx_clock_sel(struct npu2_dev *ndev)
709 {
710 if (ndev->type != NPU2_DEV_TYPE_OPENCAPI) {
711 /*
712 * Change the RX clk mux control to be done by
713 * software instead of HW. This avoids glitches caused
714 * by changing the mux setting.
715 *
716 * Work around a known DL bug by doing these writes
717 * twice.
718 */
719 npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev),
720 0x80000002, 0x80000003);
721 npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev),
722 0x80000002, 0x80000003);
723
724 npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev),
725 0x80000000, 0x80000003);
726 npu2_write_mask_4b(ndev->npu, NPU2_NTL_DL_CLK_CTRL(ndev),
727 0x80000000, 0x80000003);
728 }
729 return PROCEDURE_NEXT;
730 }
731
732 /* Procedure 1.2.5 - IO PHY Tx FIFO Init */
phy_tx_fifo_init(struct npu2_dev * ndev)733 static uint32_t phy_tx_fifo_init(struct npu2_dev *ndev)
734 {
735 int lane;
736
737 FOR_EACH_LANE(ndev, lane) {
738 phy_write_lane(ndev, &NPU2_PHY_TX_UNLOAD_CLK_DISABLE, lane, 0);
739 phy_write_lane(ndev, &NPU2_PHY_TX_FIFO_INIT, lane, 1);
740 phy_write_lane(ndev, &NPU2_PHY_TX_UNLOAD_CLK_DISABLE, lane, 1);
741 }
742
743 return PROCEDURE_COMPLETE;
744 }
745
746 /* We group TX FIFO init in here mainly because that's what was done
747 * on NVLink1 */
748 DEFINE_PROCEDURE(phy_rx_dccal, phy_rx_dccal_complete, phy_rx_clock_sel,
749 phy_tx_fifo_init);
750
751 /* Procedure 1.2.7 - I/O PHY Upstream Link Training */
phy_rx_training(struct npu2_dev * ndev)752 static uint32_t phy_rx_training(struct npu2_dev *ndev)
753 {
754 int lane;
755
756 FOR_EACH_LANE(ndev, lane)
757 phy_write_lane(ndev, &NPU2_PHY_RX_RUN_LANE, lane, 1);
758
759 return PROCEDURE_NEXT;
760 }
761
phy_rx_training_wait(struct npu2_dev * ndev)762 static uint32_t phy_rx_training_wait(struct npu2_dev *ndev)
763 {
764 int lane;
765
766 FOR_EACH_LANE(ndev, lane)
767 if (!phy_read_lane(ndev, &NPU2_PHY_RX_INIT_DONE, lane))
768 return PROCEDURE_INPROGRESS;
769
770 return PROCEDURE_COMPLETE;
771 }
772 DEFINE_PROCEDURE(phy_rx_training, phy_rx_training_wait);
773
check_credit(struct npu2_dev * ndev,uint64_t reg,const char * reg_name,uint64_t expected)774 static uint32_t check_credit(struct npu2_dev *ndev, uint64_t reg,
775 const char *reg_name, uint64_t expected)
776 {
777 uint64_t val;
778
779 val = npu2_read(ndev->npu, reg);
780 if (val == expected)
781 return 0;
782
783 NPU2DEVERR(ndev, "%s: expected 0x%llx, read 0x%llx\n",
784 reg_name, expected, val);
785
786 return 1;
787 }
788
789 #define CHECK_CREDIT(ndev, reg, expected) \
790 check_credit(ndev, reg(ndev), #reg, expected);
791
check_credits(struct npu2_dev * ndev)792 static uint32_t check_credits(struct npu2_dev *ndev)
793 {
794 int fail = 0;
795 uint64_t val;
796
797 fail += CHECK_CREDIT(ndev, NPU2_NTL_CRED_HDR_CREDIT_RX, 0x0BE0BE0000000000ULL);
798 fail += CHECK_CREDIT(ndev, NPU2_NTL_RSP_HDR_CREDIT_RX, 0x0BE0BE0000000000ULL);
799 fail += CHECK_CREDIT(ndev, NPU2_NTL_CRED_DATA_CREDIT_RX, 0x1001000000000000ULL);
800 fail += CHECK_CREDIT(ndev, NPU2_NTL_RSP_DATA_CREDIT_RX, 0x1001000000000000ULL);
801 fail += CHECK_CREDIT(ndev, NPU2_NTL_DBD_HDR_CREDIT_RX, 0x0640640000000000ULL);
802 fail += CHECK_CREDIT(ndev, NPU2_NTL_ATSD_HDR_CREDIT_RX, 0x0200200000000000ULL);
803
804 assert(!fail);
805
806 val = npu2_read(ndev->npu, NPU2_NTL_MISC_CFG1(ndev));
807 val &= 0xFF3FFFFFFFFFFFFFUL;
808 npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val);
809
810 if (!poll_fence_status(ndev, 0x0))
811 return PROCEDURE_COMPLETE | PROCEDURE_FAILED;
812
813 val = NPU2_NTL_MISC_CFG2_NDL_RX_PARITY_ENA;
814 npu2_write_mask(ndev->npu, NPU2_NTL_MISC_CFG2(ndev), val, val);
815
816 return PROCEDURE_COMPLETE;
817 }
818 DEFINE_PROCEDURE(check_credits);
819
820 static struct procedure *npu_procedures[] = {
821 &procedure_stop,
822 &procedure_nop,
823 NULL,
824 NULL,
825 &procedure_phy_reset,
826 &procedure_phy_tx_zcal,
827 &procedure_phy_rx_dccal,
828 &procedure_phy_enable_tx_rxcal,
829 &procedure_phy_disable_tx_rxcal,
830 &procedure_phy_rx_training,
831 &procedure_reset_ntl,
832
833 /* Place holders for pre-terminate and terminate procedures */
834 &procedure_nop,
835 &procedure_nop,
836 &procedure_check_credits
837 };
838
839 /* Run a procedure step(s) and return status */
get_procedure_status(struct npu2_dev * dev)840 static uint32_t get_procedure_status(struct npu2_dev *dev)
841 {
842 uint32_t result;
843 uint16_t procedure = dev->procedure_number;
844 uint16_t step = dev->procedure_step;
845 const char *name = npu_procedures[procedure]->name;
846
847 do {
848 result = npu_procedures[procedure]->steps[step](dev);
849
850 if (result & PROCEDURE_NEXT) {
851 step++;
852 NPU2DEVINF(dev, "Running procedure %s step %d\n", name, step);
853 }
854 } while (result & PROCEDURE_NEXT);
855
856 dev->procedure_step = step;
857
858 if (result & PROCEDURE_COMPLETE)
859 NPU2DEVINF(dev, "Procedure %s complete\n", name);
860 else if (mftb() > dev->procedure_tb + msecs_to_tb(1000)) {
861 NPU2DEVINF(dev, "Procedure %s timed out\n", name);
862 result = PROCEDURE_COMPLETE | PROCEDURE_FAILED;
863 }
864
865 /* Mask off internal state bits */
866 dev->procedure_status = result & PROCEDURE_STATUS_MASK;
867
868 return dev->procedure_status;
869 }
870
npu_dev_procedure_read(struct npu2_dev * dev,uint32_t offset,uint32_t size,uint32_t * data)871 static int64_t npu_dev_procedure_read(struct npu2_dev *dev, uint32_t offset,
872 uint32_t size, uint32_t *data)
873 {
874 int64_t rc = OPAL_SUCCESS;
875
876 if (size != 4) {
877 /* Short config reads are not supported */
878 prlog(PR_ERR, "NPU%d: Short read of procedure register\n", npu2_dev_to_phb(dev)->opal_id);
879 return OPAL_PARAMETER;
880 }
881
882 *data = 0;
883
884 switch (offset) {
885 case 0:
886 /* Only run the procedure if not already complete */
887 if (dev->procedure_status & PROCEDURE_COMPLETE)
888 *data = dev->procedure_status;
889 else
890 *data = get_procedure_status(dev);
891
892 break;
893
894 case 4:
895 *data = dev->procedure_number;
896 break;
897
898 default:
899 prlog(PR_ERR, "NPU%d: Invalid vendor specific offset 0x%08x\n",
900 npu2_dev_to_phb(dev)->opal_id, offset);
901 rc = OPAL_PARAMETER;
902 }
903
904 return rc;
905 }
906
npu_dev_procedure_write(struct npu2_dev * dev,uint32_t offset,uint32_t size,uint32_t data)907 static int64_t npu_dev_procedure_write(struct npu2_dev *dev, uint32_t offset,
908 uint32_t size, uint32_t data)
909 {
910 const char *name;
911 int64_t rc = OPAL_SUCCESS;
912
913 if (size != 4) {
914 /* Short config writes are not supported */
915 prlog(PR_ERR, "NPU%d: Short read of procedure register\n",
916 npu2_dev_to_phb(dev)->opal_id);
917 return OPAL_PARAMETER;
918 }
919
920 switch (offset) {
921 case 0:
922 /* We ignore writes to the status register */
923 NPU2DEVINF(dev, "Ignoring writes to status register\n");
924 break;
925
926 case 4:
927 if (data >= ARRAY_SIZE(npu_procedures) ||
928 !npu_procedures[data]) {
929 NPU2DEVINF(dev, "Unsupported procedure number %d\n", data);
930 dev->procedure_status = PROCEDURE_COMPLETE
931 | PROCEDURE_UNSUPPORTED;
932 break;
933 }
934
935 name = npu_procedures[data]->name;
936 if (dev->procedure_number == data
937 && !(dev->procedure_status & PROCEDURE_COMPLETE))
938 NPU2DEVINF(dev, "Restarting procedure %s\n", name);
939 else
940 NPU2DEVINF(dev, "Starting procedure %s\n", name);
941
942 dev->procedure_status = PROCEDURE_INPROGRESS;
943 dev->procedure_number = data;
944 dev->procedure_step = 0;
945 dev->procedure_tb = mftb();
946 break;
947
948 default:
949 NPU2DEVINF(dev, "Invalid vendor specific offset 0x%08x\n", offset);
950 rc = OPAL_PARAMETER;
951 }
952
953 return rc;
954 }
955
npu2_dev_procedure(void * dev,struct pci_cfg_reg_filter * pcrf,uint32_t offset,uint32_t len,uint32_t * data,bool write)956 int64_t npu2_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf,
957 uint32_t offset, uint32_t len, uint32_t *data,
958 bool write)
959 {
960 struct pci_virt_device *pvd = dev;
961 struct npu2_dev *ndev = pvd->data;
962
963 if (write)
964 return npu_dev_procedure_write(ndev, offset - pcrf->start,
965 len, *data);
966
967 return npu_dev_procedure_read(ndev, offset - pcrf->start, len, data);
968 }
969
npu2_dev_procedure_reset(struct npu2_dev * dev)970 void npu2_dev_procedure_reset(struct npu2_dev *dev)
971 {
972 uint64_t val;
973
974 /* Fence the brick */
975 val = npu2_read(dev->npu, NPU2_NTL_MISC_CFG1(dev));
976 val |= PPC_BIT(8) | PPC_BIT(9);
977 npu2_write(dev->npu, NPU2_NTL_MISC_CFG1(dev), val);
978
979 npu2_clear_link_flag(dev, NPU2_DEV_DL_RESET);
980 }
981
run_procedure(struct npu2_dev * dev,uint16_t procedure_number)982 static uint32_t run_procedure(struct npu2_dev *dev, uint16_t procedure_number)
983 {
984 struct procedure *proc;
985 const char *name;
986 uint32_t result;
987
988 assert(procedure_number <= ARRAY_SIZE(npu_procedures));
989 proc = npu_procedures[procedure_number];
990 assert(proc);
991
992 name = proc->name;
993 NPU2DEVINF(dev, "Running procedure %s\n", name);
994 dev->procedure_status = PROCEDURE_INPROGRESS;
995 dev->procedure_number = procedure_number;
996 dev->procedure_step = 0;
997 dev->procedure_tb = mftb();
998
999 result = get_procedure_status(dev);
1000 while (!(result & PROCEDURE_COMPLETE)) {
1001 time_wait_ms(1);
1002 result = get_procedure_status(dev);
1003 }
1004 return result;
1005 }
1006
npu2_opencapi_bump_ui_lane(struct npu2_dev * dev)1007 void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev)
1008 {
1009 uint64_t reg;
1010 uint64_t status_xscom;
1011 int lane, bit = 7;
1012
1013 status_xscom = OB_ODL_TRAINING_STATUS(dev->brick_index);
1014 xscom_read(dev->npu->chip_id, status_xscom, ®);
1015 reg = GETFIELD(OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B, reg);
1016
1017 FOR_EACH_LANE(dev, lane) {
1018 if (reg & (1 << bit--))
1019 continue;
1020 prlog(PR_TRACE, "OCAPI: bumpui bumping lane %d\n", lane);
1021 for (int i = 0; i < 4; i++) {
1022 phy_write_lane(dev, &NPU2_PHY_RX_PR_BUMP_SL_1UI, lane, 1);
1023 phy_write_lane(dev, &NPU2_PHY_RX_PR_BUMP_SL_1UI, lane, 0);
1024 }
1025 }
1026 }
1027
npu2_opencapi_phy_init(struct npu2_dev * dev)1028 void npu2_opencapi_phy_init(struct npu2_dev *dev)
1029 {
1030 run_procedure(dev, 5); /* procedure_phy_tx_zcal */
1031 /*
1032 * This is only required for OpenCAPI - Hostboot tries to set this
1033 * on systems where it can tell a link is OpenCAPI, but for
1034 * Witherspoon it needs to be done in skiboot after device detection.
1035 */
1036 phy_write(dev, &NPU2_PHY_RX_RC_ENABLE_AUTO_RECAL, 0x1);
1037 }
1038
npu2_opencapi_phy_reset(struct npu2_dev * dev)1039 void npu2_opencapi_phy_reset(struct npu2_dev *dev)
1040 {
1041 run_procedure(dev, 4); /* procedure_phy_reset */
1042 run_procedure(dev, 6); /* procedure_phy_rx_dccal */
1043 }
1044
npu2_opencapi_phy_prbs31(struct npu2_dev * dev)1045 void npu2_opencapi_phy_prbs31(struct npu2_dev *dev)
1046 {
1047 phy_write(dev, &NPU2_PHY_TX_DRV_DATA_PATTERN_GCRMSG, 0xD);
1048 }
1049