1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef __PCI_H
18 #define __PCI_H
19
20 #include <opal.h>
21 #include <device.h>
22 #include <lock.h>
23 #include <bitmap.h>
24 #include <ccan/list/list.h>
25
26 #define PCITRACE(_p, _bdfn, fmt, a...) \
27 prlog(PR_TRACE, "PHB#%04x:%02x:%02x.%x " fmt, \
28 (_p)->opal_id, \
29 ((_bdfn) >> 8) & 0xff, \
30 ((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
31 #define PCIDBG(_p, _bdfn, fmt, a...) \
32 prlog(PR_DEBUG, "PHB#%04x:%02x:%02x.%x " fmt, \
33 (_p)->opal_id, \
34 ((_bdfn) >> 8) & 0xff, \
35 ((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
36 #define PCINOTICE(_p, _bdfn, fmt, a...) \
37 prlog(PR_NOTICE, "PHB#%04x:%02x:%02x.%x " fmt, \
38 (_p)->opal_id, \
39 ((_bdfn) >> 8) & 0xff, \
40 ((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
41 #define PCIERR(_p, _bdfn, fmt, a...) \
42 prlog(PR_ERR, "PHB#%04x:%02x:%02x.%x " fmt, \
43 (_p)->opal_id, \
44 ((_bdfn) >> 8) & 0xff, \
45 ((_bdfn) >> 3) & 0x1f, (_bdfn) & 0x7, ## a)
46
47 struct pci_device;
48 struct pci_cfg_reg_filter;
49
50 typedef int64_t (*pci_cfg_reg_func)(void *dev,
51 struct pci_cfg_reg_filter *pcrf,
52 uint32_t offset, uint32_t len,
53 uint32_t *data, bool write);
54 typedef void (*pci_cap_free_data_func)(void *data);
55 struct pci_cfg_reg_filter {
56 uint32_t flags;
57 #define PCI_REG_FLAG_READ 0x1
58 #define PCI_REG_FLAG_WRITE 0x2
59 #define PCI_REG_FLAG_MASK 0x3
60 uint32_t start;
61 uint32_t len;
62 uint8_t *data;
63 pci_cfg_reg_func func;
64 struct list_node link;
65 };
66
67 /*
68 * While this might not be necessary in the long run, the existing
69 * Linux kernels expect us to provide a device-tree that contains
70 * a representation of all PCI devices below the host bridge. Thus
71 * we need to perform a bus scan. We don't need to assign MMIO/IO
72 * resources, but we do need to assign bus numbers in a way that
73 * is going to be compatible with the HW constraints for PE filtering
74 * that is naturally aligned power of twos for ranges below a bridge.
75 *
76 * Thus the structure pci_device is used for the tracking of the
77 * detected devices and the later generation of the device-tree.
78 *
79 * We do not keep a separate structure for a bus, however a device
80 * can have children in which case a device is a bridge.
81 *
82 * Because this is likely to change, we avoid putting too much
83 * information in that structure nor relying on it for anything
84 * else but the construction of the flat device-tree.
85 */
86 struct pci_device {
87 uint16_t bdfn;
88 bool is_bridge;
89 bool is_multifunction;
90 bool is_vf;
91 uint8_t dev_type; /* PCIE */
92 uint8_t primary_bus;
93 uint8_t secondary_bus;
94 uint8_t subordinate_bus;
95 uint32_t scan_map;
96
97 uint32_t vdid;
98 uint32_t sub_vdid;
99 #define PCI_VENDOR_ID(x) ((x) & 0xFFFF)
100 #define PCI_DEVICE_ID(x) ((x) >> 16)
101 uint32_t class;
102 uint64_t cap_list;
103 struct {
104 uint32_t pos;
105 void *data;
106 pci_cap_free_data_func free_func;
107 } cap[64];
108 uint32_t mps; /* Max payload size capability */
109
110 uint32_t pcrf_start;
111 uint32_t pcrf_end;
112 struct list_head pcrf;
113
114 /*
115 * Relaxed ordering is a feature which allows PCIe devices accessing GPU
116 * memory to bypass the normal PCIe ordering rules to increase
117 * performance. It is enabled on a per-PEC basis so every device on a
118 * PEC must support it before we can enable it.
119 */
120 bool allow_relaxed_ordering;
121
122 struct dt_node *dn;
123 struct pci_slot *slot;
124 struct pci_device *parent;
125 struct phb *phb;
126 struct list_head children;
127 struct list_node link;
128 };
129
pci_set_cap(struct pci_device * pd,int id,int pos,void * data,pci_cap_free_data_func free_func,bool ext)130 static inline void pci_set_cap(struct pci_device *pd, int id, int pos,
131 void *data, pci_cap_free_data_func free_func,
132 bool ext)
133 {
134 if (!ext) {
135 pd->cap_list |= (0x1ul << id);
136 pd->cap[id].pos = pos;
137 pd->cap[id].data = data;
138 pd->cap[id].free_func = free_func;
139 } else {
140 pd->cap_list |= (0x1ul << (id + 32));
141 pd->cap[id + 32].pos = pos;
142 pd->cap[id + 32].data = data;
143 pd->cap[id + 32].free_func = free_func;
144 }
145 }
146
pci_has_cap(struct pci_device * pd,int id,bool ext)147 static inline bool pci_has_cap(struct pci_device *pd,
148 int id, bool ext)
149 {
150 if (!ext)
151 return !!(pd->cap_list & (0x1ul << id));
152 else
153 return !!(pd->cap_list & (0x1ul << (id + 32)));
154 }
155
pci_cap(struct pci_device * pd,int id,bool ext)156 static inline int pci_cap(struct pci_device *pd,
157 int id, bool ext)
158 {
159 if (!ext)
160 return pd->cap[id].pos;
161 else
162 return pd->cap[id + 32].pos;
163 }
164
pci_cap_data(struct pci_device * pd,int id,bool ext)165 static inline void *pci_cap_data(struct pci_device *pd, int id, bool ext)
166 {
167 if (!ext)
168 return pd->cap[id].data;
169 else
170 return pd->cap[id + 32].data;
171 }
172
173 /*
174 * When generating the device-tree, we need to keep track of
175 * the LSI mapping & swizzle it. This state structure is
176 * passed by the PHB to pci_add_nodes() and will be used
177 * internally.
178 *
179 * We assume that the interrupt parent (PIC) #address-cells
180 * is 0 and #interrupt-cells has a max value of 2.
181 */
182 struct pci_lsi_state {
183 #define MAX_INT_SIZE 2
184 uint32_t int_size; /* #cells */
185 uint32_t int_val[4][MAX_INT_SIZE]; /* INTA...INTD */
186 uint32_t int_parent[4];
187 };
188
189 /*
190 * NOTE: All PCI functions return negative OPAL error codes
191 *
192 * In addition, some functions may return a positive timeout
193 * value or some other state information, see the description
194 * of individual functions. If nothing is specified, it's
195 * just an error code or 0 (success).
196 *
197 * Functions that operate asynchronously will return a positive
198 * delay value and will require the ->poll() op to be called after
199 * that delay. ->poll() will then return success, a negative error
200 * code, or another delay.
201 *
202 * Note: If an asynchronous function returns 0, it has completed
203 * successfully and does not require a call to ->poll(). Similarly
204 * if ->poll() is called while no operation is in progress, it will
205 * simply return 0 (success)
206 *
207 * Note that all functions except ->lock() itself assume that the
208 * caller is holding the PHB lock.
209 *
210 * TODO: Add more interfaces to control things like link width
211 * reduction for power savings etc...
212 */
213
214 struct phb;
215 extern int last_phb_id;
216
217 struct phb_ops {
218 /*
219 * Config space ops
220 */
221 int64_t (*cfg_read8)(struct phb *phb, uint32_t bdfn,
222 uint32_t offset, uint8_t *data);
223 int64_t (*cfg_read16)(struct phb *phb, uint32_t bdfn,
224 uint32_t offset, uint16_t *data);
225 int64_t (*cfg_read32)(struct phb *phb, uint32_t bdfn,
226 uint32_t offset, uint32_t *data);
227 int64_t (*cfg_write8)(struct phb *phb, uint32_t bdfn,
228 uint32_t offset, uint8_t data);
229 int64_t (*cfg_write16)(struct phb *phb, uint32_t bdfn,
230 uint32_t offset, uint16_t data);
231 int64_t (*cfg_write32)(struct phb *phb, uint32_t bdfn,
232 uint32_t offset, uint32_t data);
233
234 /*
235 * Bus number selection. See pci_scan() for a description
236 */
237 uint8_t (*choose_bus)(struct phb *phb, struct pci_device *bridge,
238 uint8_t candidate, uint8_t *max_bus,
239 bool *use_max);
240 int64_t (*get_reserved_pe_number)(struct phb *phb);
241
242 /*
243 * Device init method is called after a device has been detected
244 * and before probing further. It can alter things like scan_map
245 * for bridge ports etc...
246 */
247 int (*device_init)(struct phb *phb, struct pci_device *device,
248 void *data);
249 void (*device_remove)(struct phb *phb, struct pci_device *pd);
250
251 /* PHB final fixup is called after PCI probing is completed */
252 void (*phb_final_fixup)(struct phb *phb);
253
254 /*
255 * EEH methods
256 *
257 * The various arguments are identical to the corresponding
258 * OPAL functions
259 */
260 int64_t (*eeh_freeze_status)(struct phb *phb, uint64_t pe_number,
261 uint8_t *freeze_state,
262 uint16_t *pci_error_type,
263 uint16_t *severity);
264 int64_t (*eeh_freeze_clear)(struct phb *phb, uint64_t pe_number,
265 uint64_t eeh_action_token);
266 int64_t (*eeh_freeze_set)(struct phb *phb, uint64_t pe_number,
267 uint64_t eeh_action_token);
268 int64_t (*err_inject)(struct phb *phb, uint64_t pe_number,
269 uint32_t type, uint32_t func, uint64_t addr,
270 uint64_t mask);
271 int64_t (*get_diag_data2)(struct phb *phb, void *diag_buffer,
272 uint64_t diag_buffer_len);
273 int64_t (*next_error)(struct phb *phb, uint64_t *first_frozen_pe,
274 uint16_t *pci_error_type, uint16_t *severity);
275
276 /*
277 * Other IODA methods
278 *
279 * The various arguments are identical to the corresponding
280 * OPAL functions
281 */
282 int64_t (*pci_reinit)(struct phb *phb, uint64_t scope, uint64_t data);
283 int64_t (*phb_mmio_enable)(struct phb *phb, uint16_t window_type,
284 uint16_t window_num, uint16_t enable);
285
286 int64_t (*set_phb_mem_window)(struct phb *phb, uint16_t window_type,
287 uint16_t window_num, uint64_t addr,
288 uint64_t pci_addr, uint64_t size);
289
290 int64_t (*map_pe_mmio_window)(struct phb *phb, uint64_t pe_number,
291 uint16_t window_type, uint16_t window_num,
292 uint16_t segment_num);
293
294 int64_t (*set_pe)(struct phb *phb, uint64_t pe_number,
295 uint64_t bus_dev_func, uint8_t bus_compare,
296 uint8_t dev_compare, uint8_t func_compare,
297 uint8_t pe_action);
298
299 int64_t (*set_peltv)(struct phb *phb, uint32_t parent_pe,
300 uint32_t child_pe, uint8_t state);
301
302 int64_t (*map_pe_dma_window)(struct phb *phb, uint64_t pe_number,
303 uint16_t window_id, uint16_t tce_levels,
304 uint64_t tce_table_addr,
305 uint64_t tce_table_size,
306 uint64_t tce_page_size);
307
308 int64_t (*map_pe_dma_window_real)(struct phb *phb, uint64_t pe_number,
309 uint16_t dma_window_number,
310 uint64_t pci_start_addr,
311 uint64_t pci_mem_size);
312
313 int64_t (*set_mve)(struct phb *phb, uint32_t mve_number,
314 uint64_t pe_number);
315
316 int64_t (*set_mve_enable)(struct phb *phb, uint32_t mve_number,
317 uint32_t state);
318
319 int64_t (*set_xive_pe)(struct phb *phb, uint64_t pe_number,
320 uint32_t xive_num);
321
322 int64_t (*get_msi_32)(struct phb *phb, uint64_t mve_number,
323 uint32_t xive_num, uint8_t msi_range,
324 uint32_t *msi_address, uint32_t *message_data);
325
326 int64_t (*get_msi_64)(struct phb *phb, uint64_t mve_number,
327 uint32_t xive_num, uint8_t msi_range,
328 uint64_t *msi_address, uint32_t *message_data);
329
330 int64_t (*ioda_reset)(struct phb *phb, bool purge);
331
332 int64_t (*papr_errinjct_reset)(struct phb *phb);
333
334 /*
335 * IODA2 PCI interfaces
336 */
337 int64_t (*pci_msi_eoi)(struct phb *phb, uint32_t hwirq);
338
339 /* TCE Kill abstraction */
340 int64_t (*tce_kill)(struct phb *phb, uint32_t kill_type,
341 uint64_t pe_number, uint32_t tce_size,
342 uint64_t dma_addr, uint32_t npages);
343
344 /* Put phb in capi mode or pcie mode */
345 int64_t (*set_capi_mode)(struct phb *phb, uint64_t mode,
346 uint64_t pe_number);
347
348 int64_t (*set_capp_recovery)(struct phb *phb);
349
350 /* PCI peer-to-peer setup */
351 void (*set_p2p)(struct phb *phb, uint64_t mode, uint64_t flags,
352 uint16_t pe_number);
353
354 /* Get/set PBCQ Tunnel BAR register */
355 void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr);
356 int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr);
357 };
358
359 enum phb_type {
360 phb_type_pci,
361 phb_type_pcix_v1,
362 phb_type_pcix_v2,
363 phb_type_pcie_v1,
364 phb_type_pcie_v2,
365 phb_type_pcie_v3,
366 phb_type_pcie_v4,
367 phb_type_npu_v2,
368 phb_type_npu_v2_opencapi,
369 };
370
371
372 extern bool verbose_eeh;
373
374 struct phb {
375 struct dt_node *dt_node;
376 int opal_id;
377 uint32_t scan_map;
378 enum phb_type phb_type;
379 struct lock lock;
380 struct list_head devices;
381 struct list_head virt_devices;
382 const struct phb_ops *ops;
383 struct pci_lsi_state lstate;
384 uint32_t mps;
385 bitmap_t *filter_map;
386
387 /* PCI-X only slot info, for PCI-E this is in the RC bridge */
388 struct pci_slot *slot;
389
390 /* Base location code used to generate the children one */
391 const char *base_loc_code;
392
393 /* Additional data the platform might need to attach */
394 void *platform_data;
395 };
396
phb_lock(struct phb * phb)397 static inline void phb_lock(struct phb *phb)
398 {
399 lock(&phb->lock);
400 }
401
phb_unlock(struct phb * phb)402 static inline void phb_unlock(struct phb *phb)
403 {
404 unlock(&phb->lock);
405 }
406
407 /* Config space ops wrappers */
pci_cfg_read8(struct phb * phb,uint32_t bdfn,uint32_t offset,uint8_t * data)408 static inline int64_t pci_cfg_read8(struct phb *phb, uint32_t bdfn,
409 uint32_t offset, uint8_t *data)
410 {
411 return phb->ops->cfg_read8(phb, bdfn, offset, data);
412 }
413
pci_cfg_read16(struct phb * phb,uint32_t bdfn,uint32_t offset,uint16_t * data)414 static inline int64_t pci_cfg_read16(struct phb *phb, uint32_t bdfn,
415 uint32_t offset, uint16_t *data)
416 {
417 return phb->ops->cfg_read16(phb, bdfn, offset, data);
418 }
419
pci_cfg_read32(struct phb * phb,uint32_t bdfn,uint32_t offset,uint32_t * data)420 static inline int64_t pci_cfg_read32(struct phb *phb, uint32_t bdfn,
421 uint32_t offset, uint32_t *data)
422 {
423 return phb->ops->cfg_read32(phb, bdfn, offset, data);
424 }
425
pci_cfg_write8(struct phb * phb,uint32_t bdfn,uint32_t offset,uint8_t data)426 static inline int64_t pci_cfg_write8(struct phb *phb, uint32_t bdfn,
427 uint32_t offset, uint8_t data)
428 {
429 return phb->ops->cfg_write8(phb, bdfn, offset, data);
430 }
431
pci_cfg_write16(struct phb * phb,uint32_t bdfn,uint32_t offset,uint16_t data)432 static inline int64_t pci_cfg_write16(struct phb *phb, uint32_t bdfn,
433 uint32_t offset, uint16_t data)
434 {
435 return phb->ops->cfg_write16(phb, bdfn, offset, data);
436 }
437
pci_cfg_write32(struct phb * phb,uint32_t bdfn,uint32_t offset,uint32_t data)438 static inline int64_t pci_cfg_write32(struct phb *phb, uint32_t bdfn,
439 uint32_t offset, uint32_t data)
440 {
441 return phb->ops->cfg_write32(phb, bdfn, offset, data);
442 }
443
444 /* Utilities */
445 extern void pci_remove_bus(struct phb *phb, struct list_head *list);
446 extern uint8_t pci_scan_bus(struct phb *phb, uint8_t bus, uint8_t max_bus,
447 struct list_head *list, struct pci_device *parent,
448 bool scan_downstream);
449 extern void pci_add_device_nodes(struct phb *phb,
450 struct list_head *list,
451 struct dt_node *parent_node,
452 struct pci_lsi_state *lstate,
453 uint8_t swizzle);
454 extern int64_t pci_find_cap(struct phb *phb, uint16_t bdfn, uint8_t cap);
455 extern int64_t pci_find_ecap(struct phb *phb, uint16_t bdfn, uint16_t cap,
456 uint8_t *version);
457 extern void pci_init_capabilities(struct phb *phb, struct pci_device *pd);
458 extern bool pci_wait_crs(struct phb *phb, uint16_t bdfn, uint32_t *out_vdid);
459 extern void pci_restore_slot_bus_configs(struct pci_slot *slot);
460 extern void pci_device_init(struct phb *phb, struct pci_device *pd);
461 extern struct pci_device *pci_walk_dev(struct phb *phb,
462 struct pci_device *pd,
463 int (*cb)(struct phb *,
464 struct pci_device *,
465 void *),
466 void *userdata);
467 extern struct pci_device *pci_find_dev(struct phb *phb, uint16_t bdfn);
468 extern void pci_restore_bridge_buses(struct phb *phb, struct pci_device *pd);
469 extern struct pci_cfg_reg_filter *pci_find_cfg_reg_filter(struct pci_device *pd,
470 uint32_t start, uint32_t len);
471 extern int64_t pci_handle_cfg_filters(struct phb *phb, uint32_t bdfn,
472 uint32_t offset, uint32_t len,
473 uint32_t *data, bool write);
474 extern struct pci_cfg_reg_filter *pci_add_cfg_reg_filter(struct pci_device *pd,
475 uint32_t start, uint32_t len,
476 uint32_t flags, pci_cfg_reg_func func);
477
478 /* Manage PHBs */
479 #define OPAL_DYNAMIC_PHB_ID (~0)
480 extern int64_t pci_register_phb(struct phb *phb, int opal_id);
481 extern int64_t pci_unregister_phb(struct phb *phb);
482 extern struct phb *pci_get_phb(uint64_t phb_id);
483
__pci_next_phb_idx(uint64_t * phb_id)484 static inline struct phb *__pci_next_phb_idx(uint64_t *phb_id) {
485 struct phb *phb = NULL;
486 while (phb == NULL && *phb_id <= last_phb_id) {
487 phb = pci_get_phb((*phb_id)++);
488 }
489 return phb;
490 }
491
492 #define for_each_phb(phb) \
493 for (uint64_t __phb_idx = 0; \
494 (phb = __pci_next_phb_idx(&__phb_idx)) ; )
495
496 /* Device tree */
497 extern void pci_std_swizzle_irq_map(struct dt_node *dt_node,
498 struct pci_device *pd,
499 struct pci_lsi_state *lstate,
500 uint8_t swizzle);
501
502 /* Initialize all PCI slots */
503 extern void pci_init_slots(void);
504 extern int64_t pci_reset(void);
505
506 extern void opal_pci_eeh_set_evt(uint64_t phb_id);
507 extern void opal_pci_eeh_clear_evt(uint64_t phb_id);
508
509 #endif /* __PCI_H */
510