1 /* 2 * (C) Copyright 2000, 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * board/config.h - configuration options, board specific, 26 * for SinoVee Microsystems SC8xx series SBC 27 * http://www.fel.com.cn (Chinese) 28 * http://www.sinovee.com (English) 29 */ 30 31 #ifndef __CONFIG_H 32 #define __CONFIG_H 33 34 /* Custom configuration */ 35 /* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ 36 /* SC85T,SC860T, FEL8xx-AT(855T/860T) */ 37 /*#define CONFIG_FEL8xx_AT */ 38 /*#define CONFIG_LCD */ 39 /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ 40 /* #define CONFIG_50MHz */ 41 /* #define CONFIG_66MHz */ 42 /* #define CONFIG_75MHz */ 43 #define CONFIG_80MHz 44 /*#define CONFIG_100MHz */ 45 /* #define CONFIG_BUS_DIV2 1 */ 46 /* for BOOT device port size */ 47 /* #define CONFIG_BOOT_8B */ 48 #define CONFIG_BOOT_16B 49 /* #define CONFIG_BOOT_32B */ 50 /* #define CONFIG_CAN_DRIVER */ 51 /* #define DEBUG */ 52 #define CONFIG_FEC_ENET 53 54 /* #define CONFIG_SDRAM_16M */ 55 #define CONFIG_SDRAM_32M 56 /* #define CONFIG_SDRAM_64M */ 57 #define CONFIG_SYS_RESET_ADDRESS 0xffffffff 58 /* 59 * High Level Configuration Options 60 * (easy to change) 61 */ 62 63 /* #define CONFIG_MPC823 1 */ 64 /* #define CONFIG_MPC850 1 */ 65 #define CONFIG_MPC855 1 66 /* #define CONFIG_MPC860 1 */ 67 /* #define CONFIG_MPC860T 1 */ 68 69 #undef CONFIG_WATCHDOG /* watchdog */ 70 71 #define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ 72 73 #ifdef CONFIG_LCD /* with LCD controller ? */ 74 /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ 75 #endif 76 77 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 78 #undef CONFIG_8xx_CONS_SMC2 79 #undef CONFIG_8xx_CONS_NONE 80 #define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ 81 #if 0 82 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 83 #else 84 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 85 #endif 86 87 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 88 89 #define CONFIG_BOARD_TYPES 1 /* support board types */ 90 91 #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" 92 93 #undef CONFIG_BOOTARGS 94 #define CONFIG_EXTRA_ENV_SETTINGS \ 95 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 96 "nfsroot=${serverip}:${rootpath}\0" \ 97 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 98 "addip=setenv bootargs ${bootargs} " \ 99 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 100 ":${hostname}:${netdev}:off panic=1\0" \ 101 "flash_nfs=run nfsargs addip;" \ 102 "bootm ${kernel_addr}\0" \ 103 "flash_self=run ramargs addip;" \ 104 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 105 "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ 106 "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ 107 "bootfile=pImage-sc855t\0" \ 108 "kernel_addr=48000000\0" \ 109 "ramdisk_addr=48100000\0" \ 110 "" 111 #define CONFIG_BOOTCOMMAND \ 112 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 114 "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" 115 116 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 117 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 118 119 120 #ifdef CONFIG_LCD 121 # undef CONFIG_STATUS_LED /* disturbs display */ 122 #else 123 # define CONFIG_STATUS_LED 1 /* Status LED enabled */ 124 #endif /* CONFIG_LCD */ 125 126 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 127 128 /* 129 * BOOTP options 130 */ 131 #define CONFIG_BOOTP_SUBNETMASK 132 #define CONFIG_BOOTP_GATEWAY 133 #define CONFIG_BOOTP_HOSTNAME 134 #define CONFIG_BOOTP_BOOTPATH 135 #define CONFIG_BOOTP_BOOTFILESIZE 136 137 #define CONFIG_MAC_PARTITION 138 #define CONFIG_DOS_PARTITION 139 140 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 141 142 143 /* 144 * Command line configuration. 145 */ 146 #include <config_cmd_default.h> 147 148 #define CONFIG_CMD_ASKENV 149 #define CONFIG_CMD_DHCP 150 #define CONFIG_CMD_DATE 151 152 /* 153 * Miscellaneous configurable options 154 */ 155 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 156 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 157 158 #ifdef CONFIG_SYS_HUSH_PARSER 159 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 160 #endif 161 162 #if defined(CONFIG_CMD_KGDB) 163 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 164 #else 165 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 166 #endif 167 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 168 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 169 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 170 171 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 172 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 173 174 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 175 176 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 177 178 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 179 180 /* 181 * Low Level Configuration Settings 182 * (address mappings, register initial values, etc.) 183 * You should know what you are doing if you make changes here. 184 */ 185 /*----------------------------------------------------------------------- 186 * Internal Memory Mapped Register 187 */ 188 #define CONFIG_SYS_IMMR 0xFF000000 189 190 /*----------------------------------------------------------------------- 191 * Definitions for initial stack pointer and data area (in DPRAM) 192 */ 193 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 194 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 195 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 196 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 197 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 198 199 /*----------------------------------------------------------------------- 200 * Start addresses for the final memory configuration 201 * (Set up by the startup code) 202 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 203 */ 204 #define CONFIG_SYS_SDRAM_BASE 0x00000000 205 #define CONFIG_SYS_FLASH_BASE 0x40000000 206 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ 207 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 208 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 209 210 /* 211 * For booting Linux, the board info and command line data 212 * have to be in the first 8 MB of memory, since this is 213 * the maximum mapped by the Linux kernel during initialization. 214 */ 215 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 216 217 /*----------------------------------------------------------------------- 218 * FLASH organization 219 */ 220 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 221 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 222 223 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 224 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 225 226 #define CONFIG_ENV_IS_IN_FLASH 1 227 228 #ifdef CONFIG_BOOT_8B 229 #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ 230 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ 231 #elif defined (CONFIG_BOOT_16B) 232 #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ 233 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ 234 #elif defined (CONFIG_BOOT_32B) 235 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 236 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 237 #endif 238 239 /* Address and size of Redundant Environment Sector */ 240 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 241 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 242 243 244 /*----------------------------------------------------------------------- 245 * Hardware Information Block 246 */ 247 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 248 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 249 #define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ 250 251 /*----------------------------------------------------------------------- 252 * Cache Configuration 253 */ 254 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 255 #if defined(CONFIG_CMD_KGDB) 256 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 257 #endif 258 259 /*----------------------------------------------------------------------- 260 * SYPCR - System Protection Control 11-9 261 * SYPCR can only be written once after reset! 262 *----------------------------------------------------------------------- 263 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 264 */ 265 #if defined(CONFIG_WATCHDOG) 266 /*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 267 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 268 */ 269 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ 270 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 271 #else 272 #define CONFIG_SYS_SYPCR 0xffffff88 273 #endif 274 275 /*----------------------------------------------------------------------- 276 * SIUMCR - SIU Module Configuration 11-6 277 *----------------------------------------------------------------------- 278 * PCMCIA config., multi-function pin tri-state 279 */ 280 #ifndef CONFIG_CAN_DRIVER 281 /*#define CONFIG_SYS_SIUMCR 0x00610c00 */ 282 #define CONFIG_SYS_SIUMCR 0x00000000 283 #else /* we must activate GPL5 in the SIUMCR for CAN */ 284 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 285 #endif /* CONFIG_CAN_DRIVER */ 286 287 /*----------------------------------------------------------------------- 288 * TBSCR - Time Base Status and Control 11-26 289 *----------------------------------------------------------------------- 290 * Clear Reference Interrupt Status, Timebase freezing enabled 291 */ 292 #define CONFIG_SYS_TBSCR 0x0001 293 294 /*----------------------------------------------------------------------- 295 * RTCSC - Real-Time Clock Status and Control Register 11-27 296 *----------------------------------------------------------------------- 297 */ 298 #define CONFIG_SYS_RTCSC 0x00c3 299 300 /*----------------------------------------------------------------------- 301 * PISCR - Periodic Interrupt Status and Control 11-31 302 *----------------------------------------------------------------------- 303 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 304 */ 305 #define CONFIG_SYS_PISCR 0x0000 306 307 /*----------------------------------------------------------------------- 308 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 309 *----------------------------------------------------------------------- 310 * Reset PLL lock status sticky bit, timer expired status bit and timer 311 * interrupt status bit 312 */ 313 #if defined (CONFIG_100MHz) 314 #define CONFIG_SYS_PLPRCR 0x06301000 315 #define CONFIG_8xx_GCLK_FREQ 100000000 316 #elif defined (CONFIG_80MHz) 317 #define CONFIG_SYS_PLPRCR 0x04f01000 318 #define CONFIG_8xx_GCLK_FREQ 80000000 319 #elif defined(CONFIG_75MHz) 320 #define CONFIG_SYS_PLPRCR 0x04a00100 321 #define CONFIG_8xx_GCLK_FREQ 75000000 322 #elif defined(CONFIG_66MHz) 323 #define CONFIG_SYS_PLPRCR 0x04101000 324 #define CONFIG_8xx_GCLK_FREQ 66000000 325 #elif defined(CONFIG_50MHz) 326 #define CONFIG_SYS_PLPRCR 0x03101000 327 #define CONFIG_8xx_GCLK_FREQ 50000000 328 #endif 329 330 /*----------------------------------------------------------------------- 331 * SCCR - System Clock and reset Control Register 15-27 332 *----------------------------------------------------------------------- 333 * Set clock output, timebase and RTC source and divider, 334 * power management and some other internal clocks 335 */ 336 #define SCCR_MASK SCCR_EBDF11 337 #ifdef CONFIG_BUS_DIV2 338 #define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL 339 #else /* up to 50 MHz we use a 1:1 clock */ 340 #define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL 341 #endif 342 343 /*----------------------------------------------------------------------- 344 * PCMCIA stuff 345 *----------------------------------------------------------------------- 346 * 347 */ 348 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 349 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 350 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 351 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 352 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 353 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 354 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 355 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 356 357 /*----------------------------------------------------------------------- 358 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 359 *----------------------------------------------------------------------- 360 */ 361 362 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 363 364 #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ 365 #undef CONFIG_IDE_LED /* LED for ide not supported */ 366 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 367 368 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 369 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 370 371 #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010 372 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 373 /*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */ 374 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O 375 */ 376 #define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses 377 */ 378 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers 379 */ 380 #define CONFIG_ATAPI 381 #define CONFIG_SYS_PIO_MODE 0 382 383 /*----------------------------------------------------------------------- 384 * 385 *----------------------------------------------------------------------- 386 * 387 */ 388 /*#define CONFIG_SYS_DER 0x2002000F*/ 389 #define CONFIG_SYS_DER 0x0 390 391 /* 392 * Init Memory Controller: 393 * 394 * BR0/1 and OR0/1 (FLASH) 395 */ 396 397 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 398 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 399 400 /* used to re-map FLASH both when starting from SRAM or FLASH: 401 * restrict access enough to keep SRAM working (if any) 402 * but not too much to meddle with FLASH accesses 403 */ 404 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 405 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 406 407 /* 408 * FLASH timing: 409 */ 410 #if defined(CONFIG_100MHz) 411 #define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4 412 #define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 413 #define CONFIG_SYS_MxMR_PTx 0x61000000 414 #define CONFIG_SYS_MPTPR 0x400 415 416 #elif defined(CONFIG_80MHz) 417 #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 418 #define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 419 #define CONFIG_SYS_MxMR_PTx 0x4e000000 420 #define CONFIG_SYS_MPTPR 0x400 421 422 #elif defined(CONFIG_75MHz) 423 #define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4 424 #define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 425 #define CONFIG_SYS_MxMR_PTx 0x49000000 426 #define CONFIG_SYS_MPTPR 0x400 427 428 #elif defined(CONFIG_66MHz) 429 #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 430 OR_SCY_3_CLK | OR_EHTR | OR_BI) 431 /*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */ 432 #define CONFIG_SYS_OR_TIMING_DOC 0x000003f4 433 #define CONFIG_SYS_MxMR_PTx 0x40000000 434 #define CONFIG_SYS_MPTPR 0x400 435 436 #else /* 50 MHz */ 437 #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 438 #define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 439 #define CONFIG_SYS_MxMR_PTx 0x30000000 440 #define CONFIG_SYS_MPTPR 0x400 441 #endif /*CONFIG_??MHz */ 442 443 444 #if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ 445 #define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH) 446 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) 447 #elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ 448 #define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH) 449 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) 450 #elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ 451 #define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH) 452 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 453 #else 454 #error Boot device port size missing. 455 #endif 456 457 /* 458 * Disk-On-Chip configuration 459 */ 460 461 #define CONFIG_SYS_DOC_SHORT_TIMEOUT 462 #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ 463 464 #define CONFIG_SYS_DOC_SUPPORT_2000 465 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 466 #define CONFIG_SYS_DOC_BASE 0x80000000 467 468 469 /* 470 * Internal Definitions 471 * 472 * Boot Flags 473 */ 474 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 475 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 476 477 #endif /* __CONFIG_H */ 478