1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Sun6i platform dram controller init.
4 *
5 * (C) Copyright 2007-2012
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Berg Xing <bergxing@allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
11 */
12 #include <common.h>
13 #include <errno.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/dram.h>
17 #include <asm/arch/prcm.h>
18
19 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
20
21 struct dram_sun6i_para {
22 u8 bus_width;
23 u8 chan;
24 u8 rank;
25 u8 rows;
26 u16 page_size;
27 };
28
mctl_sys_init(void)29 static void mctl_sys_init(void)
30 {
31 struct sunxi_ccm_reg * const ccm =
32 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
33 const int dram_clk_div = 2;
34
35 clock_set_pll5(DRAM_CLK * dram_clk_div, false);
36
37 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
38 CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
39 CCM_DRAMCLK_CFG_UPD);
40 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
41
42 writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
43
44 /* deassert mctl reset */
45 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
46
47 /* enable mctl clock */
48 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
49 }
50
mctl_dll_init(int ch_index,struct dram_sun6i_para * para)51 static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
52 {
53 struct sunxi_mctl_phy_reg *mctl_phy;
54
55 if (ch_index == 0)
56 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
57 else
58 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
59
60 /* disable + reset dlls */
61 writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
62 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
63 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
64 if (para->bus_width == 32) {
65 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
66 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
67 }
68 udelay(2);
69
70 /* enable + reset dlls */
71 writel(0, &mctl_phy->acdllcr);
72 writel(0, &mctl_phy->dx0dllcr);
73 writel(0, &mctl_phy->dx1dllcr);
74 if (para->bus_width == 32) {
75 writel(0, &mctl_phy->dx2dllcr);
76 writel(0, &mctl_phy->dx3dllcr);
77 }
78 udelay(22);
79
80 /* enable and release reset of dlls */
81 writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
82 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
83 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
84 if (para->bus_width == 32) {
85 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
86 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
87 }
88 udelay(22);
89 }
90
mctl_rank_detect(u32 * gsr0,int rank)91 static bool mctl_rank_detect(u32 *gsr0, int rank)
92 {
93 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
94 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
95
96 mctl_await_completion(gsr0, done, done);
97 mctl_await_completion(gsr0 + 0x10, done, done);
98
99 return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
100 }
101
mctl_channel_init(int ch_index,struct dram_sun6i_para * para)102 static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
103 {
104 struct sunxi_mctl_com_reg * const mctl_com =
105 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
106 struct sunxi_mctl_ctl_reg *mctl_ctl;
107 struct sunxi_mctl_phy_reg *mctl_phy;
108
109 if (ch_index == 0) {
110 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
111 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
112 } else {
113 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
114 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
115 }
116
117 writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
118 mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
119
120 /* PHY initialization */
121 writel(MCTL_PGCR, &mctl_phy->pgcr);
122 writel(MCTL_MR0, &mctl_phy->mr0);
123 writel(MCTL_MR1, &mctl_phy->mr1);
124 writel(MCTL_MR2, &mctl_phy->mr2);
125 writel(MCTL_MR3, &mctl_phy->mr3);
126
127 writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
128 &mctl_phy->ptr0);
129
130 writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
131 writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
132
133 writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
134 (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
135 (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
136 &mctl_phy->dtpr0);
137
138 writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
139 (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
140 ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
141 (MCTL_TAOND << 0), &mctl_phy->dtpr1);
142
143 writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
144 (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
145
146 writel(1, &mctl_ctl->dfitphyupdtype0);
147 writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
148 writel(MCTL_DSGCR, &mctl_phy->dsgcr);
149 writel(MCTL_DXCCR, &mctl_phy->dxccr);
150 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
151 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
152 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
153 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
154
155 mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03);
156
157 writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
158
159 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
160 writel(MCTL_PIR_STEP1, &mctl_phy->pir);
161 udelay(10);
162 mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
163
164 /* rank detect */
165 if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
166 para->rank = 1;
167 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
168 }
169
170 /*
171 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
172 * assume nothing is connected to channel 1.
173 */
174 if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
175 para->chan = 1;
176 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
177 return;
178 }
179
180 /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
181 if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
182 para->bus_width = 16;
183 para->page_size = 2048;
184 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
185 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
186 clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
187 clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
188 }
189
190 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
191 writel(MCTL_PIR_STEP2, &mctl_phy->pir);
192 udelay(10);
193 mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11);
194
195 if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
196 panic("Training error initialising DRAM\n");
197
198 /* Move to configure state */
199 writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
200 mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01);
201
202 /* Set number of clks per micro-second */
203 writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
204 /* Set number of clks per 100 nano-seconds */
205 writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
206 /* Set memory timing registers */
207 writel(MCTL_TREFI, &mctl_ctl->trefi);
208 writel(MCTL_TMRD, &mctl_ctl->tmrd);
209 writel(MCTL_TRFC, &mctl_ctl->trfc);
210 writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
211 writel(MCTL_TRTW, &mctl_ctl->trtw);
212 writel(MCTL_TAL, &mctl_ctl->tal);
213 writel(MCTL_TCL, &mctl_ctl->tcl);
214 writel(MCTL_TCWL, &mctl_ctl->tcwl);
215 writel(MCTL_TRAS, &mctl_ctl->tras);
216 writel(MCTL_TRC, &mctl_ctl->trc);
217 writel(MCTL_TRCD, &mctl_ctl->trcd);
218 writel(MCTL_TRRD, &mctl_ctl->trrd);
219 writel(MCTL_TRTP, &mctl_ctl->trtp);
220 writel(MCTL_TWR, &mctl_ctl->twr);
221 writel(MCTL_TWTR, &mctl_ctl->twtr);
222 writel(MCTL_TEXSR, &mctl_ctl->texsr);
223 writel(MCTL_TXP, &mctl_ctl->txp);
224 writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
225 writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
226 writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
227 writel(MCTL_TDQS, &mctl_ctl->tdqs);
228 writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
229 writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
230 writel(MCTL_TCKE, &mctl_ctl->tcke);
231 writel(MCTL_TMOD, &mctl_ctl->tmod);
232 writel(MCTL_TRSTL, &mctl_ctl->trstl);
233 writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
234 writel(MCTL_TMRR, &mctl_ctl->tmrr);
235 writel(MCTL_TCKESR, &mctl_ctl->tckesr);
236 writel(MCTL_TDPD, &mctl_ctl->tdpd);
237
238 /* Unknown magic performed by boot0 */
239 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
240 clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
241
242 /* Select 16/32-bits mode for MCTL */
243 if (para->bus_width == 16)
244 setbits_le32(&mctl_ctl->ppcfg, 1);
245
246 /* Set DFI timing registers */
247 writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
248 writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
249 writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
250 writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
251
252 writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
253
254 /* DFI update configuration register */
255 writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
256
257 /* Move to access state */
258 writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
259 mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x03);
260 }
261
mctl_com_init(struct dram_sun6i_para * para)262 static void mctl_com_init(struct dram_sun6i_para *para)
263 {
264 struct sunxi_mctl_com_reg * const mctl_com =
265 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
266 struct sunxi_mctl_phy_reg * const mctl_phy1 =
267 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
268 struct sunxi_prcm_reg * const prcm =
269 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
270
271 writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
272 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
273 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
274 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
275
276 /* Unknown magic performed by boot0 */
277 setbits_le32(&mctl_com->dbgcr, (1 << 6));
278
279 if (para->chan == 1) {
280 /* Shutdown channel 1 */
281 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
282 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
283 clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
284 /*
285 * CH0 ?? this is what boot0 does. Leave as is until we can
286 * confirm this.
287 */
288 setbits_le32(&prcm->vdd_sys_pwroff,
289 PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
290 }
291 }
292
mctl_port_cfg(void)293 static void mctl_port_cfg(void)
294 {
295 struct sunxi_mctl_com_reg * const mctl_com =
296 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
297 struct sunxi_ccm_reg * const ccm =
298 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
299
300 /* enable DRAM AXI clock for CPU access */
301 setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
302
303 /* Bunch of magic writes performed by boot0 */
304 writel(0x00400302, &mctl_com->rmcr[0]);
305 writel(0x01000307, &mctl_com->rmcr[1]);
306 writel(0x00400302, &mctl_com->rmcr[2]);
307 writel(0x01000307, &mctl_com->rmcr[3]);
308 writel(0x01000307, &mctl_com->rmcr[4]);
309 writel(0x01000303, &mctl_com->rmcr[6]);
310 writel(0x01000303, &mctl_com->mmcr[0]);
311 writel(0x00400310, &mctl_com->mmcr[1]);
312 writel(0x01000307, &mctl_com->mmcr[2]);
313 writel(0x01000303, &mctl_com->mmcr[3]);
314 writel(0x01800303, &mctl_com->mmcr[4]);
315 writel(0x01800303, &mctl_com->mmcr[5]);
316 writel(0x01800303, &mctl_com->mmcr[6]);
317 writel(0x01800303, &mctl_com->mmcr[7]);
318 writel(0x01000303, &mctl_com->mmcr[8]);
319 writel(0x00000002, &mctl_com->mmcr[15]);
320 writel(0x00000310, &mctl_com->mbagcr[0]);
321 writel(0x00400310, &mctl_com->mbagcr[1]);
322 writel(0x00400310, &mctl_com->mbagcr[2]);
323 writel(0x00000307, &mctl_com->mbagcr[3]);
324 writel(0x00000317, &mctl_com->mbagcr[4]);
325 writel(0x00000307, &mctl_com->mbagcr[5]);
326 }
327
sunxi_dram_init(void)328 unsigned long sunxi_dram_init(void)
329 {
330 struct sunxi_mctl_com_reg * const mctl_com =
331 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
332 u32 offset;
333 int bank, bus, columns;
334
335 /* Set initial parameters, these get modified by the autodetect code */
336 struct dram_sun6i_para para = {
337 .bus_width = 32,
338 .chan = 2,
339 .rank = 2,
340 .page_size = 4096,
341 .rows = 16,
342 };
343
344 /* A31s only has one channel */
345 if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
346 para.chan = 1;
347
348 mctl_sys_init();
349
350 mctl_dll_init(0, ¶);
351 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
352
353 if (para.chan == 2) {
354 mctl_dll_init(1, ¶);
355 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
356 }
357
358 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
359
360 mctl_channel_init(0, ¶);
361 if (para.chan == 2)
362 mctl_channel_init(1, ¶);
363
364 mctl_com_init(¶);
365 mctl_port_cfg();
366
367 /*
368 * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
369 * 8 bit banks / 1 rank mode.
370 */
371 clrsetbits_le32(&mctl_com->cr,
372 MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
373 MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
374 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
375 MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
376 MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
377
378 /* Detect and set page size */
379 for (columns = 7; columns < 20; columns++) {
380 if (mctl_mem_matches(1 << columns))
381 break;
382 }
383 bus = (para.bus_width == 32) ? 2 : 1;
384 columns -= bus;
385 para.page_size = (1 << columns) * (bus << 1);
386 clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
387 MCTL_CR_PAGE_SIZE(para.page_size));
388
389 /* Detect and set rows */
390 for (para.rows = 11; para.rows < 16; para.rows++) {
391 offset = 1 << (para.rows + columns + bus);
392 if (mctl_mem_matches(offset))
393 break;
394 }
395 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
396 MCTL_CR_ROW(para.rows));
397
398 /* Detect bank size */
399 offset = 1 << (para.rows + columns + bus + 2);
400 bank = mctl_mem_matches(offset) ? 0 : 1;
401
402 /* Restore interleave, chan and rank values, set bank size */
403 clrsetbits_le32(&mctl_com->cr,
404 MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
405 MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
406 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
407 MCTL_CR_RANK(para.rank));
408
409 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
410 }
411