1
2/* Capstone Disassembly Engine, http://www.capstone-engine.org */
3/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
4
5/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
6|*                                                                            *|
7|* Target Register Enum Values                                                *|
8|*                                                                            *|
9|* Automatically generated file, do not edit!                                 *|
10|*                                                                            *|
11\*===----------------------------------------------------------------------===*/
12
13#ifdef GET_REGINFO_ENUM
14#undef GET_REGINFO_ENUM
15
16enum {
17  ARM_NoRegister,
18  ARM_APSR = 1,
19  ARM_APSR_NZCV = 2,
20  ARM_CPSR = 3,
21  ARM_FPEXC = 4,
22  ARM_FPINST = 5,
23  ARM_FPSCR = 6,
24  ARM_FPSCR_NZCV = 7,
25  ARM_FPSID = 8,
26  ARM_ITSTATE = 9,
27  ARM_LR = 10,
28  ARM_PC = 11,
29  ARM_SP = 12,
30  ARM_SPSR = 13,
31  ARM_D0 = 14,
32  ARM_D1 = 15,
33  ARM_D2 = 16,
34  ARM_D3 = 17,
35  ARM_D4 = 18,
36  ARM_D5 = 19,
37  ARM_D6 = 20,
38  ARM_D7 = 21,
39  ARM_D8 = 22,
40  ARM_D9 = 23,
41  ARM_D10 = 24,
42  ARM_D11 = 25,
43  ARM_D12 = 26,
44  ARM_D13 = 27,
45  ARM_D14 = 28,
46  ARM_D15 = 29,
47  ARM_D16 = 30,
48  ARM_D17 = 31,
49  ARM_D18 = 32,
50  ARM_D19 = 33,
51  ARM_D20 = 34,
52  ARM_D21 = 35,
53  ARM_D22 = 36,
54  ARM_D23 = 37,
55  ARM_D24 = 38,
56  ARM_D25 = 39,
57  ARM_D26 = 40,
58  ARM_D27 = 41,
59  ARM_D28 = 42,
60  ARM_D29 = 43,
61  ARM_D30 = 44,
62  ARM_D31 = 45,
63  ARM_FPINST2 = 46,
64  ARM_MVFR0 = 47,
65  ARM_MVFR1 = 48,
66  ARM_MVFR2 = 49,
67  ARM_Q0 = 50,
68  ARM_Q1 = 51,
69  ARM_Q2 = 52,
70  ARM_Q3 = 53,
71  ARM_Q4 = 54,
72  ARM_Q5 = 55,
73  ARM_Q6 = 56,
74  ARM_Q7 = 57,
75  ARM_Q8 = 58,
76  ARM_Q9 = 59,
77  ARM_Q10 = 60,
78  ARM_Q11 = 61,
79  ARM_Q12 = 62,
80  ARM_Q13 = 63,
81  ARM_Q14 = 64,
82  ARM_Q15 = 65,
83  ARM_R0 = 66,
84  ARM_R1 = 67,
85  ARM_R2 = 68,
86  ARM_R3 = 69,
87  ARM_R4 = 70,
88  ARM_R5 = 71,
89  ARM_R6 = 72,
90  ARM_R7 = 73,
91  ARM_R8 = 74,
92  ARM_R9 = 75,
93  ARM_R10 = 76,
94  ARM_R11 = 77,
95  ARM_R12 = 78,
96  ARM_S0 = 79,
97  ARM_S1 = 80,
98  ARM_S2 = 81,
99  ARM_S3 = 82,
100  ARM_S4 = 83,
101  ARM_S5 = 84,
102  ARM_S6 = 85,
103  ARM_S7 = 86,
104  ARM_S8 = 87,
105  ARM_S9 = 88,
106  ARM_S10 = 89,
107  ARM_S11 = 90,
108  ARM_S12 = 91,
109  ARM_S13 = 92,
110  ARM_S14 = 93,
111  ARM_S15 = 94,
112  ARM_S16 = 95,
113  ARM_S17 = 96,
114  ARM_S18 = 97,
115  ARM_S19 = 98,
116  ARM_S20 = 99,
117  ARM_S21 = 100,
118  ARM_S22 = 101,
119  ARM_S23 = 102,
120  ARM_S24 = 103,
121  ARM_S25 = 104,
122  ARM_S26 = 105,
123  ARM_S27 = 106,
124  ARM_S28 = 107,
125  ARM_S29 = 108,
126  ARM_S30 = 109,
127  ARM_S31 = 110,
128  ARM_D0_D2 = 111,
129  ARM_D1_D3 = 112,
130  ARM_D2_D4 = 113,
131  ARM_D3_D5 = 114,
132  ARM_D4_D6 = 115,
133  ARM_D5_D7 = 116,
134  ARM_D6_D8 = 117,
135  ARM_D7_D9 = 118,
136  ARM_D8_D10 = 119,
137  ARM_D9_D11 = 120,
138  ARM_D10_D12 = 121,
139  ARM_D11_D13 = 122,
140  ARM_D12_D14 = 123,
141  ARM_D13_D15 = 124,
142  ARM_D14_D16 = 125,
143  ARM_D15_D17 = 126,
144  ARM_D16_D18 = 127,
145  ARM_D17_D19 = 128,
146  ARM_D18_D20 = 129,
147  ARM_D19_D21 = 130,
148  ARM_D20_D22 = 131,
149  ARM_D21_D23 = 132,
150  ARM_D22_D24 = 133,
151  ARM_D23_D25 = 134,
152  ARM_D24_D26 = 135,
153  ARM_D25_D27 = 136,
154  ARM_D26_D28 = 137,
155  ARM_D27_D29 = 138,
156  ARM_D28_D30 = 139,
157  ARM_D29_D31 = 140,
158  ARM_Q0_Q1 = 141,
159  ARM_Q1_Q2 = 142,
160  ARM_Q2_Q3 = 143,
161  ARM_Q3_Q4 = 144,
162  ARM_Q4_Q5 = 145,
163  ARM_Q5_Q6 = 146,
164  ARM_Q6_Q7 = 147,
165  ARM_Q7_Q8 = 148,
166  ARM_Q8_Q9 = 149,
167  ARM_Q9_Q10 = 150,
168  ARM_Q10_Q11 = 151,
169  ARM_Q11_Q12 = 152,
170  ARM_Q12_Q13 = 153,
171  ARM_Q13_Q14 = 154,
172  ARM_Q14_Q15 = 155,
173  ARM_Q0_Q1_Q2_Q3 = 156,
174  ARM_Q1_Q2_Q3_Q4 = 157,
175  ARM_Q2_Q3_Q4_Q5 = 158,
176  ARM_Q3_Q4_Q5_Q6 = 159,
177  ARM_Q4_Q5_Q6_Q7 = 160,
178  ARM_Q5_Q6_Q7_Q8 = 161,
179  ARM_Q6_Q7_Q8_Q9 = 162,
180  ARM_Q7_Q8_Q9_Q10 = 163,
181  ARM_Q8_Q9_Q10_Q11 = 164,
182  ARM_Q9_Q10_Q11_Q12 = 165,
183  ARM_Q10_Q11_Q12_Q13 = 166,
184  ARM_Q11_Q12_Q13_Q14 = 167,
185  ARM_Q12_Q13_Q14_Q15 = 168,
186  ARM_R12_SP = 169,
187  ARM_R0_R1 = 170,
188  ARM_R2_R3 = 171,
189  ARM_R4_R5 = 172,
190  ARM_R6_R7 = 173,
191  ARM_R8_R9 = 174,
192  ARM_R10_R11 = 175,
193  ARM_D0_D1_D2 = 176,
194  ARM_D1_D2_D3 = 177,
195  ARM_D2_D3_D4 = 178,
196  ARM_D3_D4_D5 = 179,
197  ARM_D4_D5_D6 = 180,
198  ARM_D5_D6_D7 = 181,
199  ARM_D6_D7_D8 = 182,
200  ARM_D7_D8_D9 = 183,
201  ARM_D8_D9_D10 = 184,
202  ARM_D9_D10_D11 = 185,
203  ARM_D10_D11_D12 = 186,
204  ARM_D11_D12_D13 = 187,
205  ARM_D12_D13_D14 = 188,
206  ARM_D13_D14_D15 = 189,
207  ARM_D14_D15_D16 = 190,
208  ARM_D15_D16_D17 = 191,
209  ARM_D16_D17_D18 = 192,
210  ARM_D17_D18_D19 = 193,
211  ARM_D18_D19_D20 = 194,
212  ARM_D19_D20_D21 = 195,
213  ARM_D20_D21_D22 = 196,
214  ARM_D21_D22_D23 = 197,
215  ARM_D22_D23_D24 = 198,
216  ARM_D23_D24_D25 = 199,
217  ARM_D24_D25_D26 = 200,
218  ARM_D25_D26_D27 = 201,
219  ARM_D26_D27_D28 = 202,
220  ARM_D27_D28_D29 = 203,
221  ARM_D28_D29_D30 = 204,
222  ARM_D29_D30_D31 = 205,
223  ARM_D0_D2_D4 = 206,
224  ARM_D1_D3_D5 = 207,
225  ARM_D2_D4_D6 = 208,
226  ARM_D3_D5_D7 = 209,
227  ARM_D4_D6_D8 = 210,
228  ARM_D5_D7_D9 = 211,
229  ARM_D6_D8_D10 = 212,
230  ARM_D7_D9_D11 = 213,
231  ARM_D8_D10_D12 = 214,
232  ARM_D9_D11_D13 = 215,
233  ARM_D10_D12_D14 = 216,
234  ARM_D11_D13_D15 = 217,
235  ARM_D12_D14_D16 = 218,
236  ARM_D13_D15_D17 = 219,
237  ARM_D14_D16_D18 = 220,
238  ARM_D15_D17_D19 = 221,
239  ARM_D16_D18_D20 = 222,
240  ARM_D17_D19_D21 = 223,
241  ARM_D18_D20_D22 = 224,
242  ARM_D19_D21_D23 = 225,
243  ARM_D20_D22_D24 = 226,
244  ARM_D21_D23_D25 = 227,
245  ARM_D22_D24_D26 = 228,
246  ARM_D23_D25_D27 = 229,
247  ARM_D24_D26_D28 = 230,
248  ARM_D25_D27_D29 = 231,
249  ARM_D26_D28_D30 = 232,
250  ARM_D27_D29_D31 = 233,
251  ARM_D0_D2_D4_D6 = 234,
252  ARM_D1_D3_D5_D7 = 235,
253  ARM_D2_D4_D6_D8 = 236,
254  ARM_D3_D5_D7_D9 = 237,
255  ARM_D4_D6_D8_D10 = 238,
256  ARM_D5_D7_D9_D11 = 239,
257  ARM_D6_D8_D10_D12 = 240,
258  ARM_D7_D9_D11_D13 = 241,
259  ARM_D8_D10_D12_D14 = 242,
260  ARM_D9_D11_D13_D15 = 243,
261  ARM_D10_D12_D14_D16 = 244,
262  ARM_D11_D13_D15_D17 = 245,
263  ARM_D12_D14_D16_D18 = 246,
264  ARM_D13_D15_D17_D19 = 247,
265  ARM_D14_D16_D18_D20 = 248,
266  ARM_D15_D17_D19_D21 = 249,
267  ARM_D16_D18_D20_D22 = 250,
268  ARM_D17_D19_D21_D23 = 251,
269  ARM_D18_D20_D22_D24 = 252,
270  ARM_D19_D21_D23_D25 = 253,
271  ARM_D20_D22_D24_D26 = 254,
272  ARM_D21_D23_D25_D27 = 255,
273  ARM_D22_D24_D26_D28 = 256,
274  ARM_D23_D25_D27_D29 = 257,
275  ARM_D24_D26_D28_D30 = 258,
276  ARM_D25_D27_D29_D31 = 259,
277  ARM_D1_D2 = 260,
278  ARM_D3_D4 = 261,
279  ARM_D5_D6 = 262,
280  ARM_D7_D8 = 263,
281  ARM_D9_D10 = 264,
282  ARM_D11_D12 = 265,
283  ARM_D13_D14 = 266,
284  ARM_D15_D16 = 267,
285  ARM_D17_D18 = 268,
286  ARM_D19_D20 = 269,
287  ARM_D21_D22 = 270,
288  ARM_D23_D24 = 271,
289  ARM_D25_D26 = 272,
290  ARM_D27_D28 = 273,
291  ARM_D29_D30 = 274,
292  ARM_D1_D2_D3_D4 = 275,
293  ARM_D3_D4_D5_D6 = 276,
294  ARM_D5_D6_D7_D8 = 277,
295  ARM_D7_D8_D9_D10 = 278,
296  ARM_D9_D10_D11_D12 = 279,
297  ARM_D11_D12_D13_D14 = 280,
298  ARM_D13_D14_D15_D16 = 281,
299  ARM_D15_D16_D17_D18 = 282,
300  ARM_D17_D18_D19_D20 = 283,
301  ARM_D19_D20_D21_D22 = 284,
302  ARM_D21_D22_D23_D24 = 285,
303  ARM_D23_D24_D25_D26 = 286,
304  ARM_D25_D26_D27_D28 = 287,
305  ARM_D27_D28_D29_D30 = 288,
306  ARM_NUM_TARGET_REGS 	// 289
307};
308
309// Register classes
310enum {
311  ARM_HPRRegClassID = 0,
312  ARM_SPRRegClassID = 1,
313  ARM_GPRRegClassID = 2,
314  ARM_GPRwithAPSRRegClassID = 3,
315  ARM_SPR_8RegClassID = 4,
316  ARM_GPRnopcRegClassID = 5,
317  ARM_rGPRRegClassID = 6,
318  ARM_tGPRwithpcRegClassID = 7,
319  ARM_hGPRRegClassID = 8,
320  ARM_tGPRRegClassID = 9,
321  ARM_GPRnopc_and_hGPRRegClassID = 10,
322  ARM_hGPR_and_rGPRRegClassID = 11,
323  ARM_tcGPRRegClassID = 12,
324  ARM_tGPR_and_tcGPRRegClassID = 13,
325  ARM_CCRRegClassID = 14,
326  ARM_GPRspRegClassID = 15,
327  ARM_hGPR_and_tGPRwithpcRegClassID = 16,
328  ARM_hGPR_and_tcGPRRegClassID = 17,
329  ARM_DPRRegClassID = 18,
330  ARM_DPR_VFP2RegClassID = 19,
331  ARM_DPR_8RegClassID = 20,
332  ARM_GPRPairRegClassID = 21,
333  ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 22,
334  ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 23,
335  ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 24,
336  ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 25,
337  ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26,
338  ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 27,
339  ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 28,
340  ARM_DPairSpcRegClassID = 29,
341  ARM_DPairSpc_with_ssub_0RegClassID = 30,
342  ARM_DPairSpc_with_ssub_4RegClassID = 31,
343  ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32,
344  ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33,
345  ARM_DPairRegClassID = 34,
346  ARM_DPair_with_ssub_0RegClassID = 35,
347  ARM_QPRRegClassID = 36,
348  ARM_DPair_with_ssub_2RegClassID = 37,
349  ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 38,
350  ARM_QPR_VFP2RegClassID = 39,
351  ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 40,
352  ARM_QPR_8RegClassID = 41,
353  ARM_DTripleRegClassID = 42,
354  ARM_DTripleSpcRegClassID = 43,
355  ARM_DTripleSpc_with_ssub_0RegClassID = 44,
356  ARM_DTriple_with_ssub_0RegClassID = 45,
357  ARM_DTriple_with_qsub_0_in_QPRRegClassID = 46,
358  ARM_DTriple_with_ssub_2RegClassID = 47,
359  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48,
360  ARM_DTripleSpc_with_ssub_4RegClassID = 49,
361  ARM_DTriple_with_ssub_4RegClassID = 50,
362  ARM_DTripleSpc_with_ssub_8RegClassID = 51,
363  ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52,
364  ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 53,
365  ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54,
366  ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55,
367  ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 56,
368  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57,
369  ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58,
370  ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59,
371  ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 60,
372  ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61,
373  ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62,
374  ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 63,
375  ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64,
376  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65,
377  ARM_DQuadSpcRegClassID = 66,
378  ARM_DQuadSpc_with_ssub_0RegClassID = 67,
379  ARM_DQuadSpc_with_ssub_4RegClassID = 68,
380  ARM_DQuadSpc_with_ssub_8RegClassID = 69,
381  ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70,
382  ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71,
383  ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72,
384  ARM_DQuadRegClassID = 73,
385  ARM_DQuad_with_ssub_0RegClassID = 74,
386  ARM_DQuad_with_ssub_2RegClassID = 75,
387  ARM_QQPRRegClassID = 76,
388  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77,
389  ARM_DQuad_with_ssub_4RegClassID = 78,
390  ARM_DQuad_with_ssub_6RegClassID = 79,
391  ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 80,
392  ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81,
393  ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
394  ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 83,
395  ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84,
396  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85,
397  ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 86,
398  ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87,
399  ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 88,
400  ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
401  ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 90,
402  ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 91,
403  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92,
404  ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93,
405  ARM_QQQQPRRegClassID = 94,
406  ARM_QQQQPR_with_ssub_0RegClassID = 95,
407  ARM_QQQQPR_with_ssub_4RegClassID = 96,
408  ARM_QQQQPR_with_ssub_8RegClassID = 97,
409  ARM_QQQQPR_with_ssub_12RegClassID = 98,
410  ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99,
411  ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100,
412  ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101,
413  ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102,
414};
415
416// Subregister indices
417enum {
418  ARM_NoSubRegister,
419  ARM_dsub_0,	// 1
420  ARM_dsub_1,	// 2
421  ARM_dsub_2,	// 3
422  ARM_dsub_3,	// 4
423  ARM_dsub_4,	// 5
424  ARM_dsub_5,	// 6
425  ARM_dsub_6,	// 7
426  ARM_dsub_7,	// 8
427  ARM_gsub_0,	// 9
428  ARM_gsub_1,	// 10
429  ARM_qqsub_0,	// 11
430  ARM_qqsub_1,	// 12
431  ARM_qsub_0,	// 13
432  ARM_qsub_1,	// 14
433  ARM_qsub_2,	// 15
434  ARM_qsub_3,	// 16
435  ARM_ssub_0,	// 17
436  ARM_ssub_1,	// 18
437  ARM_ssub_2,	// 19
438  ARM_ssub_3,	// 20
439  ARM_ssub_4,	// 21
440  ARM_ssub_5,	// 22
441  ARM_ssub_6,	// 23
442  ARM_ssub_7,	// 24
443  ARM_ssub_8,	// 25
444  ARM_ssub_9,	// 26
445  ARM_ssub_10,	// 27
446  ARM_ssub_11,	// 28
447  ARM_ssub_12,	// 29
448  ARM_ssub_13,	// 30
449  ARM_dsub_7_then_ssub_0,	// 31
450  ARM_dsub_7_then_ssub_1,	// 32
451  ARM_ssub_0_ssub_1_ssub_4_ssub_5,	// 33
452  ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,	// 34
453  ARM_ssub_2_ssub_3_ssub_6_ssub_7,	// 35
454  ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,	// 36
455  ARM_ssub_2_ssub_3_ssub_4_ssub_5,	// 37
456  ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,	// 38
457  ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 39
458  ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5,	// 40
459  ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,	// 41
460  ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 42
461  ARM_ssub_4_ssub_5_ssub_8_ssub_9,	// 43
462  ARM_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 44
463  ARM_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 45
464  ARM_ssub_6_ssub_7_dsub_5,	// 46
465  ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5,	// 47
466  ARM_ssub_6_ssub_7_dsub_5_dsub_7,	// 48
467  ARM_ssub_6_ssub_7_ssub_8_ssub_9,	// 49
468  ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 50
469  ARM_ssub_8_ssub_9_ssub_12_ssub_13,	// 51
470  ARM_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 52
471  ARM_dsub_5_dsub_7,	// 53
472  ARM_dsub_5_ssub_12_ssub_13_dsub_7,	// 54
473  ARM_dsub_5_ssub_12_ssub_13,	// 55
474  ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2,	// 56
475  ARM_NUM_TARGET_SUBREGS
476};
477
478#endif // GET_REGINFO_ENUM
479
480#ifdef GET_REGINFO_MC_DESC
481#undef GET_REGINFO_MC_DESC
482
483
484static const MCPhysReg ARMRegDiffLists[] = {
485  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
486  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
487  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
488  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
489  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
490  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
491  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
492  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
493  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
494  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
495  /* 105 */ 40, 1, 1, 1, 1, 0,
496  /* 111 */ 42, 1, 1, 1, 1, 0,
497  /* 117 */ 42, 1, 1, 1, 0,
498  /* 122 */ 64510, 1, 1, 1, 0,
499  /* 127 */ 65015, 1, 1, 1, 0,
500  /* 132 */ 65282, 1, 1, 1, 0,
501  /* 137 */ 65348, 1, 1, 1, 0,
502  /* 142 */ 13, 1, 1, 0,
503  /* 146 */ 42, 1, 1, 0,
504  /* 150 */ 65388, 1, 1, 0,
505  /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
506  /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
507  /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
508  /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0,
509  /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0,
510  /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0,
511  /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0,
512  /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0,
513  /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0,
514  /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0,
515  /* 254 */ 65489, 133, 65416, 1, 1, 0,
516  /* 260 */ 65490, 133, 65416, 1, 1, 0,
517  /* 266 */ 65491, 133, 65416, 1, 1, 0,
518  /* 272 */ 65492, 133, 65416, 1, 1, 0,
519  /* 278 */ 65493, 133, 65416, 1, 1, 0,
520  /* 284 */ 65494, 133, 65416, 1, 1, 0,
521  /* 290 */ 65495, 133, 65416, 1, 1, 0,
522  /* 296 */ 65496, 133, 65416, 1, 1, 0,
523  /* 302 */ 65497, 133, 65416, 1, 1, 0,
524  /* 308 */ 65498, 133, 65416, 1, 1, 0,
525  /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
526  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
527  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
528  /* 339 */ 65326, 1, 3, 1, 0,
529  /* 344 */ 13, 1, 0,
530  /* 347 */ 14, 1, 0,
531  /* 350 */ 65, 1, 0,
532  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
533  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
534  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
535  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
536  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
537  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
538  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
539  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
540  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
541  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
542  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
543  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
544  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
545  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
546  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
547  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
548  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
549  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
550  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
551  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
552  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
553  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
554  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
555  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
556  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
557  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
558  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
559  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
560  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
561  /* 556 */ 65045, 1, 0,
562  /* 559 */ 65260, 1, 0,
563  /* 562 */ 65299, 1, 0,
564  /* 565 */ 65300, 1, 0,
565  /* 568 */ 65301, 1, 0,
566  /* 571 */ 65302, 1, 0,
567  /* 574 */ 65303, 1, 0,
568  /* 577 */ 65304, 1, 0,
569  /* 580 */ 65305, 1, 0,
570  /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
571  /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
572  /* 600 */ 65488, 13, 121, 65416, 1, 0,
573  /* 606 */ 65489, 13, 121, 65416, 1, 0,
574  /* 612 */ 65490, 13, 121, 65416, 1, 0,
575  /* 618 */ 65491, 13, 121, 65416, 1, 0,
576  /* 624 */ 65492, 13, 121, 65416, 1, 0,
577  /* 630 */ 65493, 13, 121, 65416, 1, 0,
578  /* 636 */ 65494, 13, 121, 65416, 1, 0,
579  /* 642 */ 65495, 13, 121, 65416, 1, 0,
580  /* 648 */ 65496, 13, 121, 65416, 1, 0,
581  /* 654 */ 65497, 13, 121, 65416, 1, 0,
582  /* 660 */ 65498, 13, 121, 65416, 1, 0,
583  /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0,
584  /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0,
585  /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0,
586  /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0,
587  /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0,
588  /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0,
589  /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0,
590  /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0,
591  /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0,
592  /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0,
593  /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0,
594  /* 765 */ 65488, 133, 65416, 1, 0,
595  /* 770 */ 65499, 134, 65416, 1, 0,
596  /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
597  /* 783 */ 65432, 1, 0,
598  /* 786 */ 65433, 1, 0,
599  /* 789 */ 65434, 1, 0,
600  /* 792 */ 65435, 1, 0,
601  /* 795 */ 65436, 1, 0,
602  /* 798 */ 65437, 1, 0,
603  /* 801 */ 65464, 1, 0,
604  /* 804 */ 65508, 1, 0,
605  /* 807 */ 65509, 1, 0,
606  /* 810 */ 65510, 1, 0,
607  /* 813 */ 65511, 1, 0,
608  /* 816 */ 65512, 1, 0,
609  /* 819 */ 65513, 1, 0,
610  /* 822 */ 65514, 1, 0,
611  /* 825 */ 65515, 1, 0,
612  /* 828 */ 65520, 1, 0,
613  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
614  /* 839 */ 65136, 1, 3, 1, 2, 0,
615  /* 845 */ 65326, 1, 2, 0,
616  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
617  /* 856 */ 65136, 1, 2, 2, 0,
618  /* 861 */ 65080, 1, 2, 2, 2, 0,
619  /* 867 */ 65330, 2, 2, 2, 0,
620  /* 872 */ 65080, 1, 3, 2, 2, 0,
621  /* 878 */ 65358, 2, 2, 0,
622  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
623  /* 889 */ 65136, 1, 3, 2, 0,
624  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
625  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
626  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
627  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
628  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
629  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
630  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
631  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
632  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
633  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
634  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
635  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
636  /* 1038 */ 65344, 2, 2, 93, 2, 0,
637  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
638  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
639  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
640  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
641  /* 1080 */ 65439, 2, 0,
642  /* 1083 */ 65453, 2, 0,
643  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
644  /* 1094 */ 65136, 1, 3, 1, 3, 0,
645  /* 1100 */ 65326, 1, 3, 0,
646  /* 1104 */ 5, 0,
647  /* 1106 */ 140, 65486, 13, 0,
648  /* 1110 */ 14, 0,
649  /* 1112 */ 126, 65501, 15, 0,
650  /* 1116 */ 10, 66, 0,
651  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
652  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
653  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
654  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
655  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
656  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
657  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
658  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
659  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
660  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
661  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
662  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
663  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
664  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
665  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
666  /* 1359 */ 91, 0,
667  /* 1361 */ 98, 0,
668  /* 1363 */ 99, 0,
669  /* 1365 */ 100, 0,
670  /* 1367 */ 101, 0,
671  /* 1369 */ 102, 0,
672  /* 1371 */ 103, 0,
673  /* 1373 */ 104, 0,
674  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
675  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
676  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
677  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
678  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
679  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
680  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
681  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
682  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
683  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
684  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
685  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
686  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
687  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
688  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
689  /* 1526 */ 157, 0,
690  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
691  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
692  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
693  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
694  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
695  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
696  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
697  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
698  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
699  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
700  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
701  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
702  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
703  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
704  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
705  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
706  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
707  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
708  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
709  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
710  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
711  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
712  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
713  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
714  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
715  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
716  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
717  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
718  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
719  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
720  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
721  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
722  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
723  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
724  /* 2455 */ 65487, 13, 121, 65416, 0,
725  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
726  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
727  /* 2474 */ 65487, 133, 65416, 0,
728  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
729  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
730  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
731  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
732  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
733  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
734  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
735  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
736  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
737  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
738  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
739  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
740  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
741  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
742  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
743  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
744  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
745  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
746  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
747  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
748  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
749  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
750  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
751  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
752  /* 2832 */ 26, 65446, 92, 65445, 0,
753  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
754  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
755  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
756  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
757  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
758  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
759  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
760  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
761  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
762  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
763  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
764  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
765  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
766  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
767  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
768  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
769  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
770  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
771  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
772  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
773  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
774  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
775  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
776  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
777  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
778  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
779  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
780  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
781  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
782  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
783  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
784  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
785  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
786  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
787  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
788  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
789  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
790  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
791  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
792  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
793  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
794  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
795  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
796  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
797  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
798  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
799  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
800  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
801  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
802  /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
803  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
804  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
805  /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
806  /* 3839 */ 65298, 80, 1, 65456, 0,
807  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
808  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
809  /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
810  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
811  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
812  /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
813  /* 3948 */ 65439, 80, 1, 65457, 0,
814  /* 3953 */ 28, 65457, 0,
815  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
816  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
817  /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
818  /* 4002 */ 26, 65458, 80, 65457, 0,
819  /* 4007 */ 65439, 79, 1, 65458, 0,
820  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
821  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
822  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
823  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
824  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
825  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
826  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
827  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
828  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
829  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
830  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
831  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
832  /* 4114 */ 65445, 65470, 0,
833  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
834  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
835  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
836  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
837  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
838  /* 4182 */ 65534, 0,
839  /* 4184 */ 65535, 0,
840};
841
842static const uint16_t ARMSubRegIdxLists[] = {
843  /* 0 */ 1, 2, 0,
844  /* 3 */ 1, 17, 18, 2, 0,
845  /* 8 */ 1, 3, 0,
846  /* 11 */ 1, 17, 18, 3, 0,
847  /* 16 */ 9, 10, 0,
848  /* 19 */ 17, 18, 0,
849  /* 22 */ 1, 17, 18, 2, 19, 20, 0,
850  /* 29 */ 1, 17, 18, 3, 21, 22, 0,
851  /* 36 */ 1, 2, 3, 13, 33, 37, 0,
852  /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
853  /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
854  /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
855  /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
856  /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
857  /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
858  /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
859  /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
860  /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
861  /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
862  /* 188 */ 1, 3, 5, 33, 43, 0,
863  /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
864  /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
865  /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
866  /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
867  /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
868  /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
869  /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
870  /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
871  /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
872  /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
873  /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
874  /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
875  /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
876};
877
878static const MCRegisterDesc ARMRegDesc[] = {
879  { 12, 0, 0, 0, 0, 0 },
880  { 1235, 16, 16, 2, 66945, 0 },
881  { 1268, 16, 16, 2, 66945, 0 },
882  { 1240, 16, 16, 2, 66945, 0 },
883  { 1199, 16, 16, 2, 66945, 0 },
884  { 1250, 16, 16, 2, 66945, 0 },
885  { 1226, 16, 16, 2, 17664, 0 },
886  { 1257, 16, 16, 2, 17664, 0 },
887  { 1205, 16, 16, 2, 66913, 0 },
888  { 1211, 16, 16, 2, 66913, 0 },
889  { 1232, 16, 16, 2, 66913, 0 },
890  { 1196, 16, 16, 2, 66913, 0 },
891  { 1223, 16, 1526, 2, 66913, 0 },
892  { 1245, 16, 16, 2, 66913, 0 },
893  { 119, 350, 4013, 19, 13250, 8 },
894  { 248, 357, 2479, 19, 13250, 8 },
895  { 363, 364, 3957, 19, 13250, 8 },
896  { 479, 378, 3845, 19, 13250, 8 },
897  { 605, 392, 3893, 19, 13250, 8 },
898  { 723, 406, 3724, 19, 13250, 8 },
899  { 837, 420, 3780, 19, 13250, 8 },
900  { 943, 434, 3604, 19, 13250, 8 },
901  { 1057, 448, 3664, 19, 13250, 8 },
902  { 1163, 462, 3484, 19, 13250, 8 },
903  { 9, 476, 3544, 19, 13250, 8 },
904  { 141, 490, 3364, 19, 13250, 8 },
905  { 282, 504, 3424, 19, 13250, 8 },
906  { 408, 518, 3244, 19, 13250, 8 },
907  { 523, 532, 3304, 19, 13250, 8 },
908  { 649, 546, 3149, 19, 13250, 8 },
909  { 768, 16, 3208, 2, 17761, 0 },
910  { 882, 16, 3078, 2, 17761, 0 },
911  { 988, 16, 3113, 2, 17761, 0 },
912  { 1102, 16, 3008, 2, 17761, 0 },
913  { 59, 16, 3043, 2, 17761, 0 },
914  { 192, 16, 2938, 2, 17761, 0 },
915  { 336, 16, 2973, 2, 17761, 0 },
916  { 456, 16, 2868, 2, 17761, 0 },
917  { 575, 16, 2903, 2, 17761, 0 },
918  { 697, 16, 2797, 2, 17761, 0 },
919  { 804, 16, 2837, 2, 17761, 0 },
920  { 914, 16, 2363, 2, 17761, 0 },
921  { 1024, 16, 2411, 2, 17761, 0 },
922  { 1134, 16, 2384, 2, 17761, 0 },
923  { 95, 16, 2429, 2, 17761, 0 },
924  { 224, 16, 2789, 2, 17761, 0 },
925  { 390, 16, 16, 2, 17761, 0 },
926  { 125, 16, 16, 2, 17761, 0 },
927  { 257, 16, 16, 2, 17761, 0 },
928  { 381, 16, 16, 2, 17761, 0 },
929  { 122, 353, 1112, 22, 2196, 11 },
930  { 254, 374, 775, 22, 2196, 11 },
931  { 378, 402, 314, 22, 2196, 11 },
932  { 500, 430, 244, 22, 2196, 11 },
933  { 629, 458, 234, 22, 2196, 11 },
934  { 744, 486, 224, 22, 2196, 11 },
935  { 861, 514, 214, 22, 2196, 11 },
936  { 964, 542, 204, 22, 2196, 11 },
937  { 1081, 804, 194, 0, 12818, 20 },
938  { 1184, 807, 184, 0, 12818, 20 },
939  { 35, 810, 174, 0, 12818, 20 },
940  { 168, 813, 164, 0, 12818, 20 },
941  { 312, 816, 154, 0, 12818, 20 },
942  { 436, 819, 591, 0, 12818, 20 },
943  { 555, 822, 2447, 0, 12818, 20 },
944  { 677, 825, 1106, 0, 12818, 20 },
945  { 128, 16, 1373, 2, 66913, 0 },
946  { 260, 16, 1371, 2, 66913, 0 },
947  { 384, 16, 1371, 2, 66913, 0 },
948  { 506, 16, 1369, 2, 66913, 0 },
949  { 632, 16, 1369, 2, 66913, 0 },
950  { 750, 16, 1367, 2, 66913, 0 },
951  { 864, 16, 1367, 2, 66913, 0 },
952  { 970, 16, 1365, 2, 66913, 0 },
953  { 1084, 16, 1365, 2, 66913, 0 },
954  { 1190, 16, 1363, 2, 66913, 0 },
955  { 39, 16, 1363, 2, 66913, 0 },
956  { 176, 16, 1361, 2, 66913, 0 },
957  { 316, 16, 1359, 2, 66913, 0 },
958  { 131, 16, 4021, 2, 65585, 0 },
959  { 269, 16, 4012, 2, 65585, 0 },
960  { 387, 16, 2490, 2, 65585, 0 },
961  { 509, 16, 2478, 2, 65585, 0 },
962  { 635, 16, 3974, 2, 65585, 0 },
963  { 753, 16, 3956, 2, 65585, 0 },
964  { 867, 16, 3863, 2, 65585, 0 },
965  { 973, 16, 3844, 2, 65585, 0 },
966  { 1087, 16, 3914, 2, 65585, 0 },
967  { 1193, 16, 3892, 2, 65585, 0 },
968  { 43, 16, 3745, 2, 65585, 0 },
969  { 180, 16, 3723, 2, 65585, 0 },
970  { 320, 16, 3803, 2, 65585, 0 },
971  { 440, 16, 3779, 2, 65585, 0 },
972  { 559, 16, 3627, 2, 65585, 0 },
973  { 681, 16, 3603, 2, 65585, 0 },
974  { 788, 16, 3687, 2, 65585, 0 },
975  { 898, 16, 3663, 2, 65585, 0 },
976  { 1008, 16, 3507, 2, 65585, 0 },
977  { 1118, 16, 3483, 2, 65585, 0 },
978  { 79, 16, 3567, 2, 65585, 0 },
979  { 212, 16, 3543, 2, 65585, 0 },
980  { 356, 16, 3387, 2, 65585, 0 },
981  { 472, 16, 3363, 2, 65585, 0 },
982  { 595, 16, 3447, 2, 65585, 0 },
983  { 713, 16, 3423, 2, 65585, 0 },
984  { 824, 16, 3267, 2, 65585, 0 },
985  { 930, 16, 3243, 2, 65585, 0 },
986  { 1044, 16, 3327, 2, 65585, 0 },
987  { 1150, 16, 3303, 2, 65585, 0 },
988  { 115, 16, 3172, 2, 65585, 0 },
989  { 244, 16, 3148, 2, 65585, 0 },
990  { 360, 367, 4015, 29, 5426, 23 },
991  { 476, 381, 2502, 29, 5426, 23 },
992  { 602, 395, 3992, 29, 5426, 23 },
993  { 720, 409, 3882, 29, 5426, 23 },
994  { 834, 423, 3936, 29, 5426, 23 },
995  { 940, 437, 3767, 29, 5426, 23 },
996  { 1054, 451, 3827, 29, 5426, 23 },
997  { 1160, 465, 3651, 29, 5426, 23 },
998  { 6, 479, 3711, 29, 5426, 23 },
999  { 151, 493, 3531, 29, 5426, 23 },
1000  { 278, 507, 3591, 29, 5426, 23 },
1001  { 404, 521, 3411, 29, 5426, 23 },
1002  { 519, 535, 3471, 29, 5426, 23 },
1003  { 645, 549, 3291, 29, 5426, 23 },
1004  { 764, 4007, 3351, 11, 17602, 35 },
1005  { 878, 3948, 3196, 11, 13522, 35 },
1006  { 984, 1080, 3231, 8, 17329, 39 },
1007  { 1098, 1080, 3101, 8, 17329, 39 },
1008  { 55, 1080, 3136, 8, 17329, 39 },
1009  { 204, 1080, 3031, 8, 17329, 39 },
1010  { 332, 1080, 3066, 8, 17329, 39 },
1011  { 452, 1080, 2961, 8, 17329, 39 },
1012  { 571, 1080, 2996, 8, 17329, 39 },
1013  { 693, 1080, 2891, 8, 17329, 39 },
1014  { 800, 1080, 2926, 8, 17329, 39 },
1015  { 910, 1080, 2820, 8, 17329, 39 },
1016  { 1020, 1080, 2858, 8, 17329, 39 },
1017  { 1130, 1080, 2401, 8, 17329, 39 },
1018  { 91, 1080, 2440, 8, 17329, 39 },
1019  { 236, 1080, 2791, 8, 17329, 39 },
1020  { 251, 1339, 1114, 168, 1044, 57 },
1021  { 375, 1319, 347, 168, 1044, 57 },
1022  { 497, 1299, 142, 168, 1044, 57 },
1023  { 626, 1279, 142, 168, 1044, 57 },
1024  { 741, 1259, 142, 168, 1044, 57 },
1025  { 858, 1239, 142, 168, 1044, 57 },
1026  { 961, 1219, 142, 168, 1044, 57 },
1027  { 1078, 1203, 142, 88, 1456, 74 },
1028  { 1181, 1191, 142, 76, 2114, 87 },
1029  { 32, 1179, 142, 76, 2114, 87 },
1030  { 164, 1167, 142, 76, 2114, 87 },
1031  { 308, 1155, 142, 76, 2114, 87 },
1032  { 432, 1143, 142, 76, 2114, 87 },
1033  { 551, 1131, 344, 76, 2114, 87 },
1034  { 673, 1119, 1108, 76, 2114, 87 },
1035  { 491, 2156, 16, 474, 4, 149 },
1036  { 620, 2101, 16, 474, 4, 149 },
1037  { 735, 2046, 16, 474, 4, 149 },
1038  { 852, 1991, 16, 474, 4, 149 },
1039  { 955, 1936, 16, 474, 4, 149 },
1040  { 1072, 1885, 16, 423, 272, 166 },
1041  { 1175, 1838, 16, 376, 512, 181 },
1042  { 26, 1795, 16, 333, 720, 194 },
1043  { 158, 1756, 16, 294, 1186, 205 },
1044  { 301, 1717, 16, 294, 1186, 205 },
1045  { 424, 1678, 16, 294, 1186, 205 },
1046  { 543, 1639, 16, 294, 1186, 205 },
1047  { 665, 1600, 16, 294, 1186, 205 },
1048  { 1219, 4114, 16, 16, 17856, 2 },
1049  { 263, 783, 16, 16, 8946, 5 },
1050  { 503, 786, 16, 16, 8946, 5 },
1051  { 747, 789, 16, 16, 8946, 5 },
1052  { 967, 792, 16, 16, 8946, 5 },
1053  { 1187, 795, 16, 16, 8946, 5 },
1054  { 172, 798, 16, 16, 8946, 5 },
1055  { 366, 1513, 1113, 63, 1570, 28 },
1056  { 482, 4169, 2511, 63, 1570, 28 },
1057  { 611, 1500, 778, 63, 1570, 28 },
1058  { 726, 4156, 770, 63, 1570, 28 },
1059  { 843, 1487, 317, 63, 1570, 28 },
1060  { 946, 4143, 660, 63, 1570, 28 },
1061  { 1063, 1474, 308, 63, 1570, 28 },
1062  { 1166, 4130, 654, 63, 1570, 28 },
1063  { 16, 1461, 302, 63, 1570, 28 },
1064  { 134, 4117, 648, 63, 1570, 28 },
1065  { 289, 1448, 296, 63, 1570, 28 },
1066  { 412, 4101, 642, 63, 1570, 28 },
1067  { 531, 1435, 290, 63, 1570, 28 },
1068  { 653, 4088, 636, 63, 1570, 28 },
1069  { 776, 1424, 284, 52, 1680, 42 },
1070  { 886, 4079, 630, 43, 1872, 48 },
1071  { 996, 1417, 278, 36, 2401, 53 },
1072  { 1106, 4072, 624, 36, 2401, 53 },
1073  { 67, 1410, 272, 36, 2401, 53 },
1074  { 184, 4065, 618, 36, 2401, 53 },
1075  { 344, 1403, 266, 36, 2401, 53 },
1076  { 460, 4058, 612, 36, 2401, 53 },
1077  { 583, 1396, 260, 36, 2401, 53 },
1078  { 701, 4051, 606, 36, 2401, 53 },
1079  { 812, 1389, 254, 36, 2401, 53 },
1080  { 918, 4044, 600, 36, 2401, 53 },
1081  { 1032, 1382, 765, 36, 2401, 53 },
1082  { 1138, 4037, 2455, 36, 2401, 53 },
1083  { 103, 1375, 2474, 36, 2401, 53 },
1084  { 216, 4030, 1107, 36, 2401, 53 },
1085  { 599, 1026, 4018, 212, 5314, 92 },
1086  { 717, 1014, 3953, 212, 5314, 92 },
1087  { 831, 1002, 4002, 212, 5314, 92 },
1088  { 937, 990, 3909, 212, 5314, 92 },
1089  { 1051, 978, 3909, 212, 5314, 92 },
1090  { 1157, 966, 3798, 212, 5314, 92 },
1091  { 3, 954, 3798, 212, 5314, 92 },
1092  { 148, 942, 3682, 212, 5314, 92 },
1093  { 275, 930, 3682, 212, 5314, 92 },
1094  { 401, 918, 3562, 212, 5314, 92 },
1095  { 515, 906, 3562, 212, 5314, 92 },
1096  { 641, 894, 3442, 212, 5314, 92 },
1097  { 760, 1070, 3442, 202, 17506, 99 },
1098  { 874, 1060, 3322, 202, 13426, 99 },
1099  { 980, 1052, 3322, 194, 14226, 105 },
1100  { 1094, 1044, 3226, 194, 13698, 105 },
1101  { 51, 1038, 3226, 188, 14049, 110 },
1102  { 200, 1038, 3131, 188, 14049, 110 },
1103  { 328, 1038, 3131, 188, 14049, 110 },
1104  { 448, 1038, 3061, 188, 14049, 110 },
1105  { 567, 1038, 3061, 188, 14049, 110 },
1106  { 689, 1038, 2991, 188, 14049, 110 },
1107  { 796, 1038, 2991, 188, 14049, 110 },
1108  { 906, 1038, 2921, 188, 14049, 110 },
1109  { 1016, 1038, 2921, 188, 14049, 110 },
1110  { 1126, 1038, 2832, 188, 14049, 110 },
1111  { 87, 1038, 2855, 188, 14049, 110 },
1112  { 232, 1038, 2794, 188, 14049, 110 },
1113  { 828, 2677, 4010, 276, 5170, 114 },
1114  { 934, 2659, 3951, 276, 5170, 114 },
1115  { 1048, 2641, 3951, 276, 5170, 114 },
1116  { 1154, 2623, 3842, 276, 5170, 114 },
1117  { 0, 2605, 3842, 276, 5170, 114 },
1118  { 145, 2587, 3743, 276, 5170, 114 },
1119  { 272, 2569, 3743, 276, 5170, 114 },
1120  { 398, 2551, 3625, 276, 5170, 114 },
1121  { 512, 2533, 3625, 276, 5170, 114 },
1122  { 638, 2515, 3505, 276, 5170, 114 },
1123  { 756, 2773, 3505, 260, 17378, 123 },
1124  { 870, 2757, 3385, 260, 13298, 123 },
1125  { 976, 2743, 3385, 246, 14114, 131 },
1126  { 1090, 2729, 3265, 246, 13586, 131 },
1127  { 47, 2717, 3265, 234, 13954, 138 },
1128  { 196, 2705, 3170, 234, 13778, 138 },
1129  { 324, 2695, 3170, 224, 13873, 144 },
1130  { 444, 2695, 3099, 224, 13873, 144 },
1131  { 563, 2695, 3099, 224, 13873, 144 },
1132  { 685, 2695, 3029, 224, 13873, 144 },
1133  { 792, 2695, 3029, 224, 13873, 144 },
1134  { 902, 2695, 2959, 224, 13873, 144 },
1135  { 1012, 2695, 2959, 224, 13873, 144 },
1136  { 1122, 2695, 2856, 224, 13873, 144 },
1137  { 83, 2695, 2856, 224, 13873, 144 },
1138  { 228, 2695, 2795, 224, 13873, 144 },
1139  { 369, 360, 2509, 22, 1956, 11 },
1140  { 614, 388, 583, 22, 1956, 11 },
1141  { 846, 416, 756, 22, 1956, 11 },
1142  { 1066, 444, 747, 22, 1956, 11 },
1143  { 19, 472, 738, 22, 1956, 11 },
1144  { 293, 500, 729, 22, 1956, 11 },
1145  { 535, 528, 720, 22, 1956, 11 },
1146  { 780, 3839, 711, 3, 2336, 16 },
1147  { 1000, 562, 702, 0, 8898, 20 },
1148  { 71, 565, 693, 0, 8898, 20 },
1149  { 348, 568, 684, 0, 8898, 20 },
1150  { 587, 571, 675, 0, 8898, 20 },
1151  { 816, 574, 666, 0, 8898, 20 },
1152  { 1036, 577, 2460, 0, 8898, 20 },
1153  { 107, 580, 2468, 0, 8898, 20 },
1154  { 608, 2343, 2488, 148, 900, 57 },
1155  { 840, 2323, 588, 148, 900, 57 },
1156  { 1060, 2303, 588, 148, 900, 57 },
1157  { 13, 2283, 588, 148, 900, 57 },
1158  { 286, 2263, 588, 148, 900, 57 },
1159  { 527, 2243, 588, 148, 900, 57 },
1160  { 772, 2225, 588, 130, 1328, 66 },
1161  { 992, 2211, 588, 116, 1776, 81 },
1162  { 63, 1588, 588, 104, 2034, 87 },
1163  { 340, 1576, 588, 104, 2034, 87 },
1164  { 579, 1564, 588, 104, 2034, 87 },
1165  { 808, 1552, 588, 104, 2034, 87 },
1166  { 1028, 1540, 588, 104, 2034, 87 },
1167  { 99, 1528, 2382, 104, 2034, 87 },
1168};
1169
1170  // HPR Register Class...
1171  static const MCPhysReg HPR[] = {
1172    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31,
1173  };
1174  // HPR Bit set.
1175  static const uint8_t HPRBits[] = {
1176    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
1177  };
1178  // SPR Register Class...
1179  static const MCPhysReg SPR[] = {
1180    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31,
1181  };
1182  // SPR Bit set.
1183  static const uint8_t SPRBits[] = {
1184    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
1185  };
1186  // GPR Register Class...
1187  static const MCPhysReg GPR[] = {
1188    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1189  };
1190  // GPR Bit set.
1191  static const uint8_t GPRBits[] = {
1192    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1193  };
1194  // GPRwithAPSR Register Class...
1195  static const MCPhysReg GPRwithAPSR[] = {
1196    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV,
1197  };
1198  // GPRwithAPSR Bit set.
1199  static const uint8_t GPRwithAPSRBits[] = {
1200    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1201  };
1202  // SPR_8 Register Class...
1203  static const MCPhysReg SPR_8[] = {
1204    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15,
1205  };
1206  // SPR_8 Bit set.
1207  static const uint8_t SPR_8Bits[] = {
1208    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1209  };
1210  // GPRnopc Register Class...
1211  static const MCPhysReg GPRnopc[] = {
1212    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1213  };
1214  // GPRnopc Bit set.
1215  static const uint8_t GPRnopcBits[] = {
1216    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1217  };
1218  // rGPR Register Class...
1219  static const MCPhysReg rGPR[] = {
1220    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR,
1221  };
1222  // rGPR Bit set.
1223  static const uint8_t rGPRBits[] = {
1224    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
1225  };
1226  // tGPRwithpc Register Class...
1227  static const MCPhysReg tGPRwithpc[] = {
1228    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC,
1229  };
1230  // tGPRwithpc Bit set.
1231  static const uint8_t tGPRwithpcBits[] = {
1232    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1233  };
1234  // hGPR Register Class...
1235  static const MCPhysReg hGPR[] = {
1236    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
1237  };
1238  // hGPR Bit set.
1239  static const uint8_t hGPRBits[] = {
1240    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1241  };
1242  // tGPR Register Class...
1243  static const MCPhysReg tGPR[] = {
1244    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7,
1245  };
1246  // tGPR Bit set.
1247  static const uint8_t tGPRBits[] = {
1248    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1249  };
1250  // GPRnopc_and_hGPR Register Class...
1251  static const MCPhysReg GPRnopc_and_hGPR[] = {
1252    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
1253  };
1254  // GPRnopc_and_hGPR Bit set.
1255  static const uint8_t GPRnopc_and_hGPRBits[] = {
1256    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1257  };
1258  // hGPR_and_rGPR Register Class...
1259  static const MCPhysReg hGPR_and_rGPR[] = {
1260    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR,
1261  };
1262  // hGPR_and_rGPR Bit set.
1263  static const uint8_t hGPR_and_rGPRBits[] = {
1264    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
1265  };
1266  // tcGPR Register Class...
1267  static const MCPhysReg tcGPR[] = {
1268    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12,
1269  };
1270  // tcGPR Bit set.
1271  static const uint8_t tcGPRBits[] = {
1272    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
1273  };
1274  // tGPR_and_tcGPR Register Class...
1275  static const MCPhysReg tGPR_and_tcGPR[] = {
1276    ARM_R0, ARM_R1, ARM_R2, ARM_R3,
1277  };
1278  // tGPR_and_tcGPR Bit set.
1279  static const uint8_t tGPR_and_tcGPRBits[] = {
1280    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1281  };
1282  // CCR Register Class...
1283  static const MCPhysReg CCR[] = {
1284    ARM_CPSR,
1285  };
1286  // CCR Bit set.
1287  static const uint8_t CCRBits[] = {
1288    0x08,
1289  };
1290  // GPRsp Register Class...
1291  static const MCPhysReg GPRsp[] = {
1292    ARM_SP,
1293  };
1294  // GPRsp Bit set.
1295  static const uint8_t GPRspBits[] = {
1296    0x00, 0x10,
1297  };
1298  // hGPR_and_tGPRwithpc Register Class...
1299  static const MCPhysReg hGPR_and_tGPRwithpc[] = {
1300    ARM_PC,
1301  };
1302  // hGPR_and_tGPRwithpc Bit set.
1303  static const uint8_t hGPR_and_tGPRwithpcBits[] = {
1304    0x00, 0x08,
1305  };
1306  // hGPR_and_tcGPR Register Class...
1307  static const MCPhysReg hGPR_and_tcGPR[] = {
1308    ARM_R12,
1309  };
1310  // hGPR_and_tcGPR Bit set.
1311  static const uint8_t hGPR_and_tcGPRBits[] = {
1312    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1313  };
1314  // DPR Register Class...
1315  static const MCPhysReg DPR[] = {
1316    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31,
1317  };
1318  // DPR Bit set.
1319  static const uint8_t DPRBits[] = {
1320    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1321  };
1322  // DPR_VFP2 Register Class...
1323  static const MCPhysReg DPR_VFP2[] = {
1324    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15,
1325  };
1326  // DPR_VFP2 Bit set.
1327  static const uint8_t DPR_VFP2Bits[] = {
1328    0x00, 0xc0, 0xff, 0x3f,
1329  };
1330  // DPR_8 Register Class...
1331  static const MCPhysReg DPR_8[] = {
1332    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7,
1333  };
1334  // DPR_8 Bit set.
1335  static const uint8_t DPR_8Bits[] = {
1336    0x00, 0xc0, 0x3f,
1337  };
1338  // GPRPair Register Class...
1339  static const MCPhysReg GPRPair[] = {
1340    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP,
1341  };
1342  // GPRPair Bit set.
1343  static const uint8_t GPRPairBits[] = {
1344    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
1345  };
1346  // GPRPair_with_gsub_1_in_rGPR Register Class...
1347  static const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
1348    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11,
1349  };
1350  // GPRPair_with_gsub_1_in_rGPR Bit set.
1351  static const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
1352    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
1353  };
1354  // GPRPair_with_gsub_0_in_tGPR Register Class...
1355  static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
1356    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7,
1357  };
1358  // GPRPair_with_gsub_0_in_tGPR Bit set.
1359  static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
1360    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1361  };
1362  // GPRPair_with_gsub_0_in_hGPR Register Class...
1363  static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
1364    ARM_R8_R9, ARM_R10_R11, ARM_R12_SP,
1365  };
1366  // GPRPair_with_gsub_0_in_hGPR Bit set.
1367  static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
1368    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2,
1369  };
1370  // GPRPair_with_gsub_0_in_tcGPR Register Class...
1371  static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
1372    ARM_R0_R1, ARM_R2_R3, ARM_R12_SP,
1373  };
1374  // GPRPair_with_gsub_0_in_tcGPR Bit set.
1375  static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
1376    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
1377  };
1378  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
1379  static const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
1380    ARM_R8_R9, ARM_R10_R11,
1381  };
1382  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
1383  static const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
1384    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
1385  };
1386  // GPRPair_with_gsub_1_in_tcGPR Register Class...
1387  static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
1388    ARM_R0_R1, ARM_R2_R3,
1389  };
1390  // GPRPair_with_gsub_1_in_tcGPR Bit set.
1391  static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
1392    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
1393  };
1394  // GPRPair_with_gsub_1_in_GPRsp Register Class...
1395  static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
1396    ARM_R12_SP,
1397  };
1398  // GPRPair_with_gsub_1_in_GPRsp Bit set.
1399  static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
1400    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
1401  };
1402  // DPairSpc Register Class...
1403  static const MCPhysReg DPairSpc[] = {
1404    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31,
1405  };
1406  // DPairSpc Bit set.
1407  static const uint8_t DPairSpcBits[] = {
1408    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
1409  };
1410  // DPairSpc_with_ssub_0 Register Class...
1411  static const MCPhysReg DPairSpc_with_ssub_0[] = {
1412    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
1413  };
1414  // DPairSpc_with_ssub_0 Bit set.
1415  static const uint8_t DPairSpc_with_ssub_0Bits[] = {
1416    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1417  };
1418  // DPairSpc_with_ssub_4 Register Class...
1419  static const MCPhysReg DPairSpc_with_ssub_4[] = {
1420    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15,
1421  };
1422  // DPairSpc_with_ssub_4 Bit set.
1423  static const uint8_t DPairSpc_with_ssub_4Bits[] = {
1424    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
1425  };
1426  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
1427  static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
1428    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9,
1429  };
1430  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
1431  static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
1432    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1433  };
1434  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
1435  static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
1436    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7,
1437  };
1438  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
1439  static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
1440    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
1441  };
1442  // DPair Register Class...
1443  static const MCPhysReg DPair[] = {
1444    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15,
1445  };
1446  // DPair Bit set.
1447  static const uint8_t DPairBits[] = {
1448    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
1449  };
1450  // DPair_with_ssub_0 Register Class...
1451  static const MCPhysReg DPair_with_ssub_0[] = {
1452    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16,
1453  };
1454  // DPair_with_ssub_0 Bit set.
1455  static const uint8_t DPair_with_ssub_0Bits[] = {
1456    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
1457  };
1458  // QPR Register Class...
1459  static const MCPhysReg QPR[] = {
1460    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15,
1461  };
1462  // QPR Bit set.
1463  static const uint8_t QPRBits[] = {
1464    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1465  };
1466  // DPair_with_ssub_2 Register Class...
1467  static const MCPhysReg DPair_with_ssub_2[] = {
1468    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7,
1469  };
1470  // DPair_with_ssub_2 Bit set.
1471  static const uint8_t DPair_with_ssub_2Bits[] = {
1472    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1473  };
1474  // DPair_with_dsub_0_in_DPR_8 Register Class...
1475  static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
1476    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8,
1477  };
1478  // DPair_with_dsub_0_in_DPR_8 Bit set.
1479  static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
1480    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1481  };
1482  // QPR_VFP2 Register Class...
1483  static const MCPhysReg QPR_VFP2[] = {
1484    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
1485  };
1486  // QPR_VFP2 Bit set.
1487  static const uint8_t QPR_VFP2Bits[] = {
1488    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
1489  };
1490  // DPair_with_dsub_1_in_DPR_8 Register Class...
1491  static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
1492    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3,
1493  };
1494  // DPair_with_dsub_1_in_DPR_8 Bit set.
1495  static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
1496    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1497  };
1498  // QPR_8 Register Class...
1499  static const MCPhysReg QPR_8[] = {
1500    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3,
1501  };
1502  // QPR_8 Bit set.
1503  static const uint8_t QPR_8Bits[] = {
1504    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1505  };
1506  // DTriple Register Class...
1507  static const MCPhysReg DTriple[] = {
1508    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31,
1509  };
1510  // DTriple Bit set.
1511  static const uint8_t DTripleBits[] = {
1512    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
1513  };
1514  // DTripleSpc Register Class...
1515  static const MCPhysReg DTripleSpc[] = {
1516    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31,
1517  };
1518  // DTripleSpc Bit set.
1519  static const uint8_t DTripleSpcBits[] = {
1520    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1521  };
1522  // DTripleSpc_with_ssub_0 Register Class...
1523  static const MCPhysReg DTripleSpc_with_ssub_0[] = {
1524    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19,
1525  };
1526  // DTripleSpc_with_ssub_0 Bit set.
1527  static const uint8_t DTripleSpc_with_ssub_0Bits[] = {
1528    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1529  };
1530  // DTriple_with_ssub_0 Register Class...
1531  static const MCPhysReg DTriple_with_ssub_0[] = {
1532    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17,
1533  };
1534  // DTriple_with_ssub_0 Bit set.
1535  static const uint8_t DTriple_with_ssub_0Bits[] = {
1536    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
1537  };
1538  // DTriple_with_qsub_0_in_QPR Register Class...
1539  static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
1540    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30,
1541  };
1542  // DTriple_with_qsub_0_in_QPR Bit set.
1543  static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
1544    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
1545  };
1546  // DTriple_with_ssub_2 Register Class...
1547  static const MCPhysReg DTriple_with_ssub_2[] = {
1548    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16,
1549  };
1550  // DTriple_with_ssub_2 Bit set.
1551  static const uint8_t DTriple_with_ssub_2Bits[] = {
1552    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
1553  };
1554  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1555  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1556    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31,
1557  };
1558  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1559  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1560    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
1561  };
1562  // DTripleSpc_with_ssub_4 Register Class...
1563  static const MCPhysReg DTripleSpc_with_ssub_4[] = {
1564    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17,
1565  };
1566  // DTripleSpc_with_ssub_4 Bit set.
1567  static const uint8_t DTripleSpc_with_ssub_4Bits[] = {
1568    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
1569  };
1570  // DTriple_with_ssub_4 Register Class...
1571  static const MCPhysReg DTriple_with_ssub_4[] = {
1572    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15,
1573  };
1574  // DTriple_with_ssub_4 Bit set.
1575  static const uint8_t DTriple_with_ssub_4Bits[] = {
1576    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
1577  };
1578  // DTripleSpc_with_ssub_8 Register Class...
1579  static const MCPhysReg DTripleSpc_with_ssub_8[] = {
1580    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15,
1581  };
1582  // DTripleSpc_with_ssub_8 Bit set.
1583  static const uint8_t DTripleSpc_with_ssub_8Bits[] = {
1584    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
1585  };
1586  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
1587  static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
1588    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11,
1589  };
1590  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
1591  static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
1592    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1593  };
1594  // DTriple_with_dsub_0_in_DPR_8 Register Class...
1595  static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
1596    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9,
1597  };
1598  // DTriple_with_dsub_0_in_DPR_8 Bit set.
1599  static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
1600    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
1601  };
1602  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
1603  static const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
1604    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16,
1605  };
1606  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
1607  static const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
1608    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1609  };
1610  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1611  static const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1612    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17,
1613  };
1614  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1615  static const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1616    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
1617  };
1618  // DTriple_with_dsub_1_in_DPR_8 Register Class...
1619  static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
1620    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8,
1621  };
1622  // DTriple_with_dsub_1_in_DPR_8 Bit set.
1623  static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
1624    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1625  };
1626  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
1627  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
1628    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15,
1629  };
1630  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
1631  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
1632    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
1633  };
1634  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
1635  static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
1636    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14,
1637  };
1638  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
1639  static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
1640    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
1641  };
1642  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
1643  static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
1644    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9,
1645  };
1646  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
1647  static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
1648    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1649  };
1650  // DTriple_with_dsub_2_in_DPR_8 Register Class...
1651  static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
1652    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7,
1653  };
1654  // DTriple_with_dsub_2_in_DPR_8 Bit set.
1655  static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
1656    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
1657  };
1658  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
1659  static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
1660    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7,
1661  };
1662  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
1663  static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
1664    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
1665  };
1666  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1667  static const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1668    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9,
1669  };
1670  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1671  static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1672    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
1673  };
1674  // DTriple_with_qsub_0_in_QPR_8 Register Class...
1675  static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
1676    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8,
1677  };
1678  // DTriple_with_qsub_0_in_QPR_8 Bit set.
1679  static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
1680    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
1681  };
1682  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
1683  static const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
1684    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6,
1685  };
1686  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
1687  static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
1688    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
1689  };
1690  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
1691  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
1692    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7,
1693  };
1694  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
1695  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
1696    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
1697  };
1698  // DQuadSpc Register Class...
1699  static const MCPhysReg DQuadSpc[] = {
1700    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31,
1701  };
1702  // DQuadSpc Bit set.
1703  static const uint8_t DQuadSpcBits[] = {
1704    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
1705  };
1706  // DQuadSpc_with_ssub_0 Register Class...
1707  static const MCPhysReg DQuadSpc_with_ssub_0[] = {
1708    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19,
1709  };
1710  // DQuadSpc_with_ssub_0 Bit set.
1711  static const uint8_t DQuadSpc_with_ssub_0Bits[] = {
1712    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1713  };
1714  // DQuadSpc_with_ssub_4 Register Class...
1715  static const MCPhysReg DQuadSpc_with_ssub_4[] = {
1716    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17,
1717  };
1718  // DQuadSpc_with_ssub_4 Bit set.
1719  static const uint8_t DQuadSpc_with_ssub_4Bits[] = {
1720    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
1721  };
1722  // DQuadSpc_with_ssub_8 Register Class...
1723  static const MCPhysReg DQuadSpc_with_ssub_8[] = {
1724    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15,
1725  };
1726  // DQuadSpc_with_ssub_8 Bit set.
1727  static const uint8_t DQuadSpc_with_ssub_8Bits[] = {
1728    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
1729  };
1730  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
1731  static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
1732    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11,
1733  };
1734  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
1735  static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
1736    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1737  };
1738  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
1739  static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
1740    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9,
1741  };
1742  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
1743  static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
1744    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1745  };
1746  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
1747  static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
1748    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7,
1749  };
1750  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
1751  static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
1752    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
1753  };
1754  // DQuad Register Class...
1755  static const MCPhysReg DQuad[] = {
1756    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15,
1757  };
1758  // DQuad Bit set.
1759  static const uint8_t DQuadBits[] = {
1760    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
1761  };
1762  // DQuad_with_ssub_0 Register Class...
1763  static const MCPhysReg DQuad_with_ssub_0[] = {
1764    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18,
1765  };
1766  // DQuad_with_ssub_0 Bit set.
1767  static const uint8_t DQuad_with_ssub_0Bits[] = {
1768    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1769  };
1770  // DQuad_with_ssub_2 Register Class...
1771  static const MCPhysReg DQuad_with_ssub_2[] = {
1772    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8,
1773  };
1774  // DQuad_with_ssub_2 Bit set.
1775  static const uint8_t DQuad_with_ssub_2Bits[] = {
1776    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
1777  };
1778  // QQPR Register Class...
1779  static const MCPhysReg QQPR[] = {
1780    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15,
1781  };
1782  // QQPR Bit set.
1783  static const uint8_t QQPRBits[] = {
1784    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
1785  };
1786  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1787  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1788    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30,
1789  };
1790  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1791  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1792    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
1793  };
1794  // DQuad_with_ssub_4 Register Class...
1795  static const MCPhysReg DQuad_with_ssub_4[] = {
1796    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16,
1797  };
1798  // DQuad_with_ssub_4 Bit set.
1799  static const uint8_t DQuad_with_ssub_4Bits[] = {
1800    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
1801  };
1802  // DQuad_with_ssub_6 Register Class...
1803  static const MCPhysReg DQuad_with_ssub_6[] = {
1804    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7,
1805  };
1806  // DQuad_with_ssub_6 Bit set.
1807  static const uint8_t DQuad_with_ssub_6Bits[] = {
1808    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
1809  };
1810  // DQuad_with_dsub_0_in_DPR_8 Register Class...
1811  static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
1812    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10,
1813  };
1814  // DQuad_with_dsub_0_in_DPR_8 Bit set.
1815  static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
1816    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
1817  };
1818  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
1819  static const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
1820    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8,
1821  };
1822  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
1823  static const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
1824    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
1825  };
1826  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1827  static const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1828    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18,
1829  };
1830  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1831  static const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1832    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1833  };
1834  // DQuad_with_dsub_1_in_DPR_8 Register Class...
1835  static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
1836    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4,
1837  };
1838  // DQuad_with_dsub_1_in_DPR_8 Bit set.
1839  static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
1840    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
1841  };
1842  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
1843  static const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
1844    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7,
1845  };
1846  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
1847  static const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
1848    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
1849  };
1850  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
1851  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
1852    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16,
1853  };
1854  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
1855  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
1856    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
1857  };
1858  // DQuad_with_dsub_2_in_DPR_8 Register Class...
1859  static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
1860    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8,
1861  };
1862  // DQuad_with_dsub_2_in_DPR_8 Bit set.
1863  static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
1864    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
1865  };
1866  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1867  static const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1868    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14,
1869  };
1870  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1871  static const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1872    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
1873  };
1874  // DQuad_with_dsub_3_in_DPR_8 Register Class...
1875  static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
1876    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3,
1877  };
1878  // DQuad_with_dsub_3_in_DPR_8 Bit set.
1879  static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
1880    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
1881  };
1882  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1883  static const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1884    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10,
1885  };
1886  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1887  static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1888    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
1889  };
1890  // DQuad_with_qsub_0_in_QPR_8 Register Class...
1891  static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
1892    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4,
1893  };
1894  // DQuad_with_qsub_0_in_QPR_8 Bit set.
1895  static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
1896    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
1897  };
1898  // DQuad_with_qsub_1_in_QPR_8 Register Class...
1899  static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
1900    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3,
1901  };
1902  // DQuad_with_qsub_1_in_QPR_8 Bit set.
1903  static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
1904    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
1905  };
1906  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
1907  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
1908    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8,
1909  };
1910  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
1911  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
1912    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
1913  };
1914  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
1915  static const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
1916    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6,
1917  };
1918  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
1919  static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
1920    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
1921  };
1922  // QQQQPR Register Class...
1923  static const MCPhysReg QQQQPR[] = {
1924    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15,
1925  };
1926  // QQQQPR Bit set.
1927  static const uint8_t QQQQPRBits[] = {
1928    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
1929  };
1930  // QQQQPR_with_ssub_0 Register Class...
1931  static const MCPhysReg QQQQPR_with_ssub_0[] = {
1932    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10,
1933  };
1934  // QQQQPR_with_ssub_0 Bit set.
1935  static const uint8_t QQQQPR_with_ssub_0Bits[] = {
1936    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
1937  };
1938  // QQQQPR_with_ssub_4 Register Class...
1939  static const MCPhysReg QQQQPR_with_ssub_4[] = {
1940    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9,
1941  };
1942  // QQQQPR_with_ssub_4 Bit set.
1943  static const uint8_t QQQQPR_with_ssub_4Bits[] = {
1944    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1945  };
1946  // QQQQPR_with_ssub_8 Register Class...
1947  static const MCPhysReg QQQQPR_with_ssub_8[] = {
1948    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8,
1949  };
1950  // QQQQPR_with_ssub_8 Bit set.
1951  static const uint8_t QQQQPR_with_ssub_8Bits[] = {
1952    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
1953  };
1954  // QQQQPR_with_ssub_12 Register Class...
1955  static const MCPhysReg QQQQPR_with_ssub_12[] = {
1956    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7,
1957  };
1958  // QQQQPR_with_ssub_12 Bit set.
1959  static const uint8_t QQQQPR_with_ssub_12Bits[] = {
1960    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
1961  };
1962  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
1963  static const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
1964    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6,
1965  };
1966  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
1967  static const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
1968    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
1969  };
1970  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
1971  static const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
1972    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5,
1973  };
1974  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
1975  static const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
1976    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
1977  };
1978  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
1979  static const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
1980    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4,
1981  };
1982  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
1983  static const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
1984    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
1985  };
1986  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
1987  static const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
1988    ARM_Q0_Q1_Q2_Q3,
1989  };
1990  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
1991  static const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
1992    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
1993  };
1994
1995
1996static const MCRegisterClass ARMMCRegisterClasses[] = {
1997  { HPR, HPRBits, sizeof(HPRBits) },
1998  { SPR, SPRBits, sizeof(SPRBits) },
1999  { GPR, GPRBits, sizeof(GPRBits) },
2000  { GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits) },
2001  { SPR_8, SPR_8Bits, sizeof(SPR_8Bits) },
2002  { GPRnopc, GPRnopcBits, sizeof(GPRnopcBits) },
2003  { rGPR, rGPRBits, sizeof(rGPRBits) },
2004  { tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits) },
2005  { hGPR, hGPRBits, sizeof(hGPRBits) },
2006  { tGPR, tGPRBits, sizeof(tGPRBits) },
2007  { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, sizeof(GPRnopc_and_hGPRBits) },
2008  { hGPR_and_rGPR, hGPR_and_rGPRBits, sizeof(hGPR_and_rGPRBits) },
2009  { tcGPR, tcGPRBits, sizeof(tcGPRBits) },
2010  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, sizeof(tGPR_and_tcGPRBits) },
2011  { CCR, CCRBits, sizeof(CCRBits) },
2012  { GPRsp, GPRspBits, sizeof(GPRspBits) },
2013  { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, sizeof(hGPR_and_tGPRwithpcBits) },
2014  { hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits) },
2015  { DPR, DPRBits, sizeof(DPRBits) },
2016  { DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits) },
2017  { DPR_8, DPR_8Bits, sizeof(DPR_8Bits) },
2018  { GPRPair, GPRPairBits, sizeof(GPRPairBits) },
2019  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, sizeof(GPRPair_with_gsub_1_in_rGPRBits) },
2020  { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, sizeof(GPRPair_with_gsub_0_in_tGPRBits) },
2021  { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPair_with_gsub_0_in_hGPRBits) },
2022  { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, sizeof(GPRPair_with_gsub_0_in_tcGPRBits) },
2023  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits) },
2024  { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, sizeof(GPRPair_with_gsub_1_in_tcGPRBits) },
2025  { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, sizeof(GPRPair_with_gsub_1_in_GPRspBits) },
2026  { DPairSpc, DPairSpcBits, sizeof(DPairSpcBits) },
2027  { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, sizeof(DPairSpc_with_ssub_0Bits) },
2028  { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, sizeof(DPairSpc_with_ssub_4Bits) },
2029  { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits) },
2030  { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits) },
2031  { DPair, DPairBits, sizeof(DPairBits) },
2032  { DPair_with_ssub_0, DPair_with_ssub_0Bits, sizeof(DPair_with_ssub_0Bits) },
2033  { QPR, QPRBits, sizeof(QPRBits) },
2034  { DPair_with_ssub_2, DPair_with_ssub_2Bits, sizeof(DPair_with_ssub_2Bits) },
2035  { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, sizeof(DPair_with_dsub_0_in_DPR_8Bits) },
2036  { QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits) },
2037  { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, sizeof(DPair_with_dsub_1_in_DPR_8Bits) },
2038  { QPR_8, QPR_8Bits, sizeof(QPR_8Bits) },
2039  { DTriple, DTripleBits, sizeof(DTripleBits) },
2040  { DTripleSpc, DTripleSpcBits, sizeof(DTripleSpcBits) },
2041  { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, sizeof(DTripleSpc_with_ssub_0Bits) },
2042  { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, sizeof(DTriple_with_ssub_0Bits) },
2043  { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_qsub_0_in_QPRBits) },
2044  { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, sizeof(DTriple_with_ssub_2Bits) },
2045  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2046  { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, sizeof(DTripleSpc_with_ssub_4Bits) },
2047  { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, sizeof(DTriple_with_ssub_4Bits) },
2048  { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, sizeof(DTripleSpc_with_ssub_8Bits) },
2049  { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits) },
2050  { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, sizeof(DTriple_with_dsub_0_in_DPR_8Bits) },
2051  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits) },
2052  { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2053  { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, sizeof(DTriple_with_dsub_1_in_DPR_8Bits) },
2054  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) },
2055  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits) },
2056  { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits) },
2057  { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, sizeof(DTriple_with_dsub_2_in_DPR_8Bits) },
2058  { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits) },
2059  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2060  { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, sizeof(DTriple_with_qsub_0_in_QPR_8Bits) },
2061  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits) },
2062  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) },
2063  { DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits) },
2064  { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, sizeof(DQuadSpc_with_ssub_0Bits) },
2065  { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, sizeof(DQuadSpc_with_ssub_4Bits) },
2066  { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, sizeof(DQuadSpc_with_ssub_8Bits) },
2067  { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits) },
2068  { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits) },
2069  { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits) },
2070  { DQuad, DQuadBits, sizeof(DQuadBits) },
2071  { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, sizeof(DQuad_with_ssub_0Bits) },
2072  { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, sizeof(DQuad_with_ssub_2Bits) },
2073  { QQPR, QQPRBits, sizeof(QQPRBits) },
2074  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2075  { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, sizeof(DQuad_with_ssub_4Bits) },
2076  { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, sizeof(DQuad_with_ssub_6Bits) },
2077  { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, sizeof(DQuad_with_dsub_0_in_DPR_8Bits) },
2078  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits) },
2079  { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2080  { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, sizeof(DQuad_with_dsub_1_in_DPR_8Bits) },
2081  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits) },
2082  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) },
2083  { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, sizeof(DQuad_with_dsub_2_in_DPR_8Bits) },
2084  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2085  { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, sizeof(DQuad_with_dsub_3_in_DPR_8Bits) },
2086  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2087  { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, sizeof(DQuad_with_qsub_0_in_QPR_8Bits) },
2088  { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, sizeof(DQuad_with_qsub_1_in_QPR_8Bits) },
2089  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) },
2090  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
2091  { QQQQPR, QQQQPRBits, sizeof(QQQQPRBits) },
2092  { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, sizeof(QQQQPR_with_ssub_0Bits) },
2093  { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, sizeof(QQQQPR_with_ssub_4Bits) },
2094  { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, sizeof(QQQQPR_with_ssub_8Bits) },
2095  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, sizeof(QQQQPR_with_ssub_12Bits) },
2096  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits) },
2097  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits) },
2098  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits) },
2099  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits) },
2100};
2101
2102#endif // GET_REGINFO_MC_DESC
2103