1//===-- X86InstrVMX.td - VMX Instruction Set Extension -----*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the instructions that make up the Intel VMX instruction
11// set.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// VMX instructions
17
18let SchedRW = [WriteSystem] in {
19// 66 0F 38 80
20def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
21               "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22               Requires<[Not64BitMode]>;
23def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
24               "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
25               Requires<[In64BitMode]>;
26
27// 66 0F 38 81
28def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
29                "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
30                Requires<[Not64BitMode]>;
31def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
32                "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
33                Requires<[In64BitMode]>;
34
35// 0F 01 C1
36def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
37def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
38  "vmclear\t$vmcs", []>, PD;
39
40// OF 01 D4
41def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
42
43// 0F 01 C2
44def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
45
46// 0F 01 C3
47def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
48def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
49  "vmptrld\t$vmcs", []>, PS;
50def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs),
51  "vmptrst\t$vmcs", []>, PS;
52def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
53  "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
54  NotMemoryFoldable;
55def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
56  "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
57  NotMemoryFoldable;
58
59let mayStore = 1 in {
60def VMREAD64mr : I<0x78, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
61  "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
62  NotMemoryFoldable;
63def VMREAD32mr : I<0x78, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
64  "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
65  NotMemoryFoldable;
66} // mayStore
67
68def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
69  "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
70  NotMemoryFoldable;
71def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
72  "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
73  NotMemoryFoldable;
74
75let mayLoad = 1 in {
76def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
77  "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
78  NotMemoryFoldable;
79def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
80  "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>,
81  NotMemoryFoldable;
82} // mayLoad
83
84// 0F 01 C4
85def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
86def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
87  "vmxon\t$vmxon", []>, XS;
88} // SchedRW
89