1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
5 * Original from Linux kernel 3.0.1
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #ifndef ATH9K_H
21 #define ATH9K_H
22
23 FILE_LICENCE ( BSD2 );
24
25 #include "common.h"
26
27 /*
28 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
29 * should rely on this file or its contents.
30 */
31
32 struct ath_node;
33 struct ath_softc;
34
35 /* Macro to expand scalars to 64-bit objects */
36
37 #define ito64(x) (sizeof(x) == 1) ? \
38 (((unsigned long long int)(x)) & (0xff)) : \
39 (sizeof(x) == 2) ? \
40 (((unsigned long long int)(x)) & 0xffff) : \
41 ((sizeof(x) == 4) ? \
42 (((unsigned long long int)(x)) & 0xffffffff) : \
43 (unsigned long long int)(x))
44
45 /* increment with wrap-around */
46 #define INCR(_l, _sz) do { \
47 (_l)++; \
48 (_l) &= ((_sz) - 1); \
49 } while (0)
50
51 /* decrement with wrap-around */
52 #define DECR(_l, _sz) do { \
53 (_l)--; \
54 (_l) &= ((_sz) - 1); \
55 } while (0)
56
57 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
58
59 #define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
61
62 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
63
64 struct ath_config {
65 u16 txpowlimit;
66 u8 cabqReadytime;
67 };
68
69 /*************************/
70 /* Descriptor Management */
71 /*************************/
72
73 #define ATH_TXBUF_RESET(_bf) do { \
74 (_bf)->bf_stale = 0; \
75 (_bf)->bf_lastbf = NULL; \
76 (_bf)->bf_next = NULL; \
77 memset(&((_bf)->bf_state), 0, \
78 sizeof(struct ath_buf_state)); \
79 } while (0)
80
81 #define ATH_RXBUF_RESET(_bf) do { \
82 (_bf)->bf_stale = 0; \
83 } while (0)
84
85 /**
86 * enum buffer_type - Buffer type flags
87 *
88 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
89 * @BUF_AGGR: Indicates whether the buffer can be aggregated
90 * (used in aggregation scheduling)
91 * @BUF_XRETRY: To denote excessive retries of the buffer
92 */
93 enum buffer_type {
94 BUF_AMPDU = BIT(0),
95 BUF_AGGR = BIT(1),
96 BUF_XRETRY = BIT(2),
97 };
98
99 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
100 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
101 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
102
103 #define ATH_TXSTATUS_RING_SIZE 64
104
105 struct ath_descdma {
106 void *dd_desc;
107 u32 dd_desc_paddr;
108 u32 dd_desc_len;
109 struct ath_buf *dd_bufptr;
110 };
111
112 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
113 struct list_head *head, const char *name,
114 int nbuf, int ndesc, int is_tx);
115 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
116 struct list_head *head);
117
118 /***********/
119 /* RX / TX */
120 /***********/
121
122 #define ATH_RXBUF 16
123 #define ATH_TXBUF 16
124 #define ATH_TXBUF_RESERVE 5
125 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
126 #define ATH_TXMAXTRY 13
127
128 #define TID_TO_WME_AC(_tid) \
129 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
130 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
131 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
132 WME_AC_VO)
133
134 #define ATH_AGGR_DELIM_SZ 4
135 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
136 /* number of delimiters for encryption padding */
137 #define ATH_AGGR_ENCRYPTDELIM 10
138 /* minimum h/w qdepth to be sustained to maximize aggregation */
139 #define ATH_AGGR_MIN_QDEPTH 2
140 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
141
142 #define FCS_LEN 4
143 #define IEEE80211_SEQ_SEQ_SHIFT 4
144 #define IEEE80211_SEQ_MAX 4096
145 #define IEEE80211_WEP_IVLEN 3
146 #define IEEE80211_WEP_KIDLEN 1
147 #define IEEE80211_WEP_CRCLEN 4
148 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
149 (IEEE80211_WEP_IVLEN + \
150 IEEE80211_WEP_KIDLEN + \
151 IEEE80211_WEP_CRCLEN))
152
153 /* return whether a bit at index _n in bitmap _bm is set
154 * _sz is the size of the bitmap */
155 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
156 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
157
158 /* return block-ack bitmap index given sequence and starting sequence */
159 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
160
161 /* returns delimiter padding required given the packet length */
162 #define ATH_AGGR_GET_NDELIM(_len) \
163 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
164 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
165
166 #define BAW_WITHIN(_start, _bawsz, _seqno) \
167 ((((_seqno) - (_start)) & 4095) < (_bawsz))
168
169 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
170
171 #define ATH_TX_COMPLETE_POLL_INT 1000
172
173 enum ATH_AGGR_STATUS {
174 ATH_AGGR_DONE,
175 ATH_AGGR_BAW_CLOSED,
176 ATH_AGGR_LIMITED,
177 };
178
179 #define ATH_TXFIFO_DEPTH 8
180 struct ath_txq {
181 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
182 u32 axq_qnum; /* ath9k hardware queue number */
183 u32 *axq_link;
184 struct list_head axq_q;
185 u32 axq_depth;
186 u32 axq_ampdu_depth;
187 int stopped;
188 int axq_tx_inprogress;
189 struct list_head axq_acq;
190 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
191 struct list_head txq_fifo_pending;
192 u8 txq_headidx;
193 u8 txq_tailidx;
194 int pending_frames;
195 };
196
197 struct ath_atx_ac {
198 struct ath_txq *txq;
199 int sched;
200 struct list_head list;
201 struct list_head tid_q;
202 int clear_ps_filter;
203 };
204
205 struct ath_frame_info {
206 int framelen;
207 u32 keyix;
208 enum ath9k_key_type keytype;
209 u8 retries;
210 u16 seqno;
211 };
212
213 struct ath_buf_state {
214 u8 bf_type;
215 u8 bfs_paprd;
216 unsigned long bfs_paprd_timestamp;
217 };
218
219 struct ath_buf {
220 struct list_head list;
221 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
222 an aggregate) */
223 struct ath_buf *bf_next; /* next subframe in the aggregate */
224 struct io_buffer *bf_mpdu; /* enclosing frame structure */
225 void *bf_desc; /* virtual addr of desc */
226 u32 bf_daddr; /* physical addr of desc */
227 u32 bf_buf_addr; /* physical addr of data buffer, for DMA */
228 int bf_stale;
229 u16 bf_flags;
230 struct ath_buf_state bf_state;
231 };
232
233 struct ath_atx_tid {
234 struct list_head list;
235 struct list_head buf_q;
236 struct ath_node *an;
237 struct ath_atx_ac *ac;
238 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
239 u16 seq_start;
240 u16 seq_next;
241 u16 baw_size;
242 int tidno;
243 int baw_head; /* first un-acked tx buffer */
244 int baw_tail; /* next unused tx buffer slot */
245 int sched;
246 int paused;
247 u8 state;
248 };
249
250 struct ath_node {
251 struct ath_atx_tid tid[WME_NUM_TID];
252 struct ath_atx_ac ac[WME_NUM_AC];
253 int ps_key;
254
255 u16 maxampdu;
256 u8 mpdudensity;
257
258 int sleeping;
259 };
260
261 #define AGGR_CLEANUP BIT(1)
262 #define AGGR_ADDBA_COMPLETE BIT(2)
263 #define AGGR_ADDBA_PROGRESS BIT(3)
264
265 struct ath_tx_control {
266 struct ath_txq *txq;
267 struct ath_node *an;
268 int if_id;
269 u8 paprd;
270 };
271
272 #define ATH_TX_ERROR 0x01
273 #define ATH_TX_XRETRY 0x02
274 #define ATH_TX_BAR 0x04
275
276 /**
277 * @txq_map: Index is mac80211 queue number. This is
278 * not necessarily the same as the hardware queue number
279 * (axq_qnum).
280 */
281 struct ath_tx {
282 u16 seq_no;
283 u32 txqsetup;
284 struct list_head txbuf;
285 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
286 struct ath_descdma txdma;
287 struct ath_txq *txq_map[WME_NUM_AC];
288 };
289
290 struct ath_rx_edma {
291 struct list_head rx_fifo;
292 struct list_head rx_buffers;
293 u32 rx_fifo_hwsize;
294 };
295
296 struct ath_rx {
297 u8 defant;
298 u8 rxotherant;
299 u32 *rxlink;
300 unsigned int rxfilter;
301 struct list_head rxbuf;
302 struct ath_descdma rxdma;
303 struct ath_buf *rx_bufptr;
304 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
305
306 struct io_buffer *frag;
307 };
308
309 int ath_startrecv(struct ath_softc *sc);
310 int ath_stoprecv(struct ath_softc *sc);
311 void ath_flushrecv(struct ath_softc *sc);
312 u32 ath_calcrxfilter(struct ath_softc *sc);
313 int ath_rx_init(struct ath_softc *sc, int nbufs);
314 void ath_rx_cleanup(struct ath_softc *sc);
315 int ath_rx_tasklet(struct ath_softc *sc, int flush, int hp);
316 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
317 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
318 int ath_drain_all_txq(struct ath_softc *sc, int retry_tx);
319 void ath_draintxq(struct ath_softc *sc,
320 struct ath_txq *txq, int retry_tx);
321 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
322 int ath_tx_init(struct ath_softc *sc, int nbufs);
323 void ath_tx_cleanup(struct ath_softc *sc);
324 int ath_txq_update(struct ath_softc *sc, int qnum,
325 struct ath9k_tx_queue_info *q);
326 int ath_tx_start(struct net80211_device *dev, struct io_buffer *iob,
327 struct ath_tx_control *txctl);
328 void ath_tx_tasklet(struct ath_softc *sc);
329
330 /*******/
331 /* ANI */
332 /*******/
333
334 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
335 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
336 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
337 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
338 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
339 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
340 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
341
342 void ath_hw_pll_work(struct ath_softc *sc);
343 void ath_ani_calibrate(struct ath_softc *sc);
344
345 /********************/
346 /* Main driver core */
347 /********************/
348
349 /*
350 * Default cache line size, in bytes.
351 * Used when PCI device not fully initialized by bootrom/BIOS
352 */
353 #define DEFAULT_CACHELINE 32
354 #define ATH_REGCLASSIDS_MAX 10
355 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
356 #define ATH_MAX_SW_RETRIES 10
357 #define ATH_CHAN_MAX 255
358
359 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
360 #define ATH_RATE_DUMMY_MARKER 0
361
362 #define SC_OP_INVALID BIT(0)
363 #define SC_OP_BEACONS BIT(1)
364 #define SC_OP_RXAGGR BIT(2)
365 #define SC_OP_TXAGGR BIT(3)
366 #define SC_OP_OFFCHANNEL BIT(4)
367 #define SC_OP_PREAMBLE_SHORT BIT(5)
368 #define SC_OP_PROTECT_ENABLE BIT(6)
369 #define SC_OP_RXFLUSH BIT(7)
370 #define SC_OP_LED_ASSOCIATED BIT(8)
371 #define SC_OP_LED_ON BIT(9)
372 #define SC_OP_TSF_RESET BIT(11)
373 #define SC_OP_BT_PRIORITY_DETECTED BIT(12)
374 #define SC_OP_BT_SCAN BIT(13)
375 #define SC_OP_ANI_RUN BIT(14)
376 #define SC_OP_ENABLE_APM BIT(15)
377 #define SC_OP_PRIM_STA_VIF BIT(16)
378
379 /* Powersave flags */
380 #define PS_WAIT_FOR_BEACON BIT(0)
381 #define PS_WAIT_FOR_CAB BIT(1)
382 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
383 #define PS_WAIT_FOR_TX_ACK BIT(3)
384 #define PS_BEACON_SYNC BIT(4)
385 #define PS_TSFOOR_SYNC BIT(5)
386
387 struct ath_rate_table;
388
389 struct ath9k_legacy_rate {
390 u16 bitrate;
391 u32 flags;
392 u16 hw_value;
393 u16 hw_value_short;
394 };
395
396 enum ath9k_rate_control_flags {
397 IEEE80211_TX_RC_USE_RTS_CTS = BIT(0),
398 IEEE80211_TX_RC_USE_CTS_PROTECT = BIT(1),
399 IEEE80211_TX_RC_USE_SHORT_PREAMBLE = BIT(2),
400
401 /* rate index is an MCS rate number instead of an index */
402 IEEE80211_TX_RC_MCS = BIT(3),
403 IEEE80211_TX_RC_GREEN_FIELD = BIT(4),
404 IEEE80211_TX_RC_40_MHZ_WIDTH = BIT(5),
405 IEEE80211_TX_RC_DUP_DATA = BIT(6),
406 IEEE80211_TX_RC_SHORT_GI = BIT(7),
407 };
408
409 struct survey_info {
410 struct net80211_channel *channel;
411 u64 channel_time;
412 u64 channel_time_busy;
413 u64 channel_time_ext_busy;
414 u64 channel_time_rx;
415 u64 channel_time_tx;
416 u32 filled;
417 s8 noise;
418 };
419
420 enum survey_info_flags {
421 SURVEY_INFO_NOISE_DBM = 1<<0,
422 SURVEY_INFO_IN_USE = 1<<1,
423 SURVEY_INFO_CHANNEL_TIME = 1<<2,
424 SURVEY_INFO_CHANNEL_TIME_BUSY = 1<<3,
425 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY = 1<<4,
426 SURVEY_INFO_CHANNEL_TIME_RX = 1<<5,
427 SURVEY_INFO_CHANNEL_TIME_TX = 1<<6,
428 };
429
430 struct ath9k_vif_iter_data {
431 const u8 *hw_macaddr; /* phy's hardware address, set
432 * before starting iteration for
433 * valid bssid mask.
434 */
435 u8 mask[ETH_ALEN]; /* bssid mask */
436 int naps; /* number of AP vifs */
437 int nmeshes; /* number of mesh vifs */
438 int nstations; /* number of station vifs */
439 int nwds; /* number of nwd vifs */
440 int nadhocs; /* number of adhoc vifs */
441 int nothers; /* number of vifs not specified above. */
442 };
443
444 struct ath_softc {
445 struct net80211_device *dev;
446 struct pci_device *pdev;
447
448 int chan_idx;
449 int chan_is_ht;
450 struct survey_info *cur_survey;
451 struct survey_info survey[ATH9K_NUM_CHANNELS];
452
453 void (*intr_tq)(struct ath_softc *sc);
454 struct ath_hw *sc_ah;
455 void *mem;
456 int irq;
457
458 void (*paprd_work)(struct ath_softc *sc);
459 void (*hw_check_work)(struct ath_softc *sc);
460 void (*paprd_complete)(struct ath_softc *sc);
461
462 unsigned int hw_busy_count;
463
464 u32 intrstatus;
465 u32 sc_flags; /* SC_OP_* */
466 u16 ps_flags; /* PS_* */
467 u16 curtxpow;
468 int ps_enabled;
469 int ps_idle;
470 short nbcnvifs;
471 short nvifs;
472 unsigned long ps_usecount;
473
474 struct ath_config config;
475 struct ath_rx rx;
476 struct ath_tx tx;
477 struct net80211_hw_info *hwinfo;
478 struct ath9k_legacy_rate rates[NET80211_MAX_RATES];
479 int hw_rix;
480
481 struct ath9k_hw_cal_data caldata;
482 int last_rssi;
483
484 void (*tx_complete_work)(struct ath_softc *sc);
485 unsigned long tx_complete_work_timer;
486 void (*hw_pll_work)(struct ath_softc *sc);
487 unsigned long hw_pll_work_timer;
488
489 struct ath_descdma txsdma;
490 };
491
492 void ath9k_tasklet(struct ath_softc *sc);
493 int ath_reset(struct ath_softc *sc, int retry_tx);
494
ath_read_cachesize(struct ath_common * common,int * csz)495 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
496 {
497 common->bus_ops->read_cachesize(common, csz);
498 }
499
500 extern struct net80211_device_operations ath9k_ops;
501 extern int ath9k_modparam_nohwcrypt;
502 extern int is_ath9k_unloaded;
503
504 void ath_isr(struct net80211_device *dev);
505 void ath9k_init_crypto(struct ath_softc *sc);
506 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
507 const struct ath_bus_ops *bus_ops);
508 void ath9k_deinit_device(struct ath_softc *sc);
509 void ath9k_set_hw_capab(struct ath_softc *sc, struct net80211_device *dev);
510 int ath_set_channel(struct ath_softc *sc, struct net80211_device *dev,
511 struct ath9k_channel *hchan);
512
513 void ath_radio_enable(struct ath_softc *sc, struct net80211_device *dev);
514 void ath_radio_disable(struct ath_softc *sc, struct net80211_device *dev);
515 int ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
516 int ath9k_uses_beacons(int type);
517
518 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
519
520 void ath_start_rfkill_poll(struct ath_softc *sc);
521 extern void ath9k_rfkill_poll_state(struct net80211_device *dev);
522
523 #endif /* ATH9K_H */
524