1 #ifndef STD_TCG_H 2 #define STD_TCG_H 3 4 #include "types.h" 5 6 #define SHA1_BUFSIZE 20 7 #define SHA256_BUFSIZE 32 8 #define SHA384_BUFSIZE 48 9 #define SHA512_BUFSIZE 64 10 #define SM3_256_BUFSIZE 32 11 #define SHA3_256_BUFSIZE 32 12 #define SHA3_384_BUFSIZE 48 13 #define SHA3_512_BUFSIZE 64 14 15 16 /**************************************************************** 17 * 16bit BIOS interface 18 ****************************************************************/ 19 20 /* Define for section 12.3 */ 21 #define TCG_PC_OK 0x0 22 #define TCG_PC_TPMERROR 0x1 23 #define TCG_PC_LOGOVERFLOW 0x2 24 #define TCG_PC_UNSUPPORTED 0x3 25 26 #define TPM_ALG_SHA 0x4 27 28 #define TCG_MAGIC 0x41504354L 29 #define TCG_VERSION_MAJOR 1 30 #define TCG_VERSION_MINOR 2 31 32 #define TPM_OK 0x0 33 #define TPM_RET_BASE 0x1 34 #define TCG_GENERAL_ERROR (TPM_RET_BASE + 0x0) 35 #define TCG_TPM_IS_LOCKED (TPM_RET_BASE + 0x1) 36 #define TCG_NO_RESPONSE (TPM_RET_BASE + 0x2) 37 #define TCG_INVALID_RESPONSE (TPM_RET_BASE + 0x3) 38 #define TCG_INVALID_ACCESS_REQUEST (TPM_RET_BASE + 0x4) 39 #define TCG_FIRMWARE_ERROR (TPM_RET_BASE + 0x5) 40 #define TCG_INTEGRITY_CHECK_FAILED (TPM_RET_BASE + 0x6) 41 #define TCG_INVALID_DEVICE_ID (TPM_RET_BASE + 0x7) 42 #define TCG_INVALID_VENDOR_ID (TPM_RET_BASE + 0x8) 43 #define TCG_UNABLE_TO_OPEN (TPM_RET_BASE + 0x9) 44 #define TCG_UNABLE_TO_CLOSE (TPM_RET_BASE + 0xa) 45 #define TCG_RESPONSE_TIMEOUT (TPM_RET_BASE + 0xb) 46 #define TCG_INVALID_COM_REQUEST (TPM_RET_BASE + 0xc) 47 #define TCG_INVALID_ADR_REQUEST (TPM_RET_BASE + 0xd) 48 #define TCG_WRITE_BYTE_ERROR (TPM_RET_BASE + 0xe) 49 #define TCG_READ_BYTE_ERROR (TPM_RET_BASE + 0xf) 50 #define TCG_BLOCK_WRITE_TIMEOUT (TPM_RET_BASE + 0x10) 51 #define TCG_CHAR_WRITE_TIMEOUT (TPM_RET_BASE + 0x11) 52 #define TCG_CHAR_READ_TIMEOUT (TPM_RET_BASE + 0x12) 53 #define TCG_BLOCK_READ_TIMEOUT (TPM_RET_BASE + 0x13) 54 #define TCG_TRANSFER_ABORT (TPM_RET_BASE + 0x14) 55 #define TCG_INVALID_DRV_FUNCTION (TPM_RET_BASE + 0x15) 56 #define TCG_OUTPUT_BUFFER_TOO_SHORT (TPM_RET_BASE + 0x16) 57 #define TCG_FATAL_COM_ERROR (TPM_RET_BASE + 0x17) 58 #define TCG_INVALID_INPUT_PARA (TPM_RET_BASE + 0x18) 59 #define TCG_TCG_COMMAND_ERROR (TPM_RET_BASE + 0x19) 60 #define TCG_INTERFACE_SHUTDOWN (TPM_RET_BASE + 0x20) 61 //define TCG_PC_UNSUPPORTED (TPM_RET_BASE + 0x21) 62 #define TCG_PC_TPM_NOT_PRESENT (TPM_RET_BASE + 0x22) 63 #define TCG_PC_TPM_DEACTIVATED (TPM_RET_BASE + 0x23) 64 65 /* interrupt identifiers (al register) */ 66 enum irq_ids { 67 TCG_StatusCheck = 0, 68 TCG_HashLogExtendEvent = 1, 69 TCG_PassThroughToTPM = 2, 70 TCG_ShutdownPreBootInterface = 3, 71 TCG_HashLogEvent = 4, 72 TCG_HashAll = 5, 73 TCG_TSS = 6, 74 TCG_CompactHashLogExtendEvent = 7, 75 }; 76 77 /* Input and Output blocks for the TCG BIOS commands */ 78 79 struct hleei_short 80 { 81 u16 ipblength; 82 u16 reserved; 83 const void *hashdataptr; 84 u32 hashdatalen; 85 u32 pcrindex; 86 const void *logdataptr; 87 u32 logdatalen; 88 } PACKED; 89 90 struct hleei_long 91 { 92 u16 ipblength; 93 u16 reserved; 94 void *hashdataptr; 95 u32 hashdatalen; 96 u32 pcrindex; 97 u32 reserved2; 98 void *logdataptr; 99 u32 logdatalen; 100 } PACKED; 101 102 struct hleeo 103 { 104 u16 opblength; 105 u16 reserved; 106 u32 eventnumber; 107 u8 digest[SHA1_BUFSIZE]; 108 } PACKED; 109 110 struct pttti 111 { 112 u16 ipblength; 113 u16 reserved; 114 u16 opblength; 115 u16 reserved2; 116 u8 tpmopin[0]; 117 } PACKED; 118 119 struct pttto 120 { 121 u16 opblength; 122 u16 reserved; 123 u8 tpmopout[0]; 124 }; 125 126 struct hlei 127 { 128 u16 ipblength; 129 u16 reserved; 130 const void *hashdataptr; 131 u32 hashdatalen; 132 u32 pcrindex; 133 u32 logeventtype; 134 const void *logdataptr; 135 u32 logdatalen; 136 } PACKED; 137 138 struct hleo 139 { 140 u16 opblength; 141 u16 reserved; 142 u32 eventnumber; 143 } PACKED; 144 145 struct hai 146 { 147 u16 ipblength; 148 u16 reserved; 149 const void *hashdataptr; 150 u32 hashdatalen; 151 u32 algorithmid; 152 } PACKED; 153 154 struct ti 155 { 156 u16 ipblength; 157 u16 reserved; 158 u16 opblength; 159 u16 reserved2; 160 u8 tssoperandin[0]; 161 } PACKED; 162 163 struct to 164 { 165 u16 opblength; 166 u16 reserved; 167 u8 tssoperandout[0]; 168 } PACKED; 169 170 struct pcpes 171 { 172 u32 pcrindex; 173 u32 eventtype; 174 u8 digest[SHA1_BUFSIZE]; 175 u32 eventdatasize; 176 u8 event[0]; 177 } PACKED; 178 179 180 /**************************************************************** 181 * TPM v1.2 hardware commands 182 ****************************************************************/ 183 184 #define TPM_ORD_SelfTestFull 0x00000050 185 #define TPM_ORD_ForceClear 0x0000005d 186 #define TPM_ORD_GetCapability 0x00000065 187 #define TPM_ORD_PhysicalEnable 0x0000006f 188 #define TPM_ORD_PhysicalDisable 0x00000070 189 #define TPM_ORD_SetOwnerInstall 0x00000071 190 #define TPM_ORD_PhysicalSetDeactivated 0x00000072 191 #define TPM_ORD_SetTempDeactivated 0x00000073 192 #define TPM_ORD_Startup 0x00000099 193 #define TPM_ORD_PhysicalPresence 0x4000000a 194 #define TPM_ORD_Extend 0x00000014 195 #define TSC_ORD_ResetEstablishmentBit 0x4000000b 196 197 #define TPM_ST_CLEAR 0x0001 198 #define TPM_ST_STATE 0x0002 199 #define TPM_ST_DEACTIVATED 0x0003 200 201 #define TPM_PP_CMD_ENABLE 0x0020 202 #define TPM_PP_PRESENT 0x0008 203 #define TPM_PP_NOT_PRESENT_LOCK 0x0014 204 205 /* TPM command error codes */ 206 #define TPM_INVALID_POSTINIT 0x26 207 #define TPM_BAD_LOCALITY 0x3d 208 209 /* TPM command tags */ 210 #define TPM_TAG_RQU_CMD 0x00c1 211 #define TPM_TAG_RQU_AUTH1_CMD 0x00c2 212 #define TPM_TAG_RQU_AUTH2_CMD 0x00c3 213 214 struct tpm_req_header { 215 u16 tag; 216 u32 totlen; 217 u32 ordinal; 218 } PACKED; 219 220 struct tpm_rsp_header { 221 u16 tag; 222 u32 totlen; 223 u32 errcode; 224 } PACKED; 225 226 struct tpm_req_extend { 227 struct tpm_req_header hdr; 228 u32 pcrindex; 229 u8 digest[SHA1_BUFSIZE]; 230 } PACKED; 231 232 struct tpm_rsp_extend { 233 struct tpm_rsp_header hdr; 234 u8 digest[SHA1_BUFSIZE]; 235 } PACKED; 236 237 struct tpm_req_getcap { 238 struct tpm_req_header hdr; 239 u32 capArea; 240 u32 subCapSize; 241 u32 subCap; 242 } PACKED; 243 244 #define TPM_CAP_FLAG 0x04 245 #define TPM_CAP_PROPERTY 0x05 246 #define TPM_CAP_FLAG_PERMANENT 0x108 247 #define TPM_CAP_FLAG_VOLATILE 0x109 248 #define TPM_CAP_PROP_OWNER 0x111 249 #define TPM_CAP_PROP_TIS_TIMEOUT 0x115 250 #define TPM_CAP_PROP_DURATION 0x120 251 252 struct tpm_permanent_flags { 253 u16 tag; 254 u8 flags[20]; 255 } PACKED; 256 257 enum permFlagsIndex { 258 PERM_FLAG_IDX_DISABLE = 0, 259 PERM_FLAG_IDX_OWNERSHIP, 260 PERM_FLAG_IDX_DEACTIVATED, 261 PERM_FLAG_IDX_READPUBEK, 262 PERM_FLAG_IDX_DISABLEOWNERCLEAR, 263 PERM_FLAG_IDX_ALLOW_MAINTENANCE, 264 PERM_FLAG_IDX_PHYSICAL_PRESENCE_LIFETIME_LOCK, 265 PERM_FLAG_IDX_PHYSICAL_PRESENCE_HW_ENABLE, 266 PERM_FLAG_IDX_PHYSICAL_PRESENCE_CMD_ENABLE, 267 }; 268 269 struct tpm_res_getcap_perm_flags { 270 struct tpm_rsp_header hdr; 271 u32 size; 272 struct tpm_permanent_flags perm_flags; 273 } PACKED; 274 275 struct tpm_stclear_flags { 276 u16 tag; 277 u8 flags[5]; 278 } PACKED; 279 280 #define STCLEAR_FLAG_IDX_DEACTIVATED 0 281 #define STCLEAR_FLAG_IDX_DISABLE_FORCE_CLEAR 1 282 #define STCLEAR_FLAG_IDX_PHYSICAL_PRESENCE 2 283 #define STCLEAR_FLAG_IDX_PHYSICAL_PRESENCE_LOCK 3 284 #define STCLEAR_FLAG_IDX_GLOBAL_LOCK 4 285 286 struct tpm_res_getcap_stclear_flags { 287 struct tpm_rsp_header hdr; 288 u32 size; 289 struct tpm_stclear_flags stclear_flags; 290 } PACKED; 291 292 struct tpm_res_getcap_ownerauth { 293 struct tpm_rsp_header hdr; 294 u32 size; 295 u8 flag; 296 } PACKED; 297 298 struct tpm_res_getcap_timeouts { 299 struct tpm_rsp_header hdr; 300 u32 size; 301 u32 timeouts[4]; 302 } PACKED; 303 304 struct tpm_res_getcap_durations { 305 struct tpm_rsp_header hdr; 306 u32 size; 307 u32 durations[3]; 308 } PACKED; 309 310 struct tpm_res_sha1start { 311 struct tpm_rsp_header hdr; 312 u32 max_num_bytes; 313 } PACKED; 314 315 struct tpm_res_sha1complete { 316 struct tpm_rsp_header hdr; 317 u8 hash[20]; 318 } PACKED; 319 320 321 /**************************************************************** 322 * TPM v2.0 hardware commands 323 ****************************************************************/ 324 325 #define TPM2_NO 0 326 #define TPM2_YES 1 327 328 #define TPM2_SU_CLEAR 0x0000 329 #define TPM2_SU_STATE 0x0001 330 331 #define TPM2_RH_OWNER 0x40000001 332 #define TPM2_RS_PW 0x40000009 333 #define TPM2_RH_ENDORSEMENT 0x4000000b 334 #define TPM2_RH_PLATFORM 0x4000000c 335 336 #define TPM2_ALG_SHA1 0x0004 337 #define TPM2_ALG_SHA256 0x000b 338 #define TPM2_ALG_SHA384 0x000c 339 #define TPM2_ALG_SHA512 0x000d 340 #define TPM2_ALG_SM3_256 0x0012 341 #define TPM2_ALG_SHA3_256 0x0027 342 #define TPM2_ALG_SHA3_384 0x0028 343 #define TPM2_ALG_SHA3_512 0x0029 344 345 #define TPM2_ALG_SHA1_FLAG (1 << 0) 346 #define TPM2_ALG_SHA256_FLAG (1 << 1) 347 #define TPM2_ALG_SHA384_FLAG (1 << 2) 348 #define TPM2_ALG_SHA512_FLAG (1 << 3) 349 #define TPM2_ALG_SM3_256_FLAG (1 << 4) 350 #define TPM2_ALG_SHA3_256_FLAG (1 << 5) 351 #define TPM2_ALG_SHA3_384_FLAG (1 << 6) 352 #define TPM2_ALG_SHA3_512_FLAG (1 << 7) 353 354 /* TPM 2 command tags */ 355 #define TPM2_ST_NO_SESSIONS 0x8001 356 #define TPM2_ST_SESSIONS 0x8002 357 358 /* TPM 2 commands */ 359 #define TPM2_CC_HierarchyControl 0x121 360 #define TPM2_CC_Clear 0x126 361 #define TPM2_CC_ClearControl 0x127 362 #define TPM2_CC_HierarchyChangeAuth 0x129 363 #define TPM2_CC_PCR_Allocate 0x12b 364 #define TPM2_CC_SelfTest 0x143 365 #define TPM2_CC_Startup 0x144 366 #define TPM2_CC_Shutdown 0x145 367 #define TPM2_CC_StirRandom 0x146 368 #define TPM2_CC_GetCapability 0x17a 369 #define TPM2_CC_GetRandom 0x17b 370 #define TPM2_CC_PCR_Extend 0x182 371 372 /* TPM 2 error codes */ 373 #define TPM2_RC_INITIALIZE 0x100 374 375 /* TPM 2 Capabilities */ 376 #define TPM2_CAP_PCRS 0x00000005 377 378 /* TPM 2 data structures */ 379 380 struct tpm2_req_stirrandom { 381 struct tpm_req_header hdr; 382 u16 size; 383 u64 stir; 384 } PACKED; 385 386 struct tpm2_req_getrandom { 387 struct tpm_req_header hdr; 388 u16 bytesRequested; 389 } PACKED; 390 391 struct tpm2b_20 { 392 u16 size; 393 u8 buffer[20]; 394 } PACKED; 395 396 struct tpm2_res_getrandom { 397 struct tpm_rsp_header hdr; 398 struct tpm2b_20 rnd; 399 } PACKED; 400 401 struct tpm2_authblock { 402 u32 handle; 403 u16 noncesize; /* always 0 */ 404 u8 contsession; /* always TPM2_YES */ 405 u16 pwdsize; /* always 0 */ 406 } PACKED; 407 408 struct tpm2_req_hierarchychangeauth { 409 struct tpm_req_header hdr; 410 u32 authhandle; 411 u32 authblocksize; 412 struct tpm2_authblock authblock; 413 struct tpm2b_20 newAuth; 414 } PACKED; 415 416 struct tpm2_req_extend { 417 struct tpm_req_header hdr; 418 u32 pcrindex; 419 u32 authblocksize; 420 struct tpm2_authblock authblock; 421 u8 digest[0]; 422 } PACKED; 423 424 struct tpm2_req_clearcontrol { 425 struct tpm_req_header hdr; 426 u32 authhandle; 427 u32 authblocksize; 428 struct tpm2_authblock authblock; 429 u8 disable; 430 } PACKED; 431 432 struct tpm2_req_clear { 433 struct tpm_req_header hdr; 434 u32 authhandle; 435 u32 authblocksize; 436 struct tpm2_authblock authblock; 437 } PACKED; 438 439 struct tpm2_req_hierarchycontrol { 440 struct tpm_req_header hdr; 441 u32 authhandle; 442 u32 authblocksize; 443 struct tpm2_authblock authblock; 444 u32 enable; 445 u8 state; 446 } PACKED; 447 448 struct tpm2_req_getcapability { 449 struct tpm_req_header hdr; 450 u32 capability; 451 u32 property; 452 u32 propertycount; 453 } PACKED; 454 455 struct tpm2_res_getcapability { 456 struct tpm_rsp_header hdr; 457 u8 moreData; 458 u32 capability; 459 u8 data[0]; /* capability dependent data */ 460 } PACKED; 461 462 struct tpm2_req_pcr_allocate { 463 struct tpm_req_header hdr; 464 u32 authhandle; 465 u32 authblocksize; 466 struct tpm2_authblock authblock; 467 u32 count; 468 u8 tpms_pcr_selections[4]; 469 } PACKED; 470 471 struct tpms_pcr_selection { 472 u16 hashAlg; 473 u8 sizeOfSelect; 474 u8 pcrSelect[0]; 475 } PACKED; 476 477 struct tpml_pcr_selection { 478 u32 count; 479 struct tpms_pcr_selection selections[0]; 480 } PACKED; 481 482 483 /**************************************************************** 484 * ACPI TCPA table interface 485 ****************************************************************/ 486 487 /* event types: 10.4.1 / table 11 */ 488 #define EV_POST_CODE 1 489 #define EV_NO_ACTION 3 490 #define EV_SEPARATOR 4 491 #define EV_ACTION 5 492 #define EV_EVENT_TAG 6 493 #define EV_COMPACT_HASH 12 494 #define EV_IPL 13 495 #define EV_IPL_PARTITION_DATA 14 496 497 struct tpm2_digest_value { 498 u16 hashAlg; 499 u8 hash[0]; /* size depends on hashAlg */ 500 } PACKED; 501 502 struct tpm2_digest_values { 503 u32 count; 504 struct tpm2_digest_value digest[0]; 505 } PACKED; 506 507 // Each entry in the TPM log contains: a tpm_log_header, a variable 508 // length digest, a tpm_log_trailer, and a variable length event. The 509 // 'digest' matches what is sent to the TPM hardware via the Extend 510 // command. On TPM1.2 the digest is a SHA1 hash; on TPM2.0 the digest 511 // contains a tpm2_digest_values struct followed by a variable number 512 // of tpm2_digest_value structs (as specified by the hardware via the 513 // TPM2_CAP_PCRS request). 514 struct tpm_log_header { 515 u32 pcrindex; 516 u32 eventtype; 517 u8 digest[0]; 518 } PACKED; 519 520 struct tpm_log_trailer { 521 u32 eventdatasize; 522 u8 event[0]; 523 } PACKED; 524 525 struct TCG_EfiSpecIdEventStruct { 526 u8 signature[16]; 527 u32 platformClass; 528 u8 specVersionMinor; 529 u8 specVersionMajor; 530 u8 specErrata; 531 u8 uintnSize; 532 u32 numberOfAlgorithms; 533 struct TCG_EfiSpecIdEventAlgorithmSize { 534 u16 algorithmId; 535 u16 digestSize; 536 } digestSizes[]; 537 /* 538 u8 vendorInfoSize; 539 u8 vendorInfo[0]; 540 */ 541 } PACKED; 542 543 #define TPM_TCPA_ACPI_CLASS_CLIENT 0 544 545 struct pcctes 546 { 547 u32 eventid; 548 u32 eventdatasize; 549 u8 digest[SHA1_BUFSIZE]; 550 } PACKED; 551 552 struct pcctes_romex 553 { 554 u32 eventid; 555 u32 eventdatasize; 556 u16 reserved; 557 u16 pfa; 558 u8 digest[SHA1_BUFSIZE]; 559 } PACKED; 560 561 562 /**************************************************************** 563 * Physical presence interface 564 ****************************************************************/ 565 566 #define TPM_STATE_ENABLED 1 567 #define TPM_STATE_ACTIVE 2 568 #define TPM_STATE_OWNED 4 569 #define TPM_STATE_OWNERINSTALL 8 570 571 #define TPM_PPI_OP_NOOP 0 572 #define TPM_PPI_OP_ENABLE 1 573 #define TPM_PPI_OP_DISABLE 2 574 #define TPM_PPI_OP_ACTIVATE 3 575 #define TPM_PPI_OP_DEACTIVATE 4 576 #define TPM_PPI_OP_CLEAR 5 577 #define TPM_PPI_OP_SET_OWNERINSTALL_TRUE 8 578 #define TPM_PPI_OP_SET_OWNERINSTALL_FALSE 9 579 580 #endif // tcg.h 581