1 /* 2 * (C) Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 24 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ 25 26 #define MXC_CCM_BASE CCM_BASE_ADDR 27 28 /* DPLL register mapping structure */ 29 struct mxc_pll_reg { 30 u32 ctrl; 31 u32 config; 32 u32 op; 33 u32 mfd; 34 u32 mfn; 35 u32 mfn_minus; 36 u32 mfn_plus; 37 u32 hfs_op; 38 u32 hfs_mfd; 39 u32 hfs_mfn; 40 u32 mfn_togc; 41 u32 destat; 42 }; 43 44 /* Register maping of CCM*/ 45 struct mxc_ccm_reg { 46 u32 ccr; /* 0x0000 */ 47 u32 ccdr; 48 u32 csr; 49 u32 ccsr; 50 u32 cacrr; /* 0x0010*/ 51 u32 cbcdr; 52 u32 cbcmr; 53 u32 cscmr1; 54 u32 cscmr2; /* 0x0020 */ 55 u32 cscdr1; 56 u32 cs1cdr; 57 u32 cs2cdr; 58 u32 cdcdr; /* 0x0030 */ 59 u32 chscdr; 60 u32 cscdr2; 61 u32 cscdr3; 62 u32 cscdr4; /* 0x0040 */ 63 u32 cwdr; 64 u32 cdhipr; 65 u32 cdcr; 66 u32 ctor; /* 0x0050 */ 67 u32 clpcr; 68 u32 cisr; 69 u32 cimr; 70 u32 ccosr; /* 0x0060 */ 71 u32 cgpr; 72 u32 CCGR0; 73 u32 CCGR1; 74 u32 CCGR2; /* 0x0070 */ 75 u32 CCGR3; 76 u32 CCGR4; 77 u32 CCGR5; 78 u32 CCGR6; /* 0x0080 */ 79 u32 cmeor; 80 }; 81 82 /* Define the bits in register CACRR */ 83 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 84 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 85 86 /* Define the bits in register CBCDR */ 87 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) 88 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) 89 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 90 #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) 91 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 92 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) 93 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 94 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) 95 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 96 #define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) 97 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 98 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 99 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 100 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 101 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 102 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) 103 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 104 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) 105 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 106 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 107 108 /* Define the bits in register CSCMR1 */ 109 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 110 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) 111 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 112 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) 113 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 114 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) 115 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 116 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) 117 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 118 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) 119 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 120 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 121 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 122 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 123 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 124 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 125 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 126 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 127 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 128 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 129 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) 130 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) 131 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 132 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) 133 #define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) 134 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) 135 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 136 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) 137 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 138 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) 139 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) 140 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 141 142 /* Define the bits in register CSCDR2 */ 143 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 144 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) 145 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 146 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) 147 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 148 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) 149 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 150 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) 151 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 152 #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) 153 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 154 #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F 155 156 /* Define the bits in register CBCMR */ 157 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 158 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 159 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 160 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) 161 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 162 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) 163 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 164 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) 165 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 166 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) 167 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 168 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) 169 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) 170 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) 171 172 /* Define the bits in register CSCDR1 */ 173 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 174 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 175 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 176 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 177 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 178 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 179 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 180 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) 181 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 182 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) 183 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 184 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 185 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 186 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 187 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 188 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) 189 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 190 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 191 192 #endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ 193