1 /** @file 2 SMM profile internal header file. 3 4 Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 7 **/ 8 9 #ifndef _SMM_PROFILE_INTERNAL_H_ 10 #define _SMM_PROFILE_INTERNAL_H_ 11 12 #include <Protocol/SmmReadyToLock.h> 13 #include <Library/UefiRuntimeServicesTableLib.h> 14 #include <Library/DxeServicesTableLib.h> 15 #include <Library/CpuLib.h> 16 #include <IndustryStandard/Acpi.h> 17 18 #include "SmmProfileArch.h" 19 20 // 21 // Configure the SMM_PROFILE DTS region size 22 // 23 #define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M 24 25 #define MAX_PF_PAGE_COUNT 0x2 26 27 #define PEBS_RECORD_NUMBER 0x2 28 29 #define MAX_PF_ENTRY_COUNT 10 30 31 // 32 // This MACRO just enable unit test for the profile 33 // Please disable it. 34 // 35 36 #define IA32_PF_EC_ID (1u << 4) 37 38 #define SMM_PROFILE_NAME L"SmmProfileData" 39 40 // 41 // CPU generic definition 42 // 43 #define CPUID1_EDX_XD_SUPPORT 0x100000 44 #define MSR_EFER 0xc0000080 45 #define MSR_EFER_XD 0x800 46 47 #define CPUID1_EDX_BTS_AVAILABLE 0x200000 48 49 #define DR6_SINGLE_STEP 0x4000 50 #define RFLAG_TF 0x100 51 52 #define MSR_DEBUG_CTL 0x1D9 53 #define MSR_DEBUG_CTL_LBR 0x1 54 #define MSR_DEBUG_CTL_TR 0x40 55 #define MSR_DEBUG_CTL_BTS 0x80 56 #define MSR_DEBUG_CTL_BTINT 0x100 57 #define MSR_DS_AREA 0x600 58 59 #define HEAP_GUARD_NONSTOP_MODE \ 60 ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6) 61 62 #define NULL_DETECTION_NONSTOP_MODE \ 63 ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6) 64 65 typedef struct { 66 EFI_PHYSICAL_ADDRESS Base; 67 EFI_PHYSICAL_ADDRESS Top; 68 } MEMORY_RANGE; 69 70 typedef struct { 71 MEMORY_RANGE Range; 72 BOOLEAN Present; 73 BOOLEAN Nx; 74 } MEMORY_PROTECTION_RANGE; 75 76 typedef struct { 77 UINT64 HeaderSize; 78 UINT64 MaxDataEntries; 79 UINT64 MaxDataSize; 80 UINT64 CurDataEntries; 81 UINT64 CurDataSize; 82 UINT64 TsegStart; 83 UINT64 TsegSize; 84 UINT64 NumSmis; 85 UINT64 NumCpus; 86 } SMM_PROFILE_HEADER; 87 88 typedef struct { 89 UINT64 SmiNum; 90 UINT64 CpuNum; 91 UINT64 ApicId; 92 UINT64 ErrorCode; 93 UINT64 Instruction; 94 UINT64 Address; 95 UINT64 SmiCmd; 96 } SMM_PROFILE_ENTRY; 97 98 extern SMM_S3_RESUME_STATE *mSmmS3ResumeState; 99 extern UINTN gSmiExceptionHandlers[]; 100 extern BOOLEAN mXdSupported; 101 X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; 102 extern UINTN *mPFEntryCount; 103 extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT]; 104 extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT]; 105 106 // 107 // Internal functions 108 // 109 110 /** 111 Update IDT table to replace page fault handler and INT 1 handler. 112 113 **/ 114 VOID 115 InitIdtr ( 116 VOID 117 ); 118 119 /** 120 Check if the memory address will be mapped by 4KB-page. 121 122 @param Address The address of Memory. 123 124 **/ 125 BOOLEAN 126 IsAddressSplit ( 127 IN EFI_PHYSICAL_ADDRESS Address 128 ); 129 130 /** 131 Check if the memory address will be mapped by 4KB-page. 132 133 @param Address The address of Memory. 134 @param Nx The flag indicates if the memory is execute-disable. 135 136 **/ 137 BOOLEAN 138 IsAddressValid ( 139 IN EFI_PHYSICAL_ADDRESS Address, 140 IN BOOLEAN *Nx 141 ); 142 143 /** 144 Page Fault handler for SMM use. 145 146 **/ 147 VOID 148 SmiDefaultPFHandler ( 149 VOID 150 ); 151 152 /** 153 Clear TF in FLAGS. 154 155 @param SystemContext A pointer to the processor context when 156 the interrupt occurred on the processor. 157 158 **/ 159 VOID 160 ClearTrapFlag ( 161 IN OUT EFI_SYSTEM_CONTEXT SystemContext 162 ); 163 164 #endif // _SMM_PROFILE_H_ 165