1 #ifndef BIOS_PCI_H
2 #define BIOS_PCI_H
3
4 #include "ioport.h"
5
pci_config_writel(uint16_t bdf,uint32_t addr,uint32_t val)6 static inline void pci_config_writel(uint16_t bdf, uint32_t addr, uint32_t val)
7 {
8 outl(0xcf8, 0x80000000 | (bdf << 8) | (addr & 0xfc));
9 outl(0xcfc, val);
10 }
11
pci_config_writew(uint16_t bdf,uint32_t addr,uint16_t val)12 static inline void pci_config_writew(uint16_t bdf, uint32_t addr, uint16_t val)
13 {
14 outl(0xcf8, 0x80000000 | (bdf << 8) | (addr & 0xfc));
15 outw(0xcfc | (addr & 2), val);
16 }
17
pci_config_writeb(uint16_t bdf,uint32_t addr,uint8_t val)18 static inline void pci_config_writeb(uint16_t bdf, uint32_t addr, uint8_t val)
19 {
20 outl(0xcf8, 0x80000000 | (bdf << 8) | (addr & 0xfc));
21 outb(0xcfc | (addr & 3), val);
22 }
23
pci_config_readl(uint16_t bdf,uint32_t addr)24 static inline uint32_t pci_config_readl(uint16_t bdf, uint32_t addr)
25 {
26 outl(0xcf8, 0x80000000 | (bdf << 8) | (addr & 0xfc));
27 return inl(0xcfc);
28 }
29
pci_config_readw(uint16_t bdf,uint32_t addr)30 static inline uint16_t pci_config_readw(uint16_t bdf, uint32_t addr)
31 {
32 outl(0xcf8, 0x80000000 | (bdf << 8) | (addr & 0xfc));
33 return inw(0xcfc | (addr & 2));
34 }
35
pci_config_readb(uint16_t bdf,uint32_t addr)36 static inline uint8_t pci_config_readb(uint16_t bdf, uint32_t addr)
37 {
38 outl(0xcf8, 0x80000000 | (bdf << 8) | (addr & 0xfc));
39 return inb(0xcfc | (addr & 3));
40 }
41
42 #define PCI_VENDOR_ID 0x00
43 #define PCI_DEVICE_ID 0x02
44 #define PCI_COMMAND 0x04
45 #define PCI_CLASS_DEVICE 0x0a
46 #define PCI_HEADER_TYPE 0x0e
47 #define PCI_PRIMARY_BUS 0x18
48 #define PCI_SECONDARY_BUS 0x19
49 #define PCI_SUBORDINATE_BUS 0x1a
50 #define PCI_INTERRUPT_LINE 0x3c
51 #define PCI_INTERRUPT_PIN 0x3d
52 #define PCI_BRIDGE_CONTROL 0x3e
53
54 /* PCI_COMMAND */
55 #define PCI_COMMAND_DIS_INTX 0x400
56
57 /* PCI_CLASS_DEVICE */
58 #define PCI_CLASS_STORAGE_IDE 0x0101
59 #define PCI_CLASS_BRIDGE_PCI 0x0604
60
61 /* PCI_HEADER_TYPE */
62 #define PCI_HEADER_TYPE_BRIDGE 1
63 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
64
65 /* PCI_BRIDGE_CONTROL */
66 #define PCI_BRIDGE_CTL_SERR 0x02
67
68 /* PCI_VENDOR_ID / PCI_DEVICE_ID */
69 #define PCI_VENDOR_ID_INTEL 0x8086
70 #define PCI_DEVICE_ID_INTEL_82441 0x1237
71 #define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
72 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
73 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
74
75 #define PCIE_MMCONFIG_BASE 0xb0000000
76 #define PCIE_MMCONFIG_SIZE (256 * 1024 * 1024)
77
78 #endif
79